091d453222
A nested exception condition arises when a second exception is triggered while delivering the first exception. Most nested exceptions can be handled serially but some are converted into a double fault. If an exception is generated during delivery of a double fault then the virtual machine shuts down as a result of a triple fault. vm_exit_intinfo() is used to record that a VM-exit happened while an event was being delivered through the IDT. If an exception is triggered while handling the VM-exit it will be treated like a nested exception. vm_entry_intinfo() is used by processor-specific code to get the event to be injected into the guest on the next VM-entry. This function is responsible for deciding the disposition of nested exceptions.
921 lines
25 KiB
C
921 lines
25 KiB
C
/*-
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* Copyright (c) 2014 Neel Natu <neel@freebsd.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/_iovec.h>
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#include <sys/mman.h>
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#include <x86/psl.h>
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#include <x86/segments.h>
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#include <x86/specialreg.h>
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#include <machine/vmm.h>
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#include <machine/vmm_instruction_emul.h>
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#include <stdbool.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <assert.h>
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#include <errno.h>
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#include <vmmapi.h>
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#include "bhyverun.h"
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/*
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* Various functions in this file use 0 to denote success and VMEXIT_ABORT
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* or VMEXIT_RESTART to denote failure. This assumes that the VMEXIT_xyz
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* macros expand to non-zero values. Enforce this with a compile-time
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* assertion.
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*/
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CTASSERT(VMEXIT_ABORT != 0);
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CTASSERT(VMEXIT_RESTART != 0);
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/*
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* Using 'struct i386tss' is tempting but causes myriad sign extension
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* issues because all of its fields are defined as signed integers.
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*/
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struct tss32 {
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uint16_t tss_link;
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uint16_t rsvd1;
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uint32_t tss_esp0;
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uint16_t tss_ss0;
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uint16_t rsvd2;
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uint32_t tss_esp1;
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uint16_t tss_ss1;
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uint16_t rsvd3;
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uint32_t tss_esp2;
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uint16_t tss_ss2;
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uint16_t rsvd4;
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uint32_t tss_cr3;
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uint32_t tss_eip;
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uint32_t tss_eflags;
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uint32_t tss_eax;
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uint32_t tss_ecx;
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uint32_t tss_edx;
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uint32_t tss_ebx;
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uint32_t tss_esp;
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uint32_t tss_ebp;
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uint32_t tss_esi;
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uint32_t tss_edi;
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uint16_t tss_es;
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uint16_t rsvd5;
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uint16_t tss_cs;
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uint16_t rsvd6;
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uint16_t tss_ss;
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uint16_t rsvd7;
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uint16_t tss_ds;
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uint16_t rsvd8;
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uint16_t tss_fs;
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uint16_t rsvd9;
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uint16_t tss_gs;
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uint16_t rsvd10;
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uint16_t tss_ldt;
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uint16_t rsvd11;
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uint16_t tss_trap;
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uint16_t tss_iomap;
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};
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CTASSERT(sizeof(struct tss32) == 104);
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#define SEL_START(sel) (((sel) & ~0x7))
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#define SEL_LIMIT(sel) (((sel) | 0x7))
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#define TSS_BUSY(type) (((type) & 0x2) != 0)
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static uint64_t
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GETREG(struct vmctx *ctx, int vcpu, int reg)
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{
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uint64_t val;
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int error;
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error = vm_get_register(ctx, vcpu, reg, &val);
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assert(error == 0);
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return (val);
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}
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static void
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SETREG(struct vmctx *ctx, int vcpu, int reg, uint64_t val)
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{
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int error;
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error = vm_set_register(ctx, vcpu, reg, val);
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assert(error == 0);
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}
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static struct seg_desc
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usd_to_seg_desc(struct user_segment_descriptor *usd)
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{
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struct seg_desc seg_desc;
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seg_desc.base = (u_int)USD_GETBASE(usd);
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if (usd->sd_gran)
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seg_desc.limit = (u_int)(USD_GETLIMIT(usd) << 12) | 0xfff;
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else
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seg_desc.limit = (u_int)USD_GETLIMIT(usd);
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seg_desc.access = usd->sd_type | usd->sd_dpl << 5 | usd->sd_p << 7;
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seg_desc.access |= usd->sd_xx << 12;
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seg_desc.access |= usd->sd_def32 << 14;
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seg_desc.access |= usd->sd_gran << 15;
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return (seg_desc);
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}
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/*
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* Inject an exception with an error code that is a segment selector.
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* The format of the error code is described in section 6.13, "Error Code",
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* Intel SDM volume 3.
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*
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* Bit 0 (EXT) denotes whether the exception occurred during delivery
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* of an external event like an interrupt.
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*
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* Bit 1 (IDT) indicates whether the selector points to a gate descriptor
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* in the IDT.
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*
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* Bit 2(GDT/LDT) has the usual interpretation of Table Indicator (TI).
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*/
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static void
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sel_exception(struct vmctx *ctx, int vcpu, int vector, uint16_t sel, int ext)
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{
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int error;
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/*
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* Bit 2 from the selector is retained as-is in the error code.
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*
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* Bit 1 can be safely cleared because none of the selectors
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* encountered during task switch emulation refer to a task
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* gate in the IDT.
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*
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* Bit 0 is set depending on the value of 'ext'.
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*/
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sel &= ~0x3;
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if (ext)
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sel |= 0x1;
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error = vm_inject_exception2(ctx, vcpu, vector, sel);
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assert(error == 0);
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}
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static int
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desc_table_limit_check(struct vmctx *ctx, int vcpu, uint16_t sel)
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{
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uint64_t base;
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uint32_t limit, access;
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int error, reg;
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reg = ISLDT(sel) ? VM_REG_GUEST_LDTR : VM_REG_GUEST_GDTR;
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error = vm_get_desc(ctx, vcpu, reg, &base, &limit, &access);
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assert(error == 0);
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if (reg == VM_REG_GUEST_LDTR) {
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if (SEG_DESC_UNUSABLE(access) || !SEG_DESC_PRESENT(access))
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return (-1);
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}
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if (limit < SEL_LIMIT(sel))
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return (-1);
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else
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return (0);
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}
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static int
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desc_table_rw(struct vmctx *ctx, int vcpu, struct vm_guest_paging *paging,
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uint16_t sel, struct user_segment_descriptor *desc, bool doread)
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{
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struct iovec iov[2];
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uint64_t base;
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uint32_t limit, access;
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int error, reg;
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reg = ISLDT(sel) ? VM_REG_GUEST_LDTR : VM_REG_GUEST_GDTR;
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error = vm_get_desc(ctx, vcpu, reg, &base, &limit, &access);
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assert(error == 0);
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assert(limit >= SEL_LIMIT(sel));
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error = vm_gla2gpa(ctx, vcpu, paging, base + SEL_START(sel),
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sizeof(*desc), doread ? PROT_READ : PROT_WRITE, iov, nitems(iov));
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if (error == 0) {
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if (doread)
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vm_copyin(ctx, vcpu, iov, desc, sizeof(*desc));
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else
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vm_copyout(ctx, vcpu, desc, iov, sizeof(*desc));
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}
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return (error);
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}
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static int
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desc_table_read(struct vmctx *ctx, int vcpu, struct vm_guest_paging *paging,
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uint16_t sel, struct user_segment_descriptor *desc)
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{
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return (desc_table_rw(ctx, vcpu, paging, sel, desc, true));
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}
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static int
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desc_table_write(struct vmctx *ctx, int vcpu, struct vm_guest_paging *paging,
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uint16_t sel, struct user_segment_descriptor *desc)
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{
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return (desc_table_rw(ctx, vcpu, paging, sel, desc, false));
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}
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static int
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read_tss_descriptor(struct vmctx *ctx, int vcpu, struct vm_task_switch *ts,
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uint16_t sel, struct user_segment_descriptor *desc)
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{
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struct vm_guest_paging sup_paging;
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int error;
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assert(!ISLDT(sel));
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assert(IDXSEL(sel) != 0);
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/* Fetch the new TSS descriptor */
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if (desc_table_limit_check(ctx, vcpu, sel)) {
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if (ts->reason == TSR_IRET)
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sel_exception(ctx, vcpu, IDT_TS, sel, ts->ext);
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else
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sel_exception(ctx, vcpu, IDT_GP, sel, ts->ext);
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return (VMEXIT_RESTART);
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}
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sup_paging = ts->paging;
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sup_paging.cpl = 0; /* implicit supervisor mode */
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error = desc_table_read(ctx, vcpu, &sup_paging, sel, desc);
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if (error < 0)
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return (VMEXIT_ABORT);
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else if (error > 0)
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return (VMEXIT_RESTART);
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else
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return (0);
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}
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static bool
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code_desc(int sd_type)
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{
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/* code descriptor */
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return ((sd_type & 0x18) == 0x18);
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}
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static bool
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stack_desc(int sd_type)
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{
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/* writable data descriptor */
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return ((sd_type & 0x1A) == 0x12);
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}
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static bool
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data_desc(int sd_type)
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{
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/* data descriptor or a readable code descriptor */
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return ((sd_type & 0x18) == 0x10 || (sd_type & 0x1A) == 0x1A);
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}
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static bool
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ldt_desc(int sd_type)
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{
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return (sd_type == SDT_SYSLDT);
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}
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static int
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validate_seg_desc(struct vmctx *ctx, int vcpu, struct vm_task_switch *ts,
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int segment, struct seg_desc *seg_desc)
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{
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struct vm_guest_paging sup_paging;
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struct user_segment_descriptor usd;
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int error, idtvec;
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int cpl, dpl, rpl;
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uint16_t sel, cs;
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bool ldtseg, codeseg, stackseg, dataseg, conforming;
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ldtseg = codeseg = stackseg = dataseg = false;
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switch (segment) {
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case VM_REG_GUEST_LDTR:
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ldtseg = true;
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break;
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case VM_REG_GUEST_CS:
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codeseg = true;
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break;
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case VM_REG_GUEST_SS:
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stackseg = true;
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break;
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case VM_REG_GUEST_DS:
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case VM_REG_GUEST_ES:
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case VM_REG_GUEST_FS:
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case VM_REG_GUEST_GS:
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dataseg = true;
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break;
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default:
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assert(0);
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}
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/* Get the segment selector */
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sel = GETREG(ctx, vcpu, segment);
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/* LDT selector must point into the GDT */
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if (ldtseg && ISLDT(sel)) {
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sel_exception(ctx, vcpu, IDT_TS, sel, ts->ext);
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return (VMEXIT_RESTART);
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}
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/* Descriptor table limit check */
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if (desc_table_limit_check(ctx, vcpu, sel)) {
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sel_exception(ctx, vcpu, IDT_TS, sel, ts->ext);
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return (VMEXIT_RESTART);
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}
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/* NULL selector */
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if (IDXSEL(sel) == 0) {
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/* Code and stack segment selectors cannot be NULL */
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if (codeseg || stackseg) {
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sel_exception(ctx, vcpu, IDT_TS, sel, ts->ext);
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return (VMEXIT_RESTART);
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}
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seg_desc->base = 0;
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seg_desc->limit = 0;
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seg_desc->access = 0x10000; /* unusable */
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return (0);
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}
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/* Read the descriptor from the GDT/LDT */
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sup_paging = ts->paging;
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sup_paging.cpl = 0; /* implicit supervisor mode */
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error = desc_table_read(ctx, vcpu, &sup_paging, sel, &usd);
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if (error < 0)
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return (VMEXIT_ABORT);
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else if (error > 0)
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return (VMEXIT_RESTART);
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/* Verify that the descriptor type is compatible with the segment */
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if ((ldtseg && !ldt_desc(usd.sd_type)) ||
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(codeseg && !code_desc(usd.sd_type)) ||
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(dataseg && !data_desc(usd.sd_type)) ||
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(stackseg && !stack_desc(usd.sd_type))) {
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sel_exception(ctx, vcpu, IDT_TS, sel, ts->ext);
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return (VMEXIT_RESTART);
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}
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/* Segment must be marked present */
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if (!usd.sd_p) {
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if (ldtseg)
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idtvec = IDT_TS;
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else if (stackseg)
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idtvec = IDT_SS;
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else
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idtvec = IDT_NP;
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sel_exception(ctx, vcpu, idtvec, sel, ts->ext);
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return (VMEXIT_RESTART);
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}
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cs = GETREG(ctx, vcpu, VM_REG_GUEST_CS);
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cpl = cs & SEL_RPL_MASK;
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rpl = sel & SEL_RPL_MASK;
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dpl = usd.sd_dpl;
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if (stackseg && (rpl != cpl || dpl != cpl)) {
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sel_exception(ctx, vcpu, IDT_TS, sel, ts->ext);
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return (VMEXIT_RESTART);
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}
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if (codeseg) {
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conforming = (usd.sd_type & 0x4) ? true : false;
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if ((conforming && (cpl < dpl)) ||
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(!conforming && (cpl != dpl))) {
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sel_exception(ctx, vcpu, IDT_TS, sel, ts->ext);
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return (VMEXIT_RESTART);
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}
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}
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if (dataseg) {
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/*
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* A data segment is always non-conforming except when it's
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* descriptor is a readable, conforming code segment.
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*/
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if (code_desc(usd.sd_type) && (usd.sd_type & 0x4) != 0)
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conforming = true;
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else
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conforming = false;
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if (!conforming && (rpl > dpl || cpl > dpl)) {
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sel_exception(ctx, vcpu, IDT_TS, sel, ts->ext);
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return (VMEXIT_RESTART);
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}
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}
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*seg_desc = usd_to_seg_desc(&usd);
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return (0);
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}
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static void
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tss32_save(struct vmctx *ctx, int vcpu, struct vm_task_switch *task_switch,
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uint32_t eip, struct tss32 *tss, struct iovec *iov)
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{
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/* General purpose registers */
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tss->tss_eax = GETREG(ctx, vcpu, VM_REG_GUEST_RAX);
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tss->tss_ecx = GETREG(ctx, vcpu, VM_REG_GUEST_RCX);
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tss->tss_edx = GETREG(ctx, vcpu, VM_REG_GUEST_RDX);
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tss->tss_ebx = GETREG(ctx, vcpu, VM_REG_GUEST_RBX);
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tss->tss_esp = GETREG(ctx, vcpu, VM_REG_GUEST_RSP);
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tss->tss_ebp = GETREG(ctx, vcpu, VM_REG_GUEST_RBP);
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tss->tss_esi = GETREG(ctx, vcpu, VM_REG_GUEST_RSI);
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tss->tss_edi = GETREG(ctx, vcpu, VM_REG_GUEST_RDI);
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/* Segment selectors */
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tss->tss_es = GETREG(ctx, vcpu, VM_REG_GUEST_ES);
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tss->tss_cs = GETREG(ctx, vcpu, VM_REG_GUEST_CS);
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tss->tss_ss = GETREG(ctx, vcpu, VM_REG_GUEST_SS);
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tss->tss_ds = GETREG(ctx, vcpu, VM_REG_GUEST_DS);
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tss->tss_fs = GETREG(ctx, vcpu, VM_REG_GUEST_FS);
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tss->tss_gs = GETREG(ctx, vcpu, VM_REG_GUEST_GS);
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/* eflags and eip */
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tss->tss_eflags = GETREG(ctx, vcpu, VM_REG_GUEST_RFLAGS);
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if (task_switch->reason == TSR_IRET)
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tss->tss_eflags &= ~PSL_NT;
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tss->tss_eip = eip;
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/* Copy updated old TSS into guest memory */
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vm_copyout(ctx, vcpu, tss, iov, sizeof(struct tss32));
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}
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|
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static void
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update_seg_desc(struct vmctx *ctx, int vcpu, int reg, struct seg_desc *sd)
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{
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int error;
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error = vm_set_desc(ctx, vcpu, reg, sd->base, sd->limit, sd->access);
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assert(error == 0);
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}
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static int
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tss32_restore(struct vmctx *ctx, int vcpu, struct vm_task_switch *ts,
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uint16_t ot_sel, struct tss32 *tss, struct iovec *iov)
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|
{
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|
struct seg_desc seg_desc, seg_desc2;
|
|
uint64_t *pdpte, maxphyaddr, reserved;
|
|
uint32_t eflags;
|
|
int error, i;
|
|
bool nested;
|
|
|
|
nested = false;
|
|
if (ts->reason != TSR_IRET && ts->reason != TSR_JMP) {
|
|
tss->tss_link = ot_sel;
|
|
nested = true;
|
|
}
|
|
|
|
eflags = tss->tss_eflags;
|
|
if (nested)
|
|
eflags |= PSL_NT;
|
|
|
|
/* LDTR */
|
|
SETREG(ctx, vcpu, VM_REG_GUEST_LDTR, tss->tss_ldt);
|
|
|
|
/* PBDR */
|
|
if (ts->paging.paging_mode != PAGING_MODE_FLAT) {
|
|
if (ts->paging.paging_mode == PAGING_MODE_PAE) {
|
|
/*
|
|
* XXX Assuming 36-bit MAXPHYADDR.
|
|
*/
|
|
maxphyaddr = (1UL << 36) - 1;
|
|
pdpte = paddr_guest2host(ctx, tss->tss_cr3 & ~0x1f, 32);
|
|
for (i = 0; i < 4; i++) {
|
|
/* Check reserved bits if the PDPTE is valid */
|
|
if (!(pdpte[i] & 0x1))
|
|
continue;
|
|
/*
|
|
* Bits 2:1, 8:5 and bits above the processor's
|
|
* maximum physical address are reserved.
|
|
*/
|
|
reserved = ~maxphyaddr | 0x1E6;
|
|
if (pdpte[i] & reserved) {
|
|
error = vm_inject_exception2(ctx, vcpu,
|
|
IDT_GP, 0);
|
|
assert(error == 0);
|
|
return (VMEXIT_RESTART);
|
|
}
|
|
}
|
|
SETREG(ctx, vcpu, VM_REG_GUEST_PDPTE0, pdpte[0]);
|
|
SETREG(ctx, vcpu, VM_REG_GUEST_PDPTE1, pdpte[1]);
|
|
SETREG(ctx, vcpu, VM_REG_GUEST_PDPTE2, pdpte[2]);
|
|
SETREG(ctx, vcpu, VM_REG_GUEST_PDPTE3, pdpte[3]);
|
|
}
|
|
SETREG(ctx, vcpu, VM_REG_GUEST_CR3, tss->tss_cr3);
|
|
ts->paging.cr3 = tss->tss_cr3;
|
|
}
|
|
|
|
/* eflags and eip */
|
|
SETREG(ctx, vcpu, VM_REG_GUEST_RFLAGS, eflags);
|
|
SETREG(ctx, vcpu, VM_REG_GUEST_RIP, tss->tss_eip);
|
|
|
|
/* General purpose registers */
|
|
SETREG(ctx, vcpu, VM_REG_GUEST_RAX, tss->tss_eax);
|
|
SETREG(ctx, vcpu, VM_REG_GUEST_RCX, tss->tss_ecx);
|
|
SETREG(ctx, vcpu, VM_REG_GUEST_RDX, tss->tss_edx);
|
|
SETREG(ctx, vcpu, VM_REG_GUEST_RBX, tss->tss_ebx);
|
|
SETREG(ctx, vcpu, VM_REG_GUEST_RSP, tss->tss_esp);
|
|
SETREG(ctx, vcpu, VM_REG_GUEST_RBP, tss->tss_ebp);
|
|
SETREG(ctx, vcpu, VM_REG_GUEST_RSI, tss->tss_esi);
|
|
SETREG(ctx, vcpu, VM_REG_GUEST_RDI, tss->tss_edi);
|
|
|
|
/* Segment selectors */
|
|
SETREG(ctx, vcpu, VM_REG_GUEST_ES, tss->tss_es);
|
|
SETREG(ctx, vcpu, VM_REG_GUEST_CS, tss->tss_cs);
|
|
SETREG(ctx, vcpu, VM_REG_GUEST_SS, tss->tss_ss);
|
|
SETREG(ctx, vcpu, VM_REG_GUEST_DS, tss->tss_ds);
|
|
SETREG(ctx, vcpu, VM_REG_GUEST_FS, tss->tss_fs);
|
|
SETREG(ctx, vcpu, VM_REG_GUEST_GS, tss->tss_gs);
|
|
|
|
/*
|
|
* If this is a nested task then write out the new TSS to update
|
|
* the previous link field.
|
|
*/
|
|
if (nested)
|
|
vm_copyout(ctx, vcpu, tss, iov, sizeof(*tss));
|
|
|
|
/* Validate segment descriptors */
|
|
error = validate_seg_desc(ctx, vcpu, ts, VM_REG_GUEST_LDTR, &seg_desc);
|
|
if (error)
|
|
return (error);
|
|
update_seg_desc(ctx, vcpu, VM_REG_GUEST_LDTR, &seg_desc);
|
|
|
|
/*
|
|
* Section "Checks on Guest Segment Registers", Intel SDM, Vol 3.
|
|
*
|
|
* The SS and CS attribute checks on VM-entry are inter-dependent so
|
|
* we need to make sure that both segments are valid before updating
|
|
* either of them. This ensures that the VMCS state can pass the
|
|
* VM-entry checks so the guest can handle any exception injected
|
|
* during task switch emulation.
|
|
*/
|
|
error = validate_seg_desc(ctx, vcpu, ts, VM_REG_GUEST_CS, &seg_desc);
|
|
if (error)
|
|
return (error);
|
|
error = validate_seg_desc(ctx, vcpu, ts, VM_REG_GUEST_SS, &seg_desc2);
|
|
if (error)
|
|
return (error);
|
|
update_seg_desc(ctx, vcpu, VM_REG_GUEST_CS, &seg_desc);
|
|
update_seg_desc(ctx, vcpu, VM_REG_GUEST_SS, &seg_desc2);
|
|
ts->paging.cpl = tss->tss_cs & SEL_RPL_MASK;
|
|
|
|
error = validate_seg_desc(ctx, vcpu, ts, VM_REG_GUEST_DS, &seg_desc);
|
|
if (error)
|
|
return (error);
|
|
update_seg_desc(ctx, vcpu, VM_REG_GUEST_DS, &seg_desc);
|
|
|
|
error = validate_seg_desc(ctx, vcpu, ts, VM_REG_GUEST_ES, &seg_desc);
|
|
if (error)
|
|
return (error);
|
|
update_seg_desc(ctx, vcpu, VM_REG_GUEST_ES, &seg_desc);
|
|
|
|
error = validate_seg_desc(ctx, vcpu, ts, VM_REG_GUEST_FS, &seg_desc);
|
|
if (error)
|
|
return (error);
|
|
update_seg_desc(ctx, vcpu, VM_REG_GUEST_FS, &seg_desc);
|
|
|
|
error = validate_seg_desc(ctx, vcpu, ts, VM_REG_GUEST_GS, &seg_desc);
|
|
if (error)
|
|
return (error);
|
|
update_seg_desc(ctx, vcpu, VM_REG_GUEST_GS, &seg_desc);
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
push_errcode(struct vmctx *ctx, int vcpu, struct vm_guest_paging *paging,
|
|
int task_type, uint32_t errcode)
|
|
{
|
|
struct iovec iov[2];
|
|
struct seg_desc seg_desc;
|
|
int stacksize, bytes, error;
|
|
uint64_t gla, cr0, rflags;
|
|
uint32_t esp;
|
|
uint16_t stacksel;
|
|
|
|
cr0 = GETREG(ctx, vcpu, VM_REG_GUEST_CR0);
|
|
rflags = GETREG(ctx, vcpu, VM_REG_GUEST_RFLAGS);
|
|
stacksel = GETREG(ctx, vcpu, VM_REG_GUEST_SS);
|
|
|
|
error = vm_get_desc(ctx, vcpu, VM_REG_GUEST_SS, &seg_desc.base,
|
|
&seg_desc.limit, &seg_desc.access);
|
|
assert(error == 0);
|
|
|
|
/*
|
|
* Section "Error Code" in the Intel SDM vol 3: the error code is
|
|
* pushed on the stack as a doubleword or word (depending on the
|
|
* default interrupt, trap or task gate size).
|
|
*/
|
|
if (task_type == SDT_SYS386BSY || task_type == SDT_SYS386TSS)
|
|
bytes = 4;
|
|
else
|
|
bytes = 2;
|
|
|
|
/*
|
|
* PUSH instruction from Intel SDM vol 2: the 'B' flag in the
|
|
* stack-segment descriptor determines the size of the stack
|
|
* pointer outside of 64-bit mode.
|
|
*/
|
|
if (SEG_DESC_DEF32(seg_desc.access))
|
|
stacksize = 4;
|
|
else
|
|
stacksize = 2;
|
|
|
|
esp = GETREG(ctx, vcpu, VM_REG_GUEST_RSP);
|
|
esp -= bytes;
|
|
|
|
if (vie_calculate_gla(paging->cpu_mode, VM_REG_GUEST_SS,
|
|
&seg_desc, esp, bytes, stacksize, PROT_WRITE, &gla)) {
|
|
sel_exception(ctx, vcpu, IDT_SS, stacksel, 1);
|
|
return (VMEXIT_RESTART);
|
|
}
|
|
|
|
if (vie_alignment_check(paging->cpl, bytes, cr0, rflags, gla)) {
|
|
error = vm_inject_exception2(ctx, vcpu, IDT_AC, 1);
|
|
assert(error == 0);
|
|
return (VMEXIT_RESTART);
|
|
}
|
|
|
|
error = vm_gla2gpa(ctx, vcpu, paging, gla, bytes, PROT_WRITE,
|
|
iov, nitems(iov));
|
|
assert(error == 0 || error == 1 || error == -1);
|
|
if (error) {
|
|
return ((error == 1) ? VMEXIT_RESTART : VMEXIT_ABORT);
|
|
}
|
|
|
|
vm_copyout(ctx, vcpu, &errcode, iov, bytes);
|
|
SETREG(ctx, vcpu, VM_REG_GUEST_RSP, esp);
|
|
return (0);
|
|
}
|
|
|
|
int
|
|
vmexit_task_switch(struct vmctx *ctx, struct vm_exit *vmexit, int *pvcpu)
|
|
{
|
|
struct seg_desc nt;
|
|
struct tss32 oldtss, newtss;
|
|
struct vm_task_switch *task_switch;
|
|
struct vm_guest_paging *paging, sup_paging;
|
|
struct user_segment_descriptor nt_desc, ot_desc;
|
|
struct iovec nt_iov[2], ot_iov[2];
|
|
uint64_t cr0, ot_base;
|
|
uint32_t eip, ot_lim, access;
|
|
int error, ext, minlimit, nt_type, ot_type, vcpu;
|
|
enum task_switch_reason reason;
|
|
uint16_t nt_sel, ot_sel;
|
|
|
|
task_switch = &vmexit->u.task_switch;
|
|
nt_sel = task_switch->tsssel;
|
|
ext = vmexit->u.task_switch.ext;
|
|
reason = vmexit->u.task_switch.reason;
|
|
paging = &vmexit->u.task_switch.paging;
|
|
vcpu = *pvcpu;
|
|
|
|
assert(paging->cpu_mode == CPU_MODE_PROTECTED);
|
|
|
|
/*
|
|
* Section 4.6, "Access Rights" in Intel SDM Vol 3.
|
|
* The following page table accesses are implicitly supervisor mode:
|
|
* - accesses to GDT or LDT to load segment descriptors
|
|
* - accesses to the task state segment during task switch
|
|
*/
|
|
sup_paging = *paging;
|
|
sup_paging.cpl = 0; /* implicit supervisor mode */
|
|
|
|
/* Fetch the new TSS descriptor */
|
|
error = read_tss_descriptor(ctx, vcpu, task_switch, nt_sel, &nt_desc);
|
|
if (error)
|
|
return (error);
|
|
|
|
nt = usd_to_seg_desc(&nt_desc);
|
|
|
|
/* Verify the type of the new TSS */
|
|
nt_type = SEG_DESC_TYPE(nt.access);
|
|
if (nt_type != SDT_SYS386BSY && nt_type != SDT_SYS386TSS &&
|
|
nt_type != SDT_SYS286BSY && nt_type != SDT_SYS286TSS) {
|
|
sel_exception(ctx, vcpu, IDT_TS, nt_sel, ext);
|
|
return (VMEXIT_RESTART);
|
|
}
|
|
|
|
/* TSS descriptor must have present bit set */
|
|
if (!SEG_DESC_PRESENT(nt.access)) {
|
|
sel_exception(ctx, vcpu, IDT_NP, nt_sel, ext);
|
|
return (VMEXIT_RESTART);
|
|
}
|
|
|
|
/*
|
|
* TSS must have a minimum length of 104 bytes for a 32-bit TSS and
|
|
* 44 bytes for a 16-bit TSS.
|
|
*/
|
|
if (nt_type == SDT_SYS386BSY || nt_type == SDT_SYS386TSS)
|
|
minlimit = 104 - 1;
|
|
else if (nt_type == SDT_SYS286BSY || nt_type == SDT_SYS286TSS)
|
|
minlimit = 44 - 1;
|
|
else
|
|
minlimit = 0;
|
|
|
|
assert(minlimit > 0);
|
|
if (nt.limit < minlimit) {
|
|
sel_exception(ctx, vcpu, IDT_TS, nt_sel, ext);
|
|
return (VMEXIT_RESTART);
|
|
}
|
|
|
|
/* TSS must be busy if task switch is due to IRET */
|
|
if (reason == TSR_IRET && !TSS_BUSY(nt_type)) {
|
|
sel_exception(ctx, vcpu, IDT_TS, nt_sel, ext);
|
|
return (VMEXIT_RESTART);
|
|
}
|
|
|
|
/*
|
|
* TSS must be available (not busy) if task switch reason is
|
|
* CALL, JMP, exception or interrupt.
|
|
*/
|
|
if (reason != TSR_IRET && TSS_BUSY(nt_type)) {
|
|
sel_exception(ctx, vcpu, IDT_GP, nt_sel, ext);
|
|
return (VMEXIT_RESTART);
|
|
}
|
|
|
|
/* Fetch the new TSS */
|
|
error = vm_gla2gpa(ctx, vcpu, &sup_paging, nt.base, minlimit + 1,
|
|
PROT_READ | PROT_WRITE, nt_iov, nitems(nt_iov));
|
|
if (error == 1) {
|
|
/* Restart vcpu execution to handle the page fault */
|
|
return (VMEXIT_RESTART);
|
|
} else if (error == -1) {
|
|
return (VMEXIT_ABORT);
|
|
} else {
|
|
assert(error == 0);
|
|
vm_copyin(ctx, vcpu, nt_iov, &newtss, minlimit + 1);
|
|
}
|
|
|
|
/* Get the old TSS selector from the guest's task register */
|
|
ot_sel = GETREG(ctx, vcpu, VM_REG_GUEST_TR);
|
|
if (ISLDT(ot_sel) || IDXSEL(ot_sel) == 0) {
|
|
/*
|
|
* This might happen if a task switch was attempted without
|
|
* ever loading the task register with LTR. In this case the
|
|
* TR would contain the values from power-on:
|
|
* (sel = 0, base = 0, limit = 0xffff).
|
|
*/
|
|
sel_exception(ctx, vcpu, IDT_TS, ot_sel, task_switch->ext);
|
|
return (VMEXIT_RESTART);
|
|
}
|
|
|
|
/* Get the old TSS base and limit from the guest's task register */
|
|
error = vm_get_desc(ctx, vcpu, VM_REG_GUEST_TR, &ot_base, &ot_lim,
|
|
&access);
|
|
assert(error == 0);
|
|
assert(!SEG_DESC_UNUSABLE(access) && SEG_DESC_PRESENT(access));
|
|
ot_type = SEG_DESC_TYPE(access);
|
|
assert(ot_type == SDT_SYS386BSY || ot_type == SDT_SYS286BSY);
|
|
|
|
/* Fetch the old TSS descriptor */
|
|
error = read_tss_descriptor(ctx, vcpu, task_switch, ot_sel,
|
|
&ot_desc);
|
|
if (error)
|
|
return (error);
|
|
|
|
/* Get the old TSS */
|
|
error = vm_gla2gpa(ctx, vcpu, &sup_paging, ot_base, minlimit + 1,
|
|
PROT_READ | PROT_WRITE, ot_iov, nitems(ot_iov));
|
|
if (error == 1) {
|
|
/* Restart vcpu execution to handle the page fault */
|
|
return (VMEXIT_RESTART);
|
|
} else if (error == -1) {
|
|
fprintf(stderr, "Error copying in old TSS: %d\n", errno);
|
|
return (VMEXIT_ABORT);
|
|
} else {
|
|
assert(error == 0);
|
|
vm_copyin(ctx, vcpu, ot_iov, &oldtss, minlimit + 1);
|
|
}
|
|
|
|
/*
|
|
* Clear the busy bit in the old TSS descriptor if the task switch
|
|
* due to an IRET or JMP instruction.
|
|
*/
|
|
if (reason == TSR_IRET || reason == TSR_JMP) {
|
|
ot_desc.sd_type &= ~0x2;
|
|
error = desc_table_write(ctx, vcpu, &sup_paging, ot_sel,
|
|
&ot_desc);
|
|
if (error)
|
|
return (error);
|
|
}
|
|
|
|
if (nt_type == SDT_SYS286BSY || nt_type == SDT_SYS286TSS) {
|
|
fprintf(stderr, "Task switch to 16-bit TSS not supported\n");
|
|
return (VMEXIT_ABORT);
|
|
}
|
|
|
|
/* Save processor state in old TSS */
|
|
eip = vmexit->rip + vmexit->inst_length;
|
|
tss32_save(ctx, vcpu, task_switch, eip, &oldtss, ot_iov);
|
|
|
|
/*
|
|
* If the task switch was triggered for any reason other than IRET
|
|
* then set the busy bit in the new TSS descriptor.
|
|
*/
|
|
if (reason != TSR_IRET) {
|
|
nt_desc.sd_type |= 0x2;
|
|
error = desc_table_write(ctx, vcpu, &sup_paging, nt_sel,
|
|
&nt_desc);
|
|
if (error)
|
|
return (error);
|
|
}
|
|
|
|
/* Update task register to point at the new TSS */
|
|
SETREG(ctx, vcpu, VM_REG_GUEST_TR, nt_sel);
|
|
|
|
/* Update the hidden descriptor state of the task register */
|
|
nt = usd_to_seg_desc(&nt_desc);
|
|
update_seg_desc(ctx, vcpu, VM_REG_GUEST_TR, &nt);
|
|
|
|
/* Set CR0.TS */
|
|
cr0 = GETREG(ctx, vcpu, VM_REG_GUEST_CR0);
|
|
SETREG(ctx, vcpu, VM_REG_GUEST_CR0, cr0 | CR0_TS);
|
|
|
|
/*
|
|
* We are now committed to the task switch. Any exceptions encountered
|
|
* after this point will be handled in the context of the new task and
|
|
* the saved instruction pointer will belong to the new task.
|
|
*/
|
|
vmexit->rip = newtss.tss_eip;
|
|
vmexit->inst_length = 0;
|
|
|
|
/* Load processor state from new TSS */
|
|
error = tss32_restore(ctx, vcpu, task_switch, ot_sel, &newtss, nt_iov);
|
|
if (error)
|
|
return (error);
|
|
|
|
/*
|
|
* Section "Interrupt Tasks" in Intel SDM, Vol 3: if an exception
|
|
* caused an error code to be generated, this error code is copied
|
|
* to the stack of the new task.
|
|
*/
|
|
if (task_switch->errcode_valid) {
|
|
assert(task_switch->ext);
|
|
assert(task_switch->reason == TSR_IDT_GATE);
|
|
error = push_errcode(ctx, vcpu, &task_switch->paging, nt_type,
|
|
task_switch->errcode);
|
|
if (error) {
|
|
return (error);
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Treatment of virtual-NMI blocking if NMI is delivered through
|
|
* a task gate.
|
|
*
|
|
* Section "Architectural State Before A VM Exit", Intel SDM, Vol3:
|
|
* If the virtual NMIs VM-execution control is 1, VM entry injects
|
|
* an NMI, and delivery of the NMI causes a task switch that causes
|
|
* a VM exit, virtual-NMI blocking is in effect before the VM exit
|
|
* commences.
|
|
*
|
|
* Thus, virtual-NMI blocking is in effect at the time of the task
|
|
* switch VM exit.
|
|
*/
|
|
|
|
/*
|
|
* Treatment of virtual-NMI unblocking on IRET from NMI handler task.
|
|
*
|
|
* Section "Changes to Instruction Behavior in VMX Non-Root Operation"
|
|
* If "virtual NMIs" control is 1 IRET removes any virtual-NMI blocking.
|
|
* This unblocking of virtual-NMI occurs even if IRET causes a fault.
|
|
*
|
|
* Thus, virtual-NMI blocking is cleared at the time of the task switch
|
|
* VM exit.
|
|
*/
|
|
|
|
/*
|
|
* If the task switch was triggered by an event delivered through
|
|
* the IDT then extinguish the pending event from the vcpu's
|
|
* exitintinfo.
|
|
*/
|
|
if (task_switch->reason == TSR_IDT_GATE) {
|
|
error = vm_set_intinfo(ctx, vcpu, 0);
|
|
assert(error == 0);
|
|
}
|
|
|
|
/*
|
|
* XXX should inject debug exception if 'T' bit is 1
|
|
*/
|
|
return (VMEXIT_RESTART);
|
|
}
|