4cb7084e29
Approved by: adrian (mentor, implicit)
1373 lines
35 KiB
C
1373 lines
35 KiB
C
/*-
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* Copyright (c) 2015-2016 Landon Fuller <landon@landonf.org>
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* Copyright (c) 2016 Michael Zhilin <mizhka@gmail.com>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer,
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* without modification.
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* 2. Redistributions in binary form must reproduce at minimum a disclaimer
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* similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
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* redistribution must be conditioned upon including a substantially
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* similar Disclaimer requirement for further binary redistribution.
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*
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* NO WARRANTY
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
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* AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
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* OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
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* IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGES.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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/*
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* Broadcom ChipCommon driver.
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*
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* With the exception of some very early chipsets, the ChipCommon core
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* has been included in all HND SoCs and chipsets based on the siba(4)
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* and bcma(4) interconnects, providing a common interface to chipset
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* identification, bus enumeration, UARTs, clocks, watchdog interrupts,
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* GPIO, flash, etc.
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*/
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#include <sys/param.h>
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#include <sys/kernel.h>
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#include <sys/lock.h>
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#include <sys/bus.h>
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#include <sys/rman.h>
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#include <sys/malloc.h>
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#include <sys/module.h>
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#include <sys/mutex.h>
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#include <sys/systm.h>
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#include <machine/bus.h>
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#include <machine/resource.h>
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#include <dev/bhnd/bhnd.h>
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#include <dev/bhnd/bhndvar.h>
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#include "chipcreg.h"
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#include "chipcvar.h"
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#include "chipc_private.h"
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devclass_t bhnd_chipc_devclass; /**< bhnd(4) chipcommon device class */
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static struct bhnd_device_quirk chipc_quirks[];
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/* Supported device identifiers */
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static const struct bhnd_device chipc_devices[] = {
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BHND_DEVICE(BCM, CC, NULL, chipc_quirks),
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BHND_DEVICE(BCM, 4706_CC, NULL, chipc_quirks),
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BHND_DEVICE_END
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};
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/* Device quirks table */
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static struct bhnd_device_quirk chipc_quirks[] = {
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/* HND OTP controller revisions */
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BHND_CORE_QUIRK (HWREV_EQ (12), CHIPC_QUIRK_OTP_HND), /* (?) */
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BHND_CORE_QUIRK (HWREV_EQ (17), CHIPC_QUIRK_OTP_HND), /* BCM4311 */
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BHND_CORE_QUIRK (HWREV_EQ (22), CHIPC_QUIRK_OTP_HND), /* BCM4312 */
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/* IPX OTP controller revisions */
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BHND_CORE_QUIRK (HWREV_EQ (21), CHIPC_QUIRK_OTP_IPX),
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BHND_CORE_QUIRK (HWREV_GTE(23), CHIPC_QUIRK_OTP_IPX),
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BHND_CORE_QUIRK (HWREV_GTE(32), CHIPC_QUIRK_SUPPORTS_SPROM),
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BHND_CORE_QUIRK (HWREV_GTE(35), CHIPC_QUIRK_SUPPORTS_CAP_EXT),
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BHND_CORE_QUIRK (HWREV_GTE(49), CHIPC_QUIRK_IPX_OTPL_SIZE),
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/* 4706 variant quirks */
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BHND_CORE_QUIRK (HWREV_EQ (38), CHIPC_QUIRK_4706_NFLASH), /* BCM5357? */
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BHND_CHIP_QUIRK (4706, HWREV_ANY, CHIPC_QUIRK_4706_NFLASH),
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/* 4331 quirks*/
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BHND_CHIP_QUIRK (4331, HWREV_ANY, CHIPC_QUIRK_4331_EXTPA_MUX_SPROM),
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BHND_PKG_QUIRK (4331, TN, CHIPC_QUIRK_4331_GPIO2_5_MUX_SPROM),
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BHND_PKG_QUIRK (4331, TNA0, CHIPC_QUIRK_4331_GPIO2_5_MUX_SPROM),
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BHND_PKG_QUIRK (4331, TT, CHIPC_QUIRK_4331_EXTPA2_MUX_SPROM),
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/* 4360 quirks */
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BHND_CHIP_QUIRK (4352, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM),
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BHND_CHIP_QUIRK (43460, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM),
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BHND_CHIP_QUIRK (43462, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM),
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BHND_CHIP_QUIRK (43602, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM),
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BHND_DEVICE_QUIRK_END
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};
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// FIXME: IRQ shouldn't be hard-coded
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#define CHIPC_MIPS_IRQ 2
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static int chipc_add_children(struct chipc_softc *sc);
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static bhnd_nvram_src chipc_find_nvram_src(struct chipc_softc *sc,
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struct chipc_caps *caps);
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static int chipc_read_caps(struct chipc_softc *sc,
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struct chipc_caps *caps);
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static bool chipc_should_enable_muxed_sprom(
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struct chipc_softc *sc);
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static int chipc_enable_otp_power(struct chipc_softc *sc);
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static void chipc_disable_otp_power(struct chipc_softc *sc);
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static int chipc_enable_sprom_pins(struct chipc_softc *sc);
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static void chipc_disable_sprom_pins(struct chipc_softc *sc);
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static int chipc_try_activate_resource(struct chipc_softc *sc,
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device_t child, int type, int rid,
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struct resource *r, bool req_direct);
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static int chipc_init_rman(struct chipc_softc *sc);
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static void chipc_free_rman(struct chipc_softc *sc);
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static struct rman *chipc_get_rman(struct chipc_softc *sc, int type);
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/* quirk and capability flag convenience macros */
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#define CHIPC_QUIRK(_sc, _name) \
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((_sc)->quirks & CHIPC_QUIRK_ ## _name)
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#define CHIPC_CAP(_sc, _name) \
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((_sc)->caps._name)
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#define CHIPC_ASSERT_QUIRK(_sc, name) \
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KASSERT(CHIPC_QUIRK((_sc), name), ("quirk " __STRING(_name) " not set"))
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#define CHIPC_ASSERT_CAP(_sc, name) \
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KASSERT(CHIPC_CAP((_sc), name), ("capability " __STRING(_name) " not set"))
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static int
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chipc_probe(device_t dev)
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{
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const struct bhnd_device *id;
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id = bhnd_device_lookup(dev, chipc_devices, sizeof(chipc_devices[0]));
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if (id == NULL)
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return (ENXIO);
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bhnd_set_default_core_desc(dev);
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return (BUS_PROBE_DEFAULT);
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}
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static int
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chipc_attach(device_t dev)
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{
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struct chipc_softc *sc;
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int error;
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sc = device_get_softc(dev);
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sc->dev = dev;
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sc->quirks = bhnd_device_quirks(dev, chipc_devices,
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sizeof(chipc_devices[0]));
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sc->sprom_refcnt = 0;
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CHIPC_LOCK_INIT(sc);
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STAILQ_INIT(&sc->mem_regions);
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/* Set up resource management */
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if ((error = chipc_init_rman(sc))) {
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device_printf(sc->dev,
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"failed to initialize chipc resource state: %d\n", error);
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goto failed;
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}
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/* Allocate the region containing the chipc register block */
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if ((sc->core_region = chipc_find_region_by_rid(sc, 0)) == NULL) {
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error = ENXIO;
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goto failed;
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}
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error = chipc_retain_region(sc, sc->core_region,
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RF_ALLOCATED|RF_ACTIVE);
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if (error) {
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sc->core_region = NULL;
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goto failed;
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}
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/* Save a direct reference to our chipc registers */
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sc->core = sc->core_region->cr_res;
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/* Fetch and parse capability register(s) */
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if ((error = chipc_read_caps(sc, &sc->caps)))
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goto failed;
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if (bootverbose)
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chipc_print_caps(sc->dev, &sc->caps);
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/* Attach all supported child devices */
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if ((error = chipc_add_children(sc)))
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goto failed;
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if ((error = bus_generic_attach(dev)))
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goto failed;
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return (0);
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failed:
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device_delete_children(sc->dev);
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if (sc->core_region != NULL) {
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chipc_release_region(sc, sc->core_region,
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RF_ALLOCATED|RF_ACTIVE);
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}
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chipc_free_rman(sc);
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CHIPC_LOCK_DESTROY(sc);
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return (error);
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}
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static int
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chipc_detach(device_t dev)
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{
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struct chipc_softc *sc;
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int error;
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sc = device_get_softc(dev);
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if ((error = bus_generic_detach(dev)))
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return (error);
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chipc_release_region(sc, sc->core_region, RF_ALLOCATED|RF_ACTIVE);
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chipc_free_rman(sc);
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CHIPC_LOCK_DESTROY(sc);
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return (0);
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}
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static int
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chipc_add_children(struct chipc_softc *sc)
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{
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device_t child;
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const char *flash_bus;
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int error;
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/* SPROM/OTP */
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if (sc->caps.nvram_src == BHND_NVRAM_SRC_SPROM ||
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sc->caps.nvram_src == BHND_NVRAM_SRC_OTP)
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{
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child = BUS_ADD_CHILD(sc->dev, 0, "bhnd_nvram", -1);
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if (child == NULL) {
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device_printf(sc->dev, "failed to add nvram device\n");
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return (ENXIO);
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}
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/* Both OTP and external SPROM are mapped at CHIPC_SPROM_OTP */
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error = chipc_set_resource(sc, child, SYS_RES_MEMORY, 0,
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CHIPC_SPROM_OTP, CHIPC_SPROM_OTP_SIZE, 0, 0);
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if (error)
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return (error);
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}
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/*
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* PMU/PWR_CTRL
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*
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* On AOB ("Always on Bus") devices, the PMU core (if it exists) is
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* attached directly to the bhnd(4) bus -- not chipc.
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*/
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if (sc->caps.pwr_ctrl || (sc->caps.pmu && !sc->caps.aob)) {
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child = BUS_ADD_CHILD(sc->dev, 0, "bhnd_pmu", -1);
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if (child == NULL) {
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device_printf(sc->dev, "failed to add pmu\n");
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return (ENXIO);
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}
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}
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/* All remaining devices are SoC-only */
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if (bhnd_get_attach_type(sc->dev) != BHND_ATTACH_NATIVE)
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return (0);
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/* UARTs */
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for (u_int i = 0; i < min(sc->caps.num_uarts, CHIPC_UART_MAX); i++) {
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child = BUS_ADD_CHILD(sc->dev, 0, "uart", -1);
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if (child == NULL) {
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device_printf(sc->dev, "failed to add uart%u\n", i);
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return (ENXIO);
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}
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/* Shared IRQ */
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error = bus_set_resource(child, SYS_RES_IRQ, 0, CHIPC_MIPS_IRQ,
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1);
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if (error) {
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device_printf(sc->dev, "failed to set uart%u irq %u\n",
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i, CHIPC_MIPS_IRQ);
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return (error);
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}
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/* UART registers are mapped sequentially */
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error = chipc_set_resource(sc, child, SYS_RES_MEMORY, 0,
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CHIPC_UART(i), CHIPC_UART_SIZE, 0, 0);
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if (error)
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return (error);
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}
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/* Flash */
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flash_bus = chipc_flash_bus_name(sc->caps.flash_type);
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if (flash_bus != NULL) {
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child = BUS_ADD_CHILD(sc->dev, 0, flash_bus, -1);
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if (child == NULL) {
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device_printf(sc->dev, "failed to add %s device\n",
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flash_bus);
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return (ENXIO);
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}
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/* flash memory mapping */
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error = chipc_set_resource(sc, child, SYS_RES_MEMORY, 0,
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0, RM_MAX_END, 1, 1);
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if (error)
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return (error);
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/* flashctrl registers */
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error = chipc_set_resource(sc, child, SYS_RES_MEMORY, 1,
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CHIPC_SFLASH_BASE, CHIPC_SFLASH_SIZE, 0, 0);
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if (error)
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return (error);
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}
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return (0);
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}
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/**
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* Determine the NVRAM data source for this device.
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*
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* The SPROM, OTP, and flash capability flags must be fully populated in
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* @p caps.
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*
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* @param sc chipc driver state.
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* @param caps capability flags to be used to derive NVRAM configuration.
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*/
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static bhnd_nvram_src
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chipc_find_nvram_src(struct chipc_softc *sc, struct chipc_caps *caps)
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{
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uint32_t otp_st, srom_ctrl;
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/*
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* We check for hardware presence in order of precedence. For example,
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* SPROM is is always used in preference to internal OTP if found.
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*/
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if (CHIPC_QUIRK(sc, SUPPORTS_SPROM) && caps->sprom) {
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srom_ctrl = bhnd_bus_read_4(sc->core, CHIPC_SPROM_CTRL);
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if (srom_ctrl & CHIPC_SRC_PRESENT)
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return (BHND_NVRAM_SRC_SPROM);
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}
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/* Check for programmed OTP H/W subregion (contains SROM data) */
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if (CHIPC_QUIRK(sc, SUPPORTS_OTP) && caps->otp_size > 0) {
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/* TODO: need access to HND-OTP device */
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if (!CHIPC_QUIRK(sc, OTP_HND)) {
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device_printf(sc->dev,
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"NVRAM unavailable: unsupported OTP controller.\n");
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return (BHND_NVRAM_SRC_UNKNOWN);
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}
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otp_st = bhnd_bus_read_4(sc->core, CHIPC_OTPST);
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if (otp_st & CHIPC_OTPS_GUP_HW)
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return (BHND_NVRAM_SRC_OTP);
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}
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/* Check for flash */
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if (caps->flash_type != CHIPC_FLASH_NONE)
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return (BHND_NVRAM_SRC_FLASH);
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/* No NVRAM hardware capability declared */
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return (BHND_NVRAM_SRC_UNKNOWN);
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}
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/* Read and parse chipc capabilities */
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static int
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chipc_read_caps(struct chipc_softc *sc, struct chipc_caps *caps)
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{
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uint32_t cap_reg;
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uint32_t cap_ext_reg;
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uint32_t regval;
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/* Fetch cap registers */
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cap_reg = bhnd_bus_read_4(sc->core, CHIPC_CAPABILITIES);
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cap_ext_reg = 0;
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if (CHIPC_QUIRK(sc, SUPPORTS_CAP_EXT))
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cap_ext_reg = bhnd_bus_read_4(sc->core, CHIPC_CAPABILITIES_EXT);
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/* Extract values */
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caps->num_uarts = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_NUM_UART);
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caps->mipseb = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_MIPSEB);
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caps->uart_gpio = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_UARTGPIO);
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caps->uart_clock = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_UCLKSEL);
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caps->extbus_type = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_EXTBUS);
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caps->pwr_ctrl = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_PWR_CTL);
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caps->jtag_master = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_JTAGP);
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caps->pll_type = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_PLL);
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caps->backplane_64 = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_BKPLN64);
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caps->boot_rom = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_ROM);
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caps->pmu = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_PMU);
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caps->eci = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_ECI);
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caps->sprom = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_SPROM);
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caps->otp_size = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_OTP_SIZE);
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caps->seci = CHIPC_GET_FLAG(cap_ext_reg, CHIPC_CAP2_SECI);
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caps->gsio = CHIPC_GET_FLAG(cap_ext_reg, CHIPC_CAP2_GSIO);
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caps->aob = CHIPC_GET_FLAG(cap_ext_reg, CHIPC_CAP2_AOB);
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/* Fetch OTP size for later IPX controller revisions */
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if (CHIPC_QUIRK(sc, IPX_OTPL_SIZE)) {
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regval = bhnd_bus_read_4(sc->core, CHIPC_OTPLAYOUT);
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caps->otp_size = CHIPC_GET_BITS(regval, CHIPC_OTPL_SIZE);
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}
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/* Determine flash type and parameters */
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caps->cfi_width = 0;
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switch (CHIPC_GET_BITS(cap_reg, CHIPC_CAP_FLASH)) {
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case CHIPC_CAP_SFLASH_ST:
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caps->flash_type = CHIPC_SFLASH_ST;
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break;
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case CHIPC_CAP_SFLASH_AT:
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caps->flash_type = CHIPC_SFLASH_AT;
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break;
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case CHIPC_CAP_NFLASH:
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/* unimplemented */
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caps->flash_type = CHIPC_NFLASH;
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break;
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case CHIPC_CAP_PFLASH:
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caps->flash_type = CHIPC_PFLASH_CFI;
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|
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/* determine cfi width */
|
|
regval = bhnd_bus_read_4(sc->core, CHIPC_FLASH_CFG);
|
|
if (CHIPC_GET_FLAG(regval, CHIPC_FLASH_CFG_DS))
|
|
caps->cfi_width = 2;
|
|
else
|
|
caps->cfi_width = 1;
|
|
|
|
break;
|
|
case CHIPC_CAP_FLASH_NONE:
|
|
caps->flash_type = CHIPC_FLASH_NONE;
|
|
break;
|
|
|
|
}
|
|
|
|
/* Handle 4706_NFLASH fallback */
|
|
if (CHIPC_QUIRK(sc, 4706_NFLASH) &&
|
|
CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_4706_NFLASH))
|
|
{
|
|
caps->flash_type = CHIPC_NFLASH_4706;
|
|
}
|
|
|
|
|
|
/* Determine NVRAM source. Must occur after the SPROM/OTP/flash
|
|
* capability flags have been populated. */
|
|
caps->nvram_src = chipc_find_nvram_src(sc, caps);
|
|
|
|
/* Determine the SPROM offset within OTP (if any). SPROM-formatted
|
|
* data is placed within the OTP general use region. */
|
|
caps->sprom_offset = 0;
|
|
if (caps->nvram_src == BHND_NVRAM_SRC_OTP) {
|
|
CHIPC_ASSERT_QUIRK(sc, OTP_IPX);
|
|
|
|
/* Bit offset to GUP HW subregion containing SPROM data */
|
|
regval = bhnd_bus_read_4(sc->core, CHIPC_OTPLAYOUT);
|
|
caps->sprom_offset = CHIPC_GET_BITS(regval, CHIPC_OTPL_GUP);
|
|
|
|
/* Convert to bytes */
|
|
caps->sprom_offset /= 8;
|
|
}
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
chipc_suspend(device_t dev)
|
|
{
|
|
return (bus_generic_suspend(dev));
|
|
}
|
|
|
|
static int
|
|
chipc_resume(device_t dev)
|
|
{
|
|
return (bus_generic_resume(dev));
|
|
}
|
|
|
|
static void
|
|
chipc_probe_nomatch(device_t dev, device_t child)
|
|
{
|
|
struct resource_list *rl;
|
|
const char *name;
|
|
|
|
name = device_get_name(child);
|
|
if (name == NULL)
|
|
name = "unknown device";
|
|
|
|
device_printf(dev, "<%s> at", name);
|
|
|
|
rl = BUS_GET_RESOURCE_LIST(dev, child);
|
|
if (rl != NULL) {
|
|
resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#jx");
|
|
resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%jd");
|
|
}
|
|
|
|
printf(" (no driver attached)\n");
|
|
}
|
|
|
|
static int
|
|
chipc_print_child(device_t dev, device_t child)
|
|
{
|
|
struct resource_list *rl;
|
|
int retval = 0;
|
|
|
|
retval += bus_print_child_header(dev, child);
|
|
|
|
rl = BUS_GET_RESOURCE_LIST(dev, child);
|
|
if (rl != NULL) {
|
|
retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY,
|
|
"%#jx");
|
|
retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ,
|
|
"%jd");
|
|
}
|
|
|
|
retval += bus_print_child_domain(dev, child);
|
|
retval += bus_print_child_footer(dev, child);
|
|
|
|
return (retval);
|
|
}
|
|
|
|
static int
|
|
chipc_child_pnpinfo_str(device_t dev, device_t child, char *buf,
|
|
size_t buflen)
|
|
{
|
|
if (buflen == 0)
|
|
return (EOVERFLOW);
|
|
|
|
*buf = '\0';
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
chipc_child_location_str(device_t dev, device_t child, char *buf,
|
|
size_t buflen)
|
|
{
|
|
if (buflen == 0)
|
|
return (EOVERFLOW);
|
|
|
|
*buf = '\0';
|
|
return (ENXIO);
|
|
}
|
|
|
|
static device_t
|
|
chipc_add_child(device_t dev, u_int order, const char *name, int unit)
|
|
{
|
|
struct chipc_softc *sc;
|
|
struct chipc_devinfo *dinfo;
|
|
device_t child;
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
child = device_add_child_ordered(dev, order, name, unit);
|
|
if (child == NULL)
|
|
return (NULL);
|
|
|
|
dinfo = malloc(sizeof(struct chipc_devinfo), M_BHND, M_NOWAIT);
|
|
if (dinfo == NULL) {
|
|
device_delete_child(dev, child);
|
|
return (NULL);
|
|
}
|
|
|
|
resource_list_init(&dinfo->resources);
|
|
device_set_ivars(child, dinfo);
|
|
|
|
return (child);
|
|
}
|
|
|
|
static void
|
|
chipc_child_deleted(device_t dev, device_t child)
|
|
{
|
|
struct chipc_devinfo *dinfo = device_get_ivars(child);
|
|
|
|
if (dinfo != NULL) {
|
|
resource_list_free(&dinfo->resources);
|
|
free(dinfo, M_BHND);
|
|
}
|
|
|
|
device_set_ivars(child, NULL);
|
|
}
|
|
|
|
static struct resource_list *
|
|
chipc_get_resource_list(device_t dev, device_t child)
|
|
{
|
|
struct chipc_devinfo *dinfo = device_get_ivars(child);
|
|
return (&dinfo->resources);
|
|
}
|
|
|
|
|
|
/* Allocate region records for the given port, and add the port's memory
|
|
* range to the mem_rman */
|
|
static int
|
|
chipc_rman_init_regions (struct chipc_softc *sc, bhnd_port_type type,
|
|
u_int port)
|
|
{
|
|
struct chipc_region *cr;
|
|
rman_res_t start, end;
|
|
u_int num_regions;
|
|
int error;
|
|
|
|
num_regions = bhnd_get_region_count(sc->dev, type, port);
|
|
for (u_int region = 0; region < num_regions; region++) {
|
|
/* Allocate new region record */
|
|
cr = chipc_alloc_region(sc, type, port, region);
|
|
if (cr == NULL)
|
|
return (ENODEV);
|
|
|
|
/* Can't manage regions that cannot be allocated */
|
|
if (cr->cr_rid < 0) {
|
|
BHND_DEBUG_DEV(sc->dev, "no rid for chipc region "
|
|
"%s%u.%u", bhnd_port_type_name(type), port, region);
|
|
chipc_free_region(sc, cr);
|
|
continue;
|
|
}
|
|
|
|
/* Add to rman's managed range */
|
|
start = cr->cr_addr;
|
|
end = cr->cr_end;
|
|
if ((error = rman_manage_region(&sc->mem_rman, start, end))) {
|
|
chipc_free_region(sc, cr);
|
|
return (error);
|
|
}
|
|
|
|
/* Add to region list */
|
|
STAILQ_INSERT_TAIL(&sc->mem_regions, cr, cr_link);
|
|
}
|
|
|
|
return (0);
|
|
}
|
|
|
|
/* Initialize memory state for all chipc port regions */
|
|
static int
|
|
chipc_init_rman(struct chipc_softc *sc)
|
|
{
|
|
u_int num_ports;
|
|
int error;
|
|
|
|
/* Port types for which we'll register chipc_region mappings */
|
|
bhnd_port_type types[] = {
|
|
BHND_PORT_DEVICE
|
|
};
|
|
|
|
/* Initialize resource manager */
|
|
sc->mem_rman.rm_start = 0;
|
|
sc->mem_rman.rm_end = BUS_SPACE_MAXADDR;
|
|
sc->mem_rman.rm_type = RMAN_ARRAY;
|
|
sc->mem_rman.rm_descr = "ChipCommon Device Memory";
|
|
if ((error = rman_init(&sc->mem_rman))) {
|
|
device_printf(sc->dev, "could not initialize mem_rman: %d\n",
|
|
error);
|
|
return (error);
|
|
}
|
|
|
|
/* Populate per-port-region state */
|
|
for (u_int i = 0; i < nitems(types); i++) {
|
|
num_ports = bhnd_get_port_count(sc->dev, types[i]);
|
|
for (u_int port = 0; port < num_ports; port++) {
|
|
error = chipc_rman_init_regions(sc, types[i], port);
|
|
if (error) {
|
|
device_printf(sc->dev,
|
|
"region init failed for %s%u: %d\n",
|
|
bhnd_port_type_name(types[i]), port,
|
|
error);
|
|
|
|
goto failed;
|
|
}
|
|
}
|
|
}
|
|
|
|
return (0);
|
|
|
|
failed:
|
|
chipc_free_rman(sc);
|
|
return (error);
|
|
}
|
|
|
|
/* Free memory management state */
|
|
static void
|
|
chipc_free_rman(struct chipc_softc *sc)
|
|
{
|
|
struct chipc_region *cr, *cr_next;
|
|
|
|
STAILQ_FOREACH_SAFE(cr, &sc->mem_regions, cr_link, cr_next)
|
|
chipc_free_region(sc, cr);
|
|
|
|
rman_fini(&sc->mem_rman);
|
|
}
|
|
|
|
/**
|
|
* Return the rman instance for a given resource @p type, if any.
|
|
*
|
|
* @param sc The chipc device state.
|
|
* @param type The resource type (e.g. SYS_RES_MEMORY, SYS_RES_IRQ, ...)
|
|
*/
|
|
static struct rman *
|
|
chipc_get_rman(struct chipc_softc *sc, int type)
|
|
{
|
|
switch (type) {
|
|
case SYS_RES_MEMORY:
|
|
return (&sc->mem_rman);
|
|
|
|
case SYS_RES_IRQ:
|
|
/* IRQs can be used with RF_SHAREABLE, so we don't perform
|
|
* any local proxying of resource requests. */
|
|
return (NULL);
|
|
|
|
default:
|
|
return (NULL);
|
|
};
|
|
}
|
|
|
|
static struct resource *
|
|
chipc_alloc_resource(device_t dev, device_t child, int type,
|
|
int *rid, rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
|
|
{
|
|
struct chipc_softc *sc;
|
|
struct chipc_region *cr;
|
|
struct resource_list_entry *rle;
|
|
struct resource *rv;
|
|
struct rman *rm;
|
|
int error;
|
|
bool passthrough, isdefault;
|
|
|
|
sc = device_get_softc(dev);
|
|
passthrough = (device_get_parent(child) != dev);
|
|
isdefault = RMAN_IS_DEFAULT_RANGE(start, end);
|
|
rle = NULL;
|
|
|
|
/* Fetch the resource manager, delegate request if necessary */
|
|
rm = chipc_get_rman(sc, type);
|
|
if (rm == NULL) {
|
|
/* Requested resource type is delegated to our parent */
|
|
rv = bus_generic_rl_alloc_resource(dev, child, type, rid,
|
|
start, end, count, flags);
|
|
return (rv);
|
|
}
|
|
|
|
/* Populate defaults */
|
|
if (!passthrough && isdefault) {
|
|
/* Fetch the resource list entry. */
|
|
rle = resource_list_find(BUS_GET_RESOURCE_LIST(dev, child),
|
|
type, *rid);
|
|
if (rle == NULL) {
|
|
device_printf(dev,
|
|
"default resource %#x type %d for child %s "
|
|
"not found\n", *rid, type,
|
|
device_get_nameunit(child));
|
|
return (NULL);
|
|
}
|
|
|
|
if (rle->res != NULL) {
|
|
device_printf(dev,
|
|
"resource entry %#x type %d for child %s is busy "
|
|
"[%d]\n",
|
|
*rid, type, device_get_nameunit(child),
|
|
rman_get_flags(rle->res));
|
|
|
|
return (NULL);
|
|
}
|
|
|
|
start = rle->start;
|
|
end = rle->end;
|
|
count = ulmax(count, rle->count);
|
|
}
|
|
|
|
/* Locate a mapping region */
|
|
if ((cr = chipc_find_region(sc, start, end)) == NULL) {
|
|
/* Resource requests outside our shared port regions can be
|
|
* delegated to our parent. */
|
|
rv = bus_generic_rl_alloc_resource(dev, child, type, rid,
|
|
start, end, count, flags);
|
|
return (rv);
|
|
}
|
|
|
|
/* Try to retain a region reference */
|
|
if ((error = chipc_retain_region(sc, cr, RF_ALLOCATED)))
|
|
return (NULL);
|
|
|
|
/* Make our rman reservation */
|
|
rv = rman_reserve_resource(rm, start, end, count, flags & ~RF_ACTIVE,
|
|
child);
|
|
if (rv == NULL) {
|
|
chipc_release_region(sc, cr, RF_ALLOCATED);
|
|
return (NULL);
|
|
}
|
|
|
|
rman_set_rid(rv, *rid);
|
|
|
|
/* Activate */
|
|
if (flags & RF_ACTIVE) {
|
|
error = bus_activate_resource(child, type, *rid, rv);
|
|
if (error) {
|
|
device_printf(dev,
|
|
"failed to activate entry %#x type %d for "
|
|
"child %s: %d\n",
|
|
*rid, type, device_get_nameunit(child), error);
|
|
|
|
chipc_release_region(sc, cr, RF_ALLOCATED);
|
|
rman_release_resource(rv);
|
|
|
|
return (NULL);
|
|
}
|
|
}
|
|
|
|
/* Update child's resource list entry */
|
|
if (rle != NULL) {
|
|
rle->res = rv;
|
|
rle->start = rman_get_start(rv);
|
|
rle->end = rman_get_end(rv);
|
|
rle->count = rman_get_size(rv);
|
|
}
|
|
|
|
return (rv);
|
|
}
|
|
|
|
static int
|
|
chipc_release_resource(device_t dev, device_t child, int type, int rid,
|
|
struct resource *r)
|
|
{
|
|
struct chipc_softc *sc;
|
|
struct chipc_region *cr;
|
|
struct rman *rm;
|
|
struct resource_list_entry *rle;
|
|
int error;
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
/* Handled by parent bus? */
|
|
rm = chipc_get_rman(sc, type);
|
|
if (rm == NULL || !rman_is_region_manager(r, rm)) {
|
|
return (bus_generic_rl_release_resource(dev, child, type, rid,
|
|
r));
|
|
}
|
|
|
|
/* Locate the mapping region */
|
|
cr = chipc_find_region(sc, rman_get_start(r), rman_get_end(r));
|
|
if (cr == NULL)
|
|
return (EINVAL);
|
|
|
|
/* Deactivate resources */
|
|
if (rman_get_flags(r) & RF_ACTIVE) {
|
|
error = BUS_DEACTIVATE_RESOURCE(dev, child, type, rid, r);
|
|
if (error)
|
|
return (error);
|
|
}
|
|
|
|
if ((error = rman_release_resource(r)))
|
|
return (error);
|
|
|
|
/* Drop allocation reference */
|
|
chipc_release_region(sc, cr, RF_ALLOCATED);
|
|
|
|
/* Clear reference from the resource list entry if exists */
|
|
rle = resource_list_find(BUS_GET_RESOURCE_LIST(dev, child), type, rid);
|
|
if (rle != NULL)
|
|
rle->res = NULL;
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
chipc_adjust_resource(device_t dev, device_t child, int type,
|
|
struct resource *r, rman_res_t start, rman_res_t end)
|
|
{
|
|
struct chipc_softc *sc;
|
|
struct chipc_region *cr;
|
|
struct rman *rm;
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
/* Handled by parent bus? */
|
|
rm = chipc_get_rman(sc, type);
|
|
if (rm == NULL || !rman_is_region_manager(r, rm)) {
|
|
return (bus_generic_adjust_resource(dev, child, type, r, start,
|
|
end));
|
|
}
|
|
|
|
/* The range is limited to the existing region mapping */
|
|
cr = chipc_find_region(sc, rman_get_start(r), rman_get_end(r));
|
|
if (cr == NULL)
|
|
return (EINVAL);
|
|
|
|
if (end <= start)
|
|
return (EINVAL);
|
|
|
|
if (start < cr->cr_addr || end > cr->cr_end)
|
|
return (EINVAL);
|
|
|
|
/* Range falls within the existing region */
|
|
return (rman_adjust_resource(r, start, end));
|
|
}
|
|
|
|
/**
|
|
* Retain an RF_ACTIVE reference to the region mapping @p r, and
|
|
* configure @p r with its subregion values.
|
|
*
|
|
* @param sc Driver instance state.
|
|
* @param child Requesting child device.
|
|
* @param type resource type of @p r.
|
|
* @param rid resource id of @p r
|
|
* @param r resource to be activated.
|
|
* @param req_direct If true, failure to allocate a direct bhnd resource
|
|
* will be treated as an error. If false, the resource will not be marked
|
|
* as RF_ACTIVE if bhnd direct resource allocation fails.
|
|
*/
|
|
static int
|
|
chipc_try_activate_resource(struct chipc_softc *sc, device_t child, int type,
|
|
int rid, struct resource *r, bool req_direct)
|
|
{
|
|
struct rman *rm;
|
|
struct chipc_region *cr;
|
|
bhnd_size_t cr_offset;
|
|
rman_res_t r_start, r_end, r_size;
|
|
int error;
|
|
|
|
rm = chipc_get_rman(sc, type);
|
|
if (rm == NULL || !rman_is_region_manager(r, rm))
|
|
return (EINVAL);
|
|
|
|
r_start = rman_get_start(r);
|
|
r_end = rman_get_end(r);
|
|
r_size = rman_get_size(r);
|
|
|
|
/* Find the corresponding chipc region */
|
|
cr = chipc_find_region(sc, r_start, r_end);
|
|
if (cr == NULL)
|
|
return (EINVAL);
|
|
|
|
/* Calculate subregion offset within the chipc region */
|
|
cr_offset = r_start - cr->cr_addr;
|
|
|
|
/* Retain (and activate, if necessary) the chipc region */
|
|
if ((error = chipc_retain_region(sc, cr, RF_ACTIVE)))
|
|
return (error);
|
|
|
|
/* Configure child resource with its subregion values. */
|
|
if (cr->cr_res->direct) {
|
|
error = chipc_init_child_resource(r, cr->cr_res->res,
|
|
cr_offset, r_size);
|
|
if (error)
|
|
goto cleanup;
|
|
|
|
/* Mark active */
|
|
if ((error = rman_activate_resource(r)))
|
|
goto cleanup;
|
|
} else if (req_direct) {
|
|
error = ENOMEM;
|
|
goto cleanup;
|
|
}
|
|
|
|
return (0);
|
|
|
|
cleanup:
|
|
chipc_release_region(sc, cr, RF_ACTIVE);
|
|
return (error);
|
|
}
|
|
|
|
static int
|
|
chipc_activate_bhnd_resource(device_t dev, device_t child, int type,
|
|
int rid, struct bhnd_resource *r)
|
|
{
|
|
struct chipc_softc *sc;
|
|
struct rman *rm;
|
|
int error;
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
/* Delegate non-locally managed resources to parent */
|
|
rm = chipc_get_rman(sc, type);
|
|
if (rm == NULL || !rman_is_region_manager(r->res, rm)) {
|
|
return (bhnd_bus_generic_activate_resource(dev, child, type,
|
|
rid, r));
|
|
}
|
|
|
|
/* Try activating the chipc region resource */
|
|
error = chipc_try_activate_resource(sc, child, type, rid, r->res,
|
|
false);
|
|
if (error)
|
|
return (error);
|
|
|
|
/* Mark the child resource as direct according to the returned resource
|
|
* state */
|
|
if (rman_get_flags(r->res) & RF_ACTIVE)
|
|
r->direct = true;
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
chipc_activate_resource(device_t dev, device_t child, int type, int rid,
|
|
struct resource *r)
|
|
{
|
|
struct chipc_softc *sc;
|
|
struct rman *rm;
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
/* Delegate non-locally managed resources to parent */
|
|
rm = chipc_get_rman(sc, type);
|
|
if (rm == NULL || !rman_is_region_manager(r, rm)) {
|
|
return (bus_generic_activate_resource(dev, child, type, rid,
|
|
r));
|
|
}
|
|
|
|
/* Try activating the chipc region-based resource */
|
|
return (chipc_try_activate_resource(sc, child, type, rid, r, true));
|
|
}
|
|
|
|
/**
|
|
* Default bhndb(4) implementation of BUS_DEACTIVATE_RESOURCE().
|
|
*/
|
|
static int
|
|
chipc_deactivate_resource(device_t dev, device_t child, int type,
|
|
int rid, struct resource *r)
|
|
{
|
|
struct chipc_softc *sc;
|
|
struct chipc_region *cr;
|
|
struct rman *rm;
|
|
int error;
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
/* Handled by parent bus? */
|
|
rm = chipc_get_rman(sc, type);
|
|
if (rm == NULL || !rman_is_region_manager(r, rm)) {
|
|
return (bus_generic_deactivate_resource(dev, child, type, rid,
|
|
r));
|
|
}
|
|
|
|
/* Find the corresponding chipc region */
|
|
cr = chipc_find_region(sc, rman_get_start(r), rman_get_end(r));
|
|
if (cr == NULL)
|
|
return (EINVAL);
|
|
|
|
/* Mark inactive */
|
|
if ((error = rman_deactivate_resource(r)))
|
|
return (error);
|
|
|
|
/* Drop associated RF_ACTIVE reference */
|
|
chipc_release_region(sc, cr, RF_ACTIVE);
|
|
|
|
return (0);
|
|
}
|
|
|
|
/**
|
|
* Examine bus state and make a best effort determination of whether it's
|
|
* likely safe to enable the muxed SPROM pins.
|
|
*
|
|
* On devices that do not use SPROM pin muxing, always returns true.
|
|
*
|
|
* @param sc chipc driver state.
|
|
*/
|
|
static bool
|
|
chipc_should_enable_muxed_sprom(struct chipc_softc *sc)
|
|
{
|
|
device_t *devs;
|
|
device_t hostb;
|
|
device_t parent;
|
|
int devcount;
|
|
int error;
|
|
bool result;
|
|
|
|
/* Nothing to do? */
|
|
if (!CHIPC_QUIRK(sc, MUX_SPROM))
|
|
return (true);
|
|
|
|
mtx_lock(&Giant); /* for newbus */
|
|
|
|
parent = device_get_parent(sc->dev);
|
|
hostb = bhnd_find_hostb_device(parent);
|
|
|
|
if ((error = device_get_children(parent, &devs, &devcount))) {
|
|
mtx_unlock(&Giant);
|
|
return (false);
|
|
}
|
|
|
|
/* Reject any active devices other than ChipCommon, or the
|
|
* host bridge (if any). */
|
|
result = true;
|
|
for (int i = 0; i < devcount; i++) {
|
|
if (devs[i] == hostb || devs[i] == sc->dev)
|
|
continue;
|
|
|
|
if (!device_is_attached(devs[i]))
|
|
continue;
|
|
|
|
if (device_is_suspended(devs[i]))
|
|
continue;
|
|
|
|
/* Active device; assume SPROM is busy */
|
|
result = false;
|
|
break;
|
|
}
|
|
|
|
free(devs, M_TEMP);
|
|
mtx_unlock(&Giant);
|
|
return (result);
|
|
}
|
|
|
|
static int
|
|
chipc_enable_sprom(device_t dev)
|
|
{
|
|
struct chipc_softc *sc;
|
|
int error;
|
|
|
|
sc = device_get_softc(dev);
|
|
CHIPC_LOCK(sc);
|
|
|
|
/* Already enabled? */
|
|
if (sc->sprom_refcnt >= 1) {
|
|
sc->sprom_refcnt++;
|
|
CHIPC_UNLOCK(sc);
|
|
|
|
return (0);
|
|
}
|
|
|
|
switch (sc->caps.nvram_src) {
|
|
case BHND_NVRAM_SRC_SPROM:
|
|
error = chipc_enable_sprom_pins(sc);
|
|
break;
|
|
case BHND_NVRAM_SRC_OTP:
|
|
error = chipc_enable_otp_power(sc);
|
|
break;
|
|
default:
|
|
error = 0;
|
|
break;
|
|
}
|
|
|
|
/* Bump the reference count */
|
|
if (error == 0)
|
|
sc->sprom_refcnt++;
|
|
|
|
CHIPC_UNLOCK(sc);
|
|
return (error);
|
|
}
|
|
|
|
static void
|
|
chipc_disable_sprom(device_t dev)
|
|
{
|
|
struct chipc_softc *sc;
|
|
|
|
sc = device_get_softc(dev);
|
|
CHIPC_LOCK(sc);
|
|
|
|
/* Check reference count, skip disable if in-use. */
|
|
KASSERT(sc->sprom_refcnt > 0, ("sprom refcnt overrelease"));
|
|
sc->sprom_refcnt--;
|
|
if (sc->sprom_refcnt > 0) {
|
|
CHIPC_UNLOCK(sc);
|
|
return;
|
|
}
|
|
|
|
switch (sc->caps.nvram_src) {
|
|
case BHND_NVRAM_SRC_SPROM:
|
|
chipc_disable_sprom_pins(sc);
|
|
break;
|
|
case BHND_NVRAM_SRC_OTP:
|
|
chipc_disable_otp_power(sc);
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
|
|
CHIPC_UNLOCK(sc);
|
|
}
|
|
|
|
static int
|
|
chipc_enable_otp_power(struct chipc_softc *sc)
|
|
{
|
|
// TODO: Enable OTP resource via PMU, and wait up to 100 usec for
|
|
// OTPS_READY to be set in `optstatus`.
|
|
return (0);
|
|
}
|
|
|
|
static void
|
|
chipc_disable_otp_power(struct chipc_softc *sc)
|
|
{
|
|
// TODO: Disable OTP resource via PMU
|
|
}
|
|
|
|
/**
|
|
* If required by this device, enable access to the SPROM.
|
|
*
|
|
* @param sc chipc driver state.
|
|
*/
|
|
static int
|
|
chipc_enable_sprom_pins(struct chipc_softc *sc)
|
|
{
|
|
uint32_t cctrl;
|
|
|
|
CHIPC_LOCK_ASSERT(sc, MA_OWNED);
|
|
KASSERT(sc->sprom_refcnt == 0, ("sprom pins already enabled"));
|
|
|
|
/* Nothing to do? */
|
|
if (!CHIPC_QUIRK(sc, MUX_SPROM))
|
|
return (0);
|
|
|
|
/* Check whether bus is busy */
|
|
if (!chipc_should_enable_muxed_sprom(sc))
|
|
return (EBUSY);
|
|
|
|
cctrl = bhnd_bus_read_4(sc->core, CHIPC_CHIPCTRL);
|
|
|
|
/* 4331 devices */
|
|
if (CHIPC_QUIRK(sc, 4331_EXTPA_MUX_SPROM)) {
|
|
cctrl &= ~CHIPC_CCTRL4331_EXTPA_EN;
|
|
|
|
if (CHIPC_QUIRK(sc, 4331_GPIO2_5_MUX_SPROM))
|
|
cctrl &= ~CHIPC_CCTRL4331_EXTPA_ON_GPIO2_5;
|
|
|
|
if (CHIPC_QUIRK(sc, 4331_EXTPA2_MUX_SPROM))
|
|
cctrl &= ~CHIPC_CCTRL4331_EXTPA_EN2;
|
|
|
|
bhnd_bus_write_4(sc->core, CHIPC_CHIPCTRL, cctrl);
|
|
return (0);
|
|
}
|
|
|
|
/* 4360 devices */
|
|
if (CHIPC_QUIRK(sc, 4360_FEM_MUX_SPROM)) {
|
|
/* Unimplemented */
|
|
}
|
|
|
|
/* Refuse to proceed on unsupported devices with muxed SPROM pins */
|
|
device_printf(sc->dev, "muxed sprom lines on unrecognized device\n");
|
|
return (ENXIO);
|
|
}
|
|
|
|
/**
|
|
* If required by this device, revert any GPIO/pin configuration applied
|
|
* to allow SPROM access.
|
|
*
|
|
* @param sc chipc driver state.
|
|
*/
|
|
static void
|
|
chipc_disable_sprom_pins(struct chipc_softc *sc)
|
|
{
|
|
uint32_t cctrl;
|
|
|
|
/* Nothing to do? */
|
|
if (!CHIPC_QUIRK(sc, MUX_SPROM))
|
|
return;
|
|
|
|
CHIPC_LOCK_ASSERT(sc, MA_OWNED);
|
|
KASSERT(sc->sprom_refcnt == 0, ("sprom pins in use"));
|
|
|
|
cctrl = bhnd_bus_read_4(sc->core, CHIPC_CHIPCTRL);
|
|
|
|
/* 4331 devices */
|
|
if (CHIPC_QUIRK(sc, 4331_EXTPA_MUX_SPROM)) {
|
|
cctrl |= CHIPC_CCTRL4331_EXTPA_EN;
|
|
|
|
if (CHIPC_QUIRK(sc, 4331_GPIO2_5_MUX_SPROM))
|
|
cctrl |= CHIPC_CCTRL4331_EXTPA_ON_GPIO2_5;
|
|
|
|
if (CHIPC_QUIRK(sc, 4331_EXTPA2_MUX_SPROM))
|
|
cctrl |= CHIPC_CCTRL4331_EXTPA_EN2;
|
|
|
|
bhnd_bus_write_4(sc->core, CHIPC_CHIPCTRL, cctrl);
|
|
return;
|
|
}
|
|
|
|
/* 4360 devices */
|
|
if (CHIPC_QUIRK(sc, 4360_FEM_MUX_SPROM)) {
|
|
/* Unimplemented */
|
|
}
|
|
}
|
|
|
|
static uint32_t
|
|
chipc_read_chipst(device_t dev)
|
|
{
|
|
struct chipc_softc *sc = device_get_softc(dev);
|
|
return (bhnd_bus_read_4(sc->core, CHIPC_CHIPST));
|
|
}
|
|
|
|
static void
|
|
chipc_write_chipctrl(device_t dev, uint32_t value, uint32_t mask)
|
|
{
|
|
struct chipc_softc *sc;
|
|
uint32_t cctrl;
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
CHIPC_LOCK(sc);
|
|
|
|
cctrl = bhnd_bus_read_4(sc->core, CHIPC_CHIPCTRL);
|
|
cctrl = (cctrl & ~mask) | (value | mask);
|
|
bhnd_bus_write_4(sc->core, CHIPC_CHIPCTRL, cctrl);
|
|
|
|
CHIPC_UNLOCK(sc);
|
|
}
|
|
|
|
static struct chipc_caps *
|
|
chipc_get_caps(device_t dev)
|
|
{
|
|
struct chipc_softc *sc;
|
|
|
|
sc = device_get_softc(dev);
|
|
return (&sc->caps);
|
|
}
|
|
|
|
static device_method_t chipc_methods[] = {
|
|
/* Device interface */
|
|
DEVMETHOD(device_probe, chipc_probe),
|
|
DEVMETHOD(device_attach, chipc_attach),
|
|
DEVMETHOD(device_detach, chipc_detach),
|
|
DEVMETHOD(device_suspend, chipc_suspend),
|
|
DEVMETHOD(device_resume, chipc_resume),
|
|
|
|
/* Bus interface */
|
|
DEVMETHOD(bus_probe_nomatch, chipc_probe_nomatch),
|
|
DEVMETHOD(bus_print_child, chipc_print_child),
|
|
DEVMETHOD(bus_child_pnpinfo_str, chipc_child_pnpinfo_str),
|
|
DEVMETHOD(bus_child_location_str, chipc_child_location_str),
|
|
|
|
DEVMETHOD(bus_add_child, chipc_add_child),
|
|
DEVMETHOD(bus_child_deleted, chipc_child_deleted),
|
|
|
|
DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource),
|
|
DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource),
|
|
DEVMETHOD(bus_delete_resource, bus_generic_rl_delete_resource),
|
|
DEVMETHOD(bus_alloc_resource, chipc_alloc_resource),
|
|
DEVMETHOD(bus_release_resource, chipc_release_resource),
|
|
DEVMETHOD(bus_adjust_resource, chipc_adjust_resource),
|
|
DEVMETHOD(bus_activate_resource, chipc_activate_resource),
|
|
DEVMETHOD(bus_deactivate_resource, chipc_deactivate_resource),
|
|
DEVMETHOD(bus_get_resource_list, chipc_get_resource_list),
|
|
|
|
DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
|
|
DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
|
|
DEVMETHOD(bus_config_intr, bus_generic_config_intr),
|
|
DEVMETHOD(bus_bind_intr, bus_generic_bind_intr),
|
|
DEVMETHOD(bus_describe_intr, bus_generic_describe_intr),
|
|
|
|
/* BHND bus inteface */
|
|
DEVMETHOD(bhnd_bus_activate_resource, chipc_activate_bhnd_resource),
|
|
|
|
/* ChipCommon interface */
|
|
DEVMETHOD(bhnd_chipc_read_chipst, chipc_read_chipst),
|
|
DEVMETHOD(bhnd_chipc_write_chipctrl, chipc_write_chipctrl),
|
|
DEVMETHOD(bhnd_chipc_enable_sprom, chipc_enable_sprom),
|
|
DEVMETHOD(bhnd_chipc_disable_sprom, chipc_disable_sprom),
|
|
DEVMETHOD(bhnd_chipc_get_caps, chipc_get_caps),
|
|
|
|
DEVMETHOD_END
|
|
};
|
|
|
|
DEFINE_CLASS_0(bhnd_chipc, bhnd_chipc_driver, chipc_methods, sizeof(struct chipc_softc));
|
|
EARLY_DRIVER_MODULE(bhnd_chipc, bhnd, bhnd_chipc_driver, bhnd_chipc_devclass, 0, 0,
|
|
BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE);
|
|
MODULE_DEPEND(bhnd_chipc, bhnd, 1, 1, 1);
|
|
MODULE_VERSION(bhnd_chipc, 1);
|