f90f4b6532
- Added bhnd_pmu driver implementations for PMU and PWRCTL chipsets, derived from Broadcom's ISC-licensed HND code. - Added bhnd bus-level support for routing per-core clock and resource power requests to the PMU device. - Lift ChipCommon support out into the bhnd module, dropping bhnd_chipc. Reviewed by: mizhka Approved by: adrian (mentor) Differential Revision: https://reviews.freebsd.org/D7492
97 lines
3.7 KiB
C
97 lines
3.7 KiB
C
/*-
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* Copyright (c) 2015-2016 Landon Fuller <landon@landonf.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer,
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* without modification.
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* 2. Redistributions in binary form must reproduce at minimum a disclaimer
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* similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
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* redistribution must be conditioned upon including a substantially
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* similar Disclaimer requirement for further binary redistribution.
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*
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* NO WARRANTY
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
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* AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
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* OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
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* IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGES.
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*
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* $FreeBSD$
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*/
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#ifndef _BHND_CORES_CHIPC_CHIPC_H_
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#define _BHND_CORES_CHIPC_CHIPC_H_
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#include <dev/bhnd/bhnd.h>
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#include <dev/bhnd/nvram/bhnd_nvram.h>
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#include "bhnd_chipc_if.h"
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/**
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* Supported ChipCommon flash types.
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*/
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typedef enum {
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CHIPC_FLASH_NONE = 0, /**< No flash, or a type unrecognized
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by the ChipCommon driver */
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CHIPC_PFLASH_CFI = 1, /**< CFI-compatible parallel flash */
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CHIPC_SFLASH_ST = 2, /**< ST serial flash */
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CHIPC_SFLASH_AT = 3, /**< Atmel serial flash */
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CHIPC_QSFLASH_ST = 4, /**< ST quad-SPI flash */
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CHIPC_QSFLASH_AT = 5, /**< Atmel quad-SPI flash */
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CHIPC_NFLASH = 6, /**< NAND flash */
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CHIPC_NFLASH_4706 = 7 /**< BCM4706 NAND flash */
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} chipc_flash;
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/**
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* ChipCommon capability flags;
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*/
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struct chipc_caps {
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uint8_t num_uarts; /**< Number of attached UARTS (1-3) */
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bool mipseb; /**< MIPS is big-endian */
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uint8_t uart_clock; /**< UART clock source (see CHIPC_CAP_UCLKSEL_*) */
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uint8_t uart_gpio; /**< UARTs own GPIO pins 12-15 */
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uint8_t extbus_type; /**< ExtBus type (CHIPC_CAP_EXTBUS_*) */
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chipc_flash flash_type; /**< flash type */
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uint8_t cfi_width; /**< CFI bus width, 0 if unknown or CFI
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not present */
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bhnd_nvram_src nvram_src; /**< identified NVRAM source */
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bus_size_t sprom_offset; /**< Offset to SPROM data within
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SPROM/OTP, 0 if unknown or not
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present */
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uint8_t otp_size; /**< OTP (row?) size, 0 if not present */
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uint8_t pll_type; /**< PLL type */
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bool pwr_ctrl; /**< Power/clock control available */
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bool jtag_master; /**< JTAG Master present */
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bool boot_rom; /**< Internal boot ROM is active */
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uint8_t backplane_64; /**< Backplane supports 64-bit addressing.
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Note that this does not gaurantee
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the CPU itself supports 64-bit
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addressing. */
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bool pmu; /**< PMU is present. */
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bool eci; /**< ECI (enhanced coexistence inteface) is present. */
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bool seci; /**< SECI (serial ECI) is present */
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bool sprom; /**< SPROM is present */
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bool gsio; /**< GSIO (SPI/I2C) present */
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bool aob; /**< AOB (always on bus) present.
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If set, PMU and GCI registers are
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not accessible via ChipCommon,
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and are instead accessible via
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dedicated cores on the bhnd bus */
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};
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#endif /* _BHND_CORES_CHIPC_CHIPC_H_ */
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