aba10e131f
For purposes of handling hardware error reported via NMIs I need a way to escape NMI context, being too restrictive to do something significant. To do it this change introduces new swi_sched() flag SWI_FROMNMI, making it careful about used KPIs. On platforms allowing IPI sending from NMI context (x86 for now) it immediately wakes clk_intr_event via new IPI_SWI, otherwise it works just like SWI_DELAY. To handle the delayed SWIs this patch calls clk_intr_event on every hardclock() tick. MFC after: 2 weeks Sponsored by: iXsystems, Inc. Differential Revision: https://reviews.freebsd.org/D25754
115 lines
3.3 KiB
C
115 lines
3.3 KiB
C
/*-
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* SPDX-License-Identifier: Beerware
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*
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* ----------------------------------------------------------------------------
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* "THE BEER-WARE LICENSE" (Revision 42):
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* <phk@FreeBSD.org> wrote this file. As long as you retain this notice you
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* can do whatever you want with this stuff. If we meet some day, and you think
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* this stuff is worth it, you can buy me a beer in return. Poul-Henning Kamp
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* ----------------------------------------------------------------------------
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*
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* $FreeBSD$
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*
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*/
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#ifndef _X86_X86_SMP_H_
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#define _X86_X86_SMP_H_
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#include <sys/bus.h>
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#include <machine/frame.h>
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#include <machine/intr_machdep.h>
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#include <x86/apicvar.h>
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#include <machine/pcb.h>
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struct pmap;
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/* global data in mp_x86.c */
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extern int mp_naps;
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extern int boot_cpu_id;
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extern struct pcb stoppcbs[];
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extern int cpu_apic_ids[];
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extern int bootAP;
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extern void *dpcpu;
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extern char *bootSTK;
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extern void *bootstacks[];
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extern unsigned int boot_address;
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extern unsigned int bootMP_size;
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extern volatile int aps_ready;
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extern struct mtx ap_boot_mtx;
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extern int cpu_logical;
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extern int cpu_cores;
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extern volatile uint32_t smp_tlb_generation;
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extern struct pmap *smp_tlb_pmap;
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extern vm_offset_t smp_tlb_addr1, smp_tlb_addr2;
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extern u_int xhits_gbl[];
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extern u_int xhits_pg[];
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extern u_int xhits_rng[];
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extern u_int ipi_global;
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extern u_int ipi_page;
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extern u_int ipi_range;
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extern u_int ipi_range_size;
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extern int nmi_kdb_lock;
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extern int nmi_is_broadcast;
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struct cpu_info {
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int cpu_present:1;
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int cpu_bsp:1;
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int cpu_disabled:1;
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int cpu_hyperthread:1;
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};
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extern struct cpu_info *cpu_info;
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/*
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* Set if MWAIT does not reliably wake when the MONITORed address is written.
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*/
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extern bool mwait_cpustop_broken;
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#ifdef COUNT_IPIS
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extern u_long *ipi_invltlb_counts[MAXCPU];
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extern u_long *ipi_invlrng_counts[MAXCPU];
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extern u_long *ipi_invlpg_counts[MAXCPU];
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extern u_long *ipi_invlcache_counts[MAXCPU];
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extern u_long *ipi_rendezvous_counts[MAXCPU];
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#endif
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/* IPI handlers */
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inthand_t
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IDTVEC(ipi_intr_bitmap_handler), /* Bitmap based IPIs */
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IDTVEC(ipi_swi), /* Runs delayed SWI */
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IDTVEC(cpustop), /* CPU stops & waits to be restarted */
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IDTVEC(cpususpend), /* CPU suspends & waits to be resumed */
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IDTVEC(rendezvous); /* handle CPU rendezvous */
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typedef void (*smp_invl_cb_t)(struct pmap *, vm_offset_t addr1,
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vm_offset_t addr2);
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/* functions in x86_mp.c */
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void assign_cpu_ids(void);
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void cpu_add(u_int apic_id, char boot_cpu);
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void cpustop_handler(void);
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void cpususpend_handler(void);
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void alloc_ap_trampoline(vm_paddr_t *physmap, unsigned int *physmap_idx);
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void init_secondary_tail(void);
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void init_secondary(void);
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void ipi_startup(int apic_id, int vector);
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void ipi_all_but_self(u_int ipi);
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void ipi_bitmap_handler(struct trapframe frame);
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void ipi_cpu(int cpu, u_int ipi);
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int ipi_nmi_handler(void);
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void ipi_swi_handler(struct trapframe frame);
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void ipi_selected(cpuset_t cpus, u_int ipi);
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void ipi_self_from_nmi(u_int vector);
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void set_interrupt_apic_ids(void);
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void smp_cache_flush(smp_invl_cb_t curcpu_cb);
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void smp_masked_invlpg(cpuset_t mask, vm_offset_t addr, struct pmap *pmap,
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smp_invl_cb_t curcpu_cb);
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void smp_masked_invlpg_range(cpuset_t mask, vm_offset_t startva,
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vm_offset_t endva, struct pmap *pmap, smp_invl_cb_t curcpu_cb);
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void smp_masked_invltlb(cpuset_t mask, struct pmap *pmap,
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smp_invl_cb_t curcpu_cb);
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void mem_range_AP_init(void);
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void topo_probe(void);
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#endif
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