caeff9a3c2
On BHND MIPS SoCs, this replaces the use of hard-coded MIPS IRQ#s in the common bhnd(4) core drivers; we now register an INTRNG child PIC that handles routing of backplane interrupt vectors via the MIPS core. On BHND PCI devices, backplane interrupt vectors are now routed to the PCI/PCIe host bridge core when bus_setup_intr() is called, where they are dispatched by the PCI core via a host interrupt (e.g. INTx/MSI). The bhndb(4) bridge driver tracks registered interrupt handlers for the bridged bhnd(4) devices and manages backplane interrupt routing, while delegating actual bus interrupt setup/teardown to the parent bus on behalf of the bridged cores. Approved by: adrian (mentor, implicit) Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D12518
69 lines
2.9 KiB
C
69 lines
2.9 KiB
C
/*-
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* Copyright (c) 2016 Landon Fuller <landonf@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer,
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* without modification.
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* 2. Redistributions in binary form must reproduce at minimum a disclaimer
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* similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
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* redistribution must be conditioned upon including a substantially
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* similar Disclaimer requirement for further binary redistribution.
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*
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* NO WARRANTY
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
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* AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
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* OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
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* IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGES.
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*
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* $FreeBSD$
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*/
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#ifndef _MIPS_BROADCOM_MIPS74KREG_H_
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#define _MIPS_BROADCOM_MIPS74KREG_H_
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#define BCM_MIPS74K_CORECTL 0x00 /**< core control */
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#define BCM_MIPS74K_EXCBASE 0x04 /**< exception base */
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#define BCM_MIPS74K_BIST_STATUS 0x0C /**< built-in self-test status */
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#define BCM_MIPS74K_INTR_STATUS 0x10 /**< interrupt status */
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/* INTR(0-5)_MASK map bcma(4) OOB interrupt bus lines to MIPS hardware
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* interrupts. */
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#define BCM_MIPS74K_INTR0_SEL 0x14 /**< IRQ0 OOBSEL mask */
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#define BCM_MIPS74K_INTR1_SEL 0x18 /**< IRQ1 OOBSEL mask */
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#define BCM_MIPS74K_INTR2_SEL 0x1C /**< IRQ2 OOBSEL mask */
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#define BCM_MIPS74K_INTR3_SEL 0x20 /**< IRQ3 OOBSEL mask */
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#define BCM_MIPS74K_INTR4_SEL 0x24 /**< IRQ4 OOBSEL mask */
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#define BCM_MIPS74K_INTR5_SEL 0x28 /**< IRQ5 OOBSEL mask */
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#define BCM_MIPS74K_NUM_INTR 6 /**< routable CPU interrupt count */
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#define BCM_MIPS74K_INTR_SEL(_intr) \
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(BCM_MIPS74K_INTR0_SEL + ((_intr) * 4))
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#define BCM_MIPS74K_INTR_SEL_FLAG(_i) (1<<_i)
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#define BCM_MIPS74K_TIMER_IVEC 31 /**< MIPS timer's bus interrupt vector */
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#define BCM_MIPS74K_NMI_MASK 0x2C /**< nmi mask */
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#define BCM_MIPS74K_GPIO_SEL 0x40 /**< gpio select */
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#define BCM_MIPS74K_GPIO_OUT 0x44 /**< gpio output enable */
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#define BCM_MIPS74K_GPIO_EN 0x48 /**< gpio enable */
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/** The MIPS timer interrupt IRQ assignment */
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#define BCM_MIPS74K_GET_TIMER_IRQ() \
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((mips_rd_intctl() & MIPS_INTCTL_IPTI_MASK) >> MIPS_INTCTL_IPTI_SHIFT)
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#endif /* _MIPS_BROADCOM_MIPS74KREG_H_ */
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