498 lines
12 KiB
C
498 lines
12 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _X86_APICVAR_H_
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#define _X86_APICVAR_H_
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/*
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* Local && I/O APIC variable definitions.
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*/
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/*
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* Layout of local APIC interrupt vectors:
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*
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* 0xff (255) +-------------+
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* | | 15 (Spurious / IPIs / Local Interrupts)
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* 0xf0 (240) +-------------+
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* | | 14 (I/O Interrupts / Timer)
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* 0xe0 (224) +-------------+
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* | | 13 (I/O Interrupts)
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* 0xd0 (208) +-------------+
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* | | 12 (I/O Interrupts)
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* 0xc0 (192) +-------------+
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* | | 11 (I/O Interrupts)
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* 0xb0 (176) +-------------+
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* | | 10 (I/O Interrupts)
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* 0xa0 (160) +-------------+
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* | | 9 (I/O Interrupts)
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* 0x90 (144) +-------------+
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* | | 8 (I/O Interrupts / System Calls)
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* 0x80 (128) +-------------+
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* | | 7 (I/O Interrupts)
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* 0x70 (112) +-------------+
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* | | 6 (I/O Interrupts)
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* 0x60 (96) +-------------+
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* | | 5 (I/O Interrupts)
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* 0x50 (80) +-------------+
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* | | 4 (I/O Interrupts)
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* 0x40 (64) +-------------+
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* | | 3 (I/O Interrupts)
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* 0x30 (48) +-------------+
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* | | 2 (ATPIC Interrupts)
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* 0x20 (32) +-------------+
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* | | 1 (Exceptions, traps, faults, etc.)
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* 0x10 (16) +-------------+
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* | | 0 (Exceptions, traps, faults, etc.)
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* 0x00 (0) +-------------+
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*
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* Note: 0x80 needs to be handled specially and not allocated to an
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* I/O device!
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*/
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#define xAPIC_MAX_APIC_ID 0xfe
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#define xAPIC_ID_ALL 0xff
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#define MAX_APIC_ID 0x200
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#define APIC_ID_ALL 0xffffffff
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#define IOAPIC_MAX_ID xAPIC_MAX_APIC_ID
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/* I/O Interrupts are used for external devices such as ISA, PCI, etc. */
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#define APIC_IO_INTS (IDT_IO_INTS + 16)
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#define APIC_NUM_IOINTS 191
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/* The timer interrupt is used for clock handling and drives hardclock, etc. */
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#define APIC_TIMER_INT (APIC_IO_INTS + APIC_NUM_IOINTS)
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/*
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********************* !!! WARNING !!! ******************************
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* Each local apic has an interrupt receive fifo that is two entries deep
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* for each interrupt priority class (higher 4 bits of interrupt vector).
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* Once the fifo is full the APIC can no longer receive interrupts for this
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* class and sending IPIs from other CPUs will be blocked.
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* To avoid deadlocks there should be no more than two IPI interrupts
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* pending at the same time.
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* Currently this is guaranteed by dividing the IPIs in two groups that have
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* each at most one IPI interrupt pending. The first group is protected by the
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* smp_ipi_mtx and waits for the completion of the IPI (Only one IPI user
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* at a time) The second group uses a single interrupt and a bitmap to avoid
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* redundant IPI interrupts.
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*/
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/* Interrupts for local APIC LVT entries other than the timer. */
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#define APIC_LOCAL_INTS 240
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#define APIC_ERROR_INT APIC_LOCAL_INTS
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#define APIC_THERMAL_INT (APIC_LOCAL_INTS + 1)
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#define APIC_CMC_INT (APIC_LOCAL_INTS + 2)
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#define APIC_IPI_INTS (APIC_LOCAL_INTS + 3)
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#define IPI_RENDEZVOUS (APIC_IPI_INTS) /* Inter-CPU rendezvous. */
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#define IPI_INVLTLB (APIC_IPI_INTS + 1) /* TLB Shootdown IPIs */
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#define IPI_INVLPG (APIC_IPI_INTS + 2)
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#define IPI_INVLRNG (APIC_IPI_INTS + 3)
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#define IPI_INVLCACHE (APIC_IPI_INTS + 4)
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/* Vector to handle bitmap based IPIs */
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#define IPI_BITMAP_VECTOR (APIC_IPI_INTS + 5)
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/* IPIs handled by IPI_BITMAP_VECTOR */
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#define IPI_AST 0 /* Generate software trap. */
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#define IPI_PREEMPT 1
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#define IPI_HARDCLOCK 2
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#define IPI_BITMAP_LAST IPI_HARDCLOCK
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#define IPI_IS_BITMAPED(x) ((x) <= IPI_BITMAP_LAST)
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#define IPI_STOP (APIC_IPI_INTS + 6) /* Stop CPU until restarted. */
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#define IPI_SUSPEND (APIC_IPI_INTS + 7) /* Suspend CPU until restarted. */
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#ifdef __i386__
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#define IPI_LAZYPMAP (APIC_IPI_INTS + 8) /* Lazy pmap release. */
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#define IPI_DYN_FIRST (APIC_IPI_INTS + 9)
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#else
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#define IPI_DYN_FIRST (APIC_IPI_INTS + 8)
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#endif
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#define IPI_DYN_LAST (253) /* IPIs allocated at runtime */
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/*
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* IPI_STOP_HARD does not need to occupy a slot in the IPI vector space since
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* it is delivered using an NMI anyways.
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*/
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#define IPI_NMI_FIRST 254
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#define IPI_TRACE 254 /* Interrupt for tracing. */
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#define IPI_STOP_HARD 255 /* Stop CPU with a NMI. */
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/*
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* The spurious interrupt can share the priority class with the IPIs since
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* it is not a normal interrupt. (Does not use the APIC's interrupt fifo)
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*/
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#define APIC_SPURIOUS_INT 255
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#ifndef LOCORE
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#define APIC_IPI_DEST_SELF -1
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#define APIC_IPI_DEST_ALL -2
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#define APIC_IPI_DEST_OTHERS -3
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#define APIC_BUS_UNKNOWN -1
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#define APIC_BUS_ISA 0
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#define APIC_BUS_EISA 1
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#define APIC_BUS_PCI 2
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#define APIC_BUS_MAX APIC_BUS_PCI
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#define IRQ_EXTINT (NUM_IO_INTS + 1)
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#define IRQ_NMI (NUM_IO_INTS + 2)
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#define IRQ_SMI (NUM_IO_INTS + 3)
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#define IRQ_DISABLED (NUM_IO_INTS + 4)
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/*
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* An APIC enumerator is a pseudo bus driver that enumerates APIC's including
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* CPU's and I/O APIC's.
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*/
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struct apic_enumerator {
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const char *apic_name;
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int (*apic_probe)(void);
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int (*apic_probe_cpus)(void);
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int (*apic_setup_local)(void);
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int (*apic_setup_io)(void);
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SLIST_ENTRY(apic_enumerator) apic_next;
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};
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inthand_t
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IDTVEC(apic_isr1), IDTVEC(apic_isr2), IDTVEC(apic_isr3),
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IDTVEC(apic_isr4), IDTVEC(apic_isr5), IDTVEC(apic_isr6),
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IDTVEC(apic_isr7), IDTVEC(cmcint), IDTVEC(errorint),
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IDTVEC(spuriousint), IDTVEC(timerint),
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IDTVEC(apic_isr1_pti), IDTVEC(apic_isr2_pti), IDTVEC(apic_isr3_pti),
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IDTVEC(apic_isr4_pti), IDTVEC(apic_isr5_pti), IDTVEC(apic_isr6_pti),
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IDTVEC(apic_isr7_pti), IDTVEC(cmcint_pti), IDTVEC(errorint_pti),
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IDTVEC(spuriousint_pti), IDTVEC(timerint_pti);
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extern vm_paddr_t lapic_paddr;
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extern int *apic_cpuids;
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void apic_register_enumerator(struct apic_enumerator *enumerator);
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void *ioapic_create(vm_paddr_t addr, int32_t apic_id, int intbase);
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int ioapic_disable_pin(void *cookie, u_int pin);
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int ioapic_get_vector(void *cookie, u_int pin);
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void ioapic_register(void *cookie);
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int ioapic_remap_vector(void *cookie, u_int pin, int vector);
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int ioapic_set_bus(void *cookie, u_int pin, int bus_type);
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int ioapic_set_extint(void *cookie, u_int pin);
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int ioapic_set_nmi(void *cookie, u_int pin);
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int ioapic_set_polarity(void *cookie, u_int pin, enum intr_polarity pol);
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int ioapic_set_triggermode(void *cookie, u_int pin,
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enum intr_trigger trigger);
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int ioapic_set_smi(void *cookie, u_int pin);
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/*
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* Struct containing pointers to APIC functions whose
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* implementation is run time selectable.
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*/
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struct apic_ops {
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void (*create)(u_int, int);
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void (*init)(vm_paddr_t);
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void (*xapic_mode)(void);
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bool (*is_x2apic)(void);
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void (*setup)(int);
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void (*dump)(const char *);
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void (*disable)(void);
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void (*eoi)(void);
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int (*id)(void);
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int (*intr_pending)(u_int);
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void (*set_logical_id)(u_int, u_int, u_int);
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u_int (*cpuid)(u_int);
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/* Vectors */
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u_int (*alloc_vector)(u_int, u_int);
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u_int (*alloc_vectors)(u_int, u_int *, u_int, u_int);
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void (*enable_vector)(u_int, u_int);
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void (*disable_vector)(u_int, u_int);
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void (*free_vector)(u_int, u_int, u_int);
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/* PMC */
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int (*enable_pmc)(void);
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void (*disable_pmc)(void);
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void (*reenable_pmc)(void);
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/* CMC */
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void (*enable_cmc)(void);
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/* AMD ELVT */
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int (*enable_mca_elvt)(void);
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/* IPI */
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void (*ipi_raw)(register_t, u_int);
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void (*ipi_vectored)(u_int, int);
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int (*ipi_wait)(int);
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int (*ipi_alloc)(inthand_t *ipifunc);
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void (*ipi_free)(int vector);
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/* LVT */
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int (*set_lvt_mask)(u_int, u_int, u_char);
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int (*set_lvt_mode)(u_int, u_int, u_int32_t);
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int (*set_lvt_polarity)(u_int, u_int, enum intr_polarity);
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int (*set_lvt_triggermode)(u_int, u_int, enum intr_trigger);
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};
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extern struct apic_ops apic_ops;
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static inline void
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lapic_create(u_int apic_id, int boot_cpu)
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{
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apic_ops.create(apic_id, boot_cpu);
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}
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static inline void
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lapic_init(vm_paddr_t addr)
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{
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apic_ops.init(addr);
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}
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static inline void
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lapic_xapic_mode(void)
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{
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apic_ops.xapic_mode();
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}
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static inline bool
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lapic_is_x2apic(void)
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{
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return (apic_ops.is_x2apic());
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}
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static inline void
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lapic_setup(int boot)
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{
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apic_ops.setup(boot);
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}
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static inline void
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lapic_dump(const char *str)
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{
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apic_ops.dump(str);
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}
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static inline void
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lapic_disable(void)
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{
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apic_ops.disable();
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}
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static inline void
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lapic_eoi(void)
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{
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apic_ops.eoi();
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}
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static inline int
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lapic_id(void)
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{
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return (apic_ops.id());
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}
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static inline int
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lapic_intr_pending(u_int vector)
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{
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return (apic_ops.intr_pending(vector));
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}
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/* XXX: UNUSED */
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static inline void
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lapic_set_logical_id(u_int apic_id, u_int cluster, u_int cluster_id)
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{
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apic_ops.set_logical_id(apic_id, cluster, cluster_id);
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}
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static inline u_int
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apic_cpuid(u_int apic_id)
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{
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return (apic_ops.cpuid(apic_id));
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}
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static inline u_int
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apic_alloc_vector(u_int apic_id, u_int irq)
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{
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return (apic_ops.alloc_vector(apic_id, irq));
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}
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static inline u_int
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apic_alloc_vectors(u_int apic_id, u_int *irqs, u_int count, u_int align)
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{
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return (apic_ops.alloc_vectors(apic_id, irqs, count, align));
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}
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static inline void
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apic_enable_vector(u_int apic_id, u_int vector)
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{
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apic_ops.enable_vector(apic_id, vector);
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}
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static inline void
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apic_disable_vector(u_int apic_id, u_int vector)
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{
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apic_ops.disable_vector(apic_id, vector);
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}
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static inline void
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apic_free_vector(u_int apic_id, u_int vector, u_int irq)
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{
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apic_ops.free_vector(apic_id, vector, irq);
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}
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static inline int
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lapic_enable_pmc(void)
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{
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return (apic_ops.enable_pmc());
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}
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static inline void
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lapic_disable_pmc(void)
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{
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apic_ops.disable_pmc();
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}
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static inline void
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lapic_reenable_pmc(void)
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{
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apic_ops.reenable_pmc();
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}
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static inline void
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lapic_enable_cmc(void)
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{
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apic_ops.enable_cmc();
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}
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static inline int
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lapic_enable_mca_elvt(void)
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{
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return (apic_ops.enable_mca_elvt());
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}
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static inline void
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lapic_ipi_raw(register_t icrlo, u_int dest)
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{
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apic_ops.ipi_raw(icrlo, dest);
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}
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static inline void
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lapic_ipi_vectored(u_int vector, int dest)
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{
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apic_ops.ipi_vectored(vector, dest);
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}
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static inline int
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lapic_ipi_wait(int delay)
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{
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return (apic_ops.ipi_wait(delay));
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}
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static inline int
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lapic_ipi_alloc(inthand_t *ipifunc)
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{
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return (apic_ops.ipi_alloc(ipifunc));
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}
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static inline void
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lapic_ipi_free(int vector)
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{
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return (apic_ops.ipi_free(vector));
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}
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static inline int
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lapic_set_lvt_mask(u_int apic_id, u_int lvt, u_char masked)
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{
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return (apic_ops.set_lvt_mask(apic_id, lvt, masked));
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}
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static inline int
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lapic_set_lvt_mode(u_int apic_id, u_int lvt, u_int32_t mode)
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{
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return (apic_ops.set_lvt_mode(apic_id, lvt, mode));
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}
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static inline int
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lapic_set_lvt_polarity(u_int apic_id, u_int lvt, enum intr_polarity pol)
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{
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return (apic_ops.set_lvt_polarity(apic_id, lvt, pol));
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}
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static inline int
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lapic_set_lvt_triggermode(u_int apic_id, u_int lvt, enum intr_trigger trigger)
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{
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return (apic_ops.set_lvt_triggermode(apic_id, lvt, trigger));
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}
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void lapic_handle_cmc(void);
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void lapic_handle_error(void);
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void lapic_handle_intr(int vector, struct trapframe *frame);
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void lapic_handle_timer(struct trapframe *frame);
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int ioapic_get_rid(u_int apic_id, uint16_t *ridp);
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extern int x2apic_mode;
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extern int lapic_eoi_suppression;
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#ifdef _SYS_SYSCTL_H_
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SYSCTL_DECL(_hw_apic);
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#endif
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#endif /* !LOCORE */
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#endif /* _X86_APICVAR_H_ */
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