d22883d715
e4b8deb222 removed the last in-tree uses of PCPU_INC(). Its
potential benefit is also practically nonexistent. Non-x86
platforms already implement it as PCPU_ADD(..., 1), and according
to [0] there are no recent x86 processors for which the 'inc'
instruction provides a performance benefit over the equivalent
memory-operand form of the 'add' instruction. The only remaining
benefit of 'inc' is smaller instruction size, which in this case
is inconsequential given the limited number of per-CPU data consumers.
[0]: https://www.agner.org/optimize/instruction_tables.pdf
Reviewed by: kib
Differential Revision: https://reviews.freebsd.org/D29308
289 lines
9.0 KiB
C
289 lines
9.0 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) Peter Wemm <peter@netplex.com.au>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _MACHINE_PCPU_H_
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#define _MACHINE_PCPU_H_
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#ifndef _SYS_CDEFS_H_
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#error "sys/cdefs.h is a prerequisite for this file"
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#endif
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#include <machine/segments.h>
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#include <machine/tss.h>
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#define PC_PTI_STACK_SZ 16
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struct monitorbuf {
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int idle_state; /* Used by cpu_idle_mwait. */
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int stop_state; /* Used by cpustop_handler. */
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char padding[128 - (2 * sizeof(int))];
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};
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_Static_assert(sizeof(struct monitorbuf) == 128, "2x cache line");
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/*
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* The SMP parts are setup in pmap.c and locore.s for the BSP, and
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* mp_machdep.c sets up the data for the AP's to "see" when they awake.
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* The reason for doing it via a struct is so that an array of pointers
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* to each CPU's data can be set up for things like "check curproc on all
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* other processors"
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*/
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#define PCPU_MD_FIELDS \
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struct monitorbuf pc_monitorbuf __aligned(128); /* cache line */\
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struct pcpu *pc_prvspace; /* Self-reference */ \
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struct pmap *pc_curpmap; \
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struct amd64tss *pc_tssp; /* TSS segment active on CPU */ \
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void *pc_pad0; \
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uint64_t pc_kcr3; \
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uint64_t pc_ucr3; \
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uint64_t pc_saved_ucr3; \
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register_t pc_rsp0; \
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register_t pc_scratch_rsp; /* User %rsp in syscall */ \
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register_t pc_scratch_rax; \
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u_int pc_apic_id; \
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u_int pc_acpi_id; /* ACPI CPU id */ \
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/* Pointer to the CPU %fs descriptor */ \
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struct user_segment_descriptor *pc_fs32p; \
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/* Pointer to the CPU %gs descriptor */ \
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struct user_segment_descriptor *pc_gs32p; \
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/* Pointer to the CPU LDT descriptor */ \
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struct system_segment_descriptor *pc_ldt; \
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/* Pointer to the CPU TSS descriptor */ \
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struct system_segment_descriptor *pc_tss; \
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u_int pc_cmci_mask; /* MCx banks for CMCI */ \
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uint64_t pc_dbreg[16]; /* ddb debugging regs */ \
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uint64_t pc_pti_stack[PC_PTI_STACK_SZ]; \
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register_t pc_pti_rsp0; \
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int pc_dbreg_cmd; /* ddb debugging reg cmd */ \
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u_int pc_vcpu_id; /* Xen vCPU ID */ \
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uint32_t pc_pcid_next; \
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uint32_t pc_pcid_gen; \
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uint32_t pc_unused; \
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uint32_t pc_ibpb_set; \
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void *pc_mds_buf; \
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void *pc_mds_buf64; \
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uint32_t pc_pad[4]; \
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uint8_t pc_mds_tmp[64]; \
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u_int pc_ipi_bitmap; \
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struct amd64tss pc_common_tss; \
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struct user_segment_descriptor pc_gdt[NGDT]; \
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void *pc_smp_tlb_pmap; \
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uint64_t pc_smp_tlb_addr1; \
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uint64_t pc_smp_tlb_addr2; \
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uint32_t pc_smp_tlb_gen; \
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u_int pc_smp_tlb_op; \
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uint64_t pc_ucr3_load_mask; \
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char __pad[2916] /* pad to UMA_PCPU_ALLOC_SIZE */
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#define PC_DBREG_CMD_NONE 0
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#define PC_DBREG_CMD_LOAD 1
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#ifdef _KERNEL
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#define MONITOR_STOPSTATE_RUNNING 0
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#define MONITOR_STOPSTATE_STOPPED 1
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#if defined(__GNUCLIKE_ASM) && defined(__GNUCLIKE___TYPEOF)
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/*
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* Evaluates to the byte offset of the per-cpu variable name.
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*/
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#define __pcpu_offset(name) \
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__offsetof(struct pcpu, name)
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/*
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* Evaluates to the type of the per-cpu variable name.
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*/
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#define __pcpu_type(name) \
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__typeof(((struct pcpu *)0)->name)
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/*
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* Evaluates to the address of the per-cpu variable name.
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*/
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#define __PCPU_PTR(name) __extension__ ({ \
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__pcpu_type(name) *__p; \
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\
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__asm __volatile("movq %%gs:%1,%0; addq %2,%0" \
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: "=r" (__p) \
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: "m" (*(struct pcpu *)(__pcpu_offset(pc_prvspace))), \
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"i" (__pcpu_offset(name))); \
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\
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__p; \
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})
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/*
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* Evaluates to the value of the per-cpu variable name.
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*/
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#define __PCPU_GET(name) __extension__ ({ \
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__pcpu_type(name) __res; \
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struct __s { \
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u_char __b[MIN(sizeof(__pcpu_type(name)), 8)]; \
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} __s; \
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\
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if (sizeof(__res) == 1 || sizeof(__res) == 2 || \
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sizeof(__res) == 4 || sizeof(__res) == 8) { \
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__asm __volatile("mov %%gs:%1,%0" \
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: "=r" (__s) \
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: "m" (*(struct __s *)(__pcpu_offset(name)))); \
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*(struct __s *)(void *)&__res = __s; \
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} else { \
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__res = *__PCPU_PTR(name); \
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} \
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__res; \
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})
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/*
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* Adds the value to the per-cpu counter name. The implementation
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* must be atomic with respect to interrupts.
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*/
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#define __PCPU_ADD(name, val) do { \
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__pcpu_type(name) __val; \
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struct __s { \
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u_char __b[MIN(sizeof(__pcpu_type(name)), 8)]; \
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} __s; \
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\
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__val = (val); \
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if (sizeof(__val) == 1 || sizeof(__val) == 2 || \
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sizeof(__val) == 4 || sizeof(__val) == 8) { \
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__s = *(struct __s *)(void *)&__val; \
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__asm __volatile("add %1,%%gs:%0" \
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: "=m" (*(struct __s *)(__pcpu_offset(name))) \
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: "r" (__s)); \
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} else \
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*__PCPU_PTR(name) += __val; \
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} while (0)
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/*
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* Sets the value of the per-cpu variable name to value val.
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*/
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#define __PCPU_SET(name, val) { \
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__pcpu_type(name) __val; \
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struct __s { \
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u_char __b[MIN(sizeof(__pcpu_type(name)), 8)]; \
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} __s; \
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\
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__val = (val); \
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if (sizeof(__val) == 1 || sizeof(__val) == 2 || \
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sizeof(__val) == 4 || sizeof(__val) == 8) { \
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__s = *(struct __s *)(void *)&__val; \
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__asm __volatile("mov %1,%%gs:%0" \
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: "=m" (*(struct __s *)(__pcpu_offset(name))) \
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: "r" (__s)); \
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} else { \
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*__PCPU_PTR(name) = __val; \
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} \
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}
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#define get_pcpu() __extension__ ({ \
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struct pcpu *__pc; \
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\
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__asm __volatile("movq %%gs:%1,%0" \
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: "=r" (__pc) \
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: "m" (*(struct pcpu *)(__pcpu_offset(pc_prvspace)))); \
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__pc; \
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})
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#define PCPU_GET(member) __PCPU_GET(pc_ ## member)
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#define PCPU_ADD(member, val) __PCPU_ADD(pc_ ## member, val)
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#define PCPU_PTR(member) __PCPU_PTR(pc_ ## member)
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#define PCPU_SET(member, val) __PCPU_SET(pc_ ## member, val)
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#define IS_BSP() (PCPU_GET(cpuid) == 0)
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#define zpcpu_offset_cpu(cpu) ((uintptr_t)&__pcpu[0] + UMA_PCPU_ALLOC_SIZE * cpu)
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#define zpcpu_base_to_offset(base) (void *)((uintptr_t)(base) - (uintptr_t)&__pcpu[0])
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#define zpcpu_offset_to_base(base) (void *)((uintptr_t)(base) + (uintptr_t)&__pcpu[0])
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#define zpcpu_sub_protected(base, n) do { \
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ZPCPU_ASSERT_PROTECTED(); \
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zpcpu_sub(base, n); \
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} while (0)
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#define zpcpu_set_protected(base, n) do { \
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__typeof(*base) __n = (n); \
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ZPCPU_ASSERT_PROTECTED(); \
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switch (sizeof(*base)) { \
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case 4: \
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__asm __volatile("movl\t%1,%%gs:(%0)" \
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: : "r" (base), "ri" (__n) : "memory", "cc"); \
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break; \
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case 8: \
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__asm __volatile("movq\t%1,%%gs:(%0)" \
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: : "r" (base), "ri" (__n) : "memory", "cc"); \
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break; \
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default: \
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*zpcpu_get(base) = __n; \
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} \
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} while (0);
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#define zpcpu_add(base, n) do { \
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__typeof(*base) __n = (n); \
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CTASSERT(sizeof(*base) == 4 || sizeof(*base) == 8); \
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switch (sizeof(*base)) { \
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case 4: \
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__asm __volatile("addl\t%1,%%gs:(%0)" \
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: : "r" (base), "ri" (__n) : "memory", "cc"); \
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break; \
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case 8: \
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__asm __volatile("addq\t%1,%%gs:(%0)" \
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: : "r" (base), "ri" (__n) : "memory", "cc"); \
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break; \
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} \
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} while (0)
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#define zpcpu_add_protected(base, n) do { \
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ZPCPU_ASSERT_PROTECTED(); \
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zpcpu_add(base, n); \
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} while (0)
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#define zpcpu_sub(base, n) do { \
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__typeof(*base) __n = (n); \
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CTASSERT(sizeof(*base) == 4 || sizeof(*base) == 8); \
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switch (sizeof(*base)) { \
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case 4: \
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__asm __volatile("subl\t%1,%%gs:(%0)" \
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: : "r" (base), "ri" (__n) : "memory", "cc"); \
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break; \
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case 8: \
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__asm __volatile("subq\t%1,%%gs:(%0)" \
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: : "r" (base), "ri" (__n) : "memory", "cc"); \
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break; \
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} \
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} while (0);
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#else /* !__GNUCLIKE_ASM || !__GNUCLIKE___TYPEOF */
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#error "this file needs to be ported to your compiler"
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#endif /* __GNUCLIKE_ASM && __GNUCLIKE___TYPEOF */
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#endif /* _KERNEL */
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#endif /* !_MACHINE_PCPU_H_ */
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