64f6f1fa7e
Submitted by: NOKUBI Hirotaka <hnokubi@yyy.or.jp> and
Takahashi Yoshihiro <nyan@wyvern.cc.kogakuin.ac.jp>
352 lines
8.8 KiB
C
352 lines
8.8 KiB
C
/* $NecBSD: bshw.h,v 1.2 1997/10/31 17:43:38 honda Exp $ */
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/* $NetBSD$ */
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/*
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* [NetBSD for NEC PC98 series]
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* Copyright (c) 1994, 1995, 1996 NetBSD/pc98 porting staff.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Copyright (c) 1994, 1995, 1996 Naofumi HONDA. All rights reserved.
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*/
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/* NEC port offsets */
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#define BSHW_DEFAULT_PORT 0xcc0
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#define BSHW_IOSZ 5
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#define addr_port 0
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#define stat_port 0
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#define ctrl_port 2
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#define cmd_port 4
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#define BSHW_MAX_OFFSET 12
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#define BSHW_SEL_TIMEOUT 0x80
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#define BSHW_READ BSR_IOR
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#define BSHW_WRITE 0x0
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#define BSHW_SMITFIFO_OFFSET 0x1000
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#define BSHW_CMD_CHECK(CCB, CAT) (bshw_cmd[(CCB)->cmd[0]] & (CAT))
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/*********************************************************
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* static inline declare.
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*********************************************************/
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static BS_INLINE void write_wd33c93 __P((struct bs_softc *, u_int, u_int8_t));
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static BS_INLINE u_int8_t read_wd33c93 __P((struct bs_softc *, u_int));
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static BS_INLINE u_int8_t bshw_get_auxstat __P((struct bs_softc *));
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static BS_INLINE u_int8_t bshw_get_busstat __P((struct bs_softc *));
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static BS_INLINE u_int8_t bshw_get_status_insat __P((struct bs_softc *));
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static BS_INLINE u_int8_t bshw_read_data __P((struct bs_softc *));
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static BS_INLINE void bshw_write_data __P((struct bs_softc *, u_int8_t));
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static BS_INLINE void bshw_set_count __P((struct bs_softc *, u_int));
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static BS_INLINE u_int bshw_get_count __P((struct bs_softc *));
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static BS_INLINE void bshw_set_dst_id __P((struct bs_softc *, u_int, u_int));
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static BS_INLINE void bshw_set_lun __P((struct bs_softc *, u_int));
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static BS_INLINE u_int bshw_get_src_id __P((struct bs_softc *));
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static BS_INLINE void bshw_negate_ack __P((struct bs_softc *));
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static BS_INLINE void bshw_assert_atn __P((struct bs_softc *));
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static BS_INLINE void bshw_assert_select __P((struct bs_softc *));
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static BS_INLINE void bshw_start_xfer __P((struct bs_softc *));
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static BS_INLINE void bshw_start_sxfer __P((struct bs_softc *));
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static BS_INLINE void bshw_cmd_pass __P((struct bs_softc *, u_int));
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static BS_INLINE void bshw_start_sat __P((struct bs_softc *, u_int));
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static BS_INLINE void bshw_abort_cmd __P((struct bs_softc *));
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static BS_INLINE void bshw_set_sync_reg __P((struct bs_softc *, u_int));
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static BS_INLINE void bshw_set_poll_trans __P((struct bs_softc *, u_int));
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static BS_INLINE void bshw_set_dma_trans __P((struct bs_softc *, u_int));
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/*********************************************************
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* global declare
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*********************************************************/
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void bs_dma_xfer __P((struct targ_info *, u_int));
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void bs_dma_xfer_end __P((struct targ_info *));
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void bshw_dmaabort __P((struct bs_softc *, struct targ_info *));
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void bshw_adj_syncdata __P((struct syncdata *));
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void bshw_set_synchronous __P((struct bs_softc *, struct targ_info *));
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void bs_smit_xfer_end __P((struct targ_info *));
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void bshw_smitabort __P((struct bs_softc *));
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void bshw_setup_ctrl_reg __P((struct bs_softc *, u_int));
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int bshw_chip_reset __P((struct bs_softc *));
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void bshw_bus_reset __P((struct bs_softc *));
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int bshw_board_probe __P((struct bs_softc *, u_int *, u_int *));
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void bshw_lock __P((struct bs_softc *));
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void bshw_unlock __P((struct bs_softc *));
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void bshw_get_syncreg __P((struct bs_softc *));
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void bshw_issue_satcmd __P((struct bs_softc *, struct bsccb *, int));
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void bshw_print_port __P((struct bs_softc *));
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void bs_lc_smit_xfer __P((struct targ_info *, u_int));
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extern struct dvcfg_hwsel bshw_hwsel;
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extern u_int8_t bshw_cmd[];
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/*********************************************************
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* hw
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*********************************************************/
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struct bshw {
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#define BSHW_SYNC_RELOAD 0x01
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#define BSHW_SMFIFO 0x02
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#define BSHW_DOUBLE_DMACHAN 0x04
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u_int hw_flags;
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u_int sregaddr;
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int ((*dma_init) __P((struct bs_softc *)));
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void ((*dma_start) __P((struct bs_softc *)));
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void ((*dma_stop) __P((struct bs_softc *)));
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};
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/*********************************************************
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* inline funcs.
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*********************************************************/
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/*
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* XXX: If your board does not work well, Please try BS_NEEDS_WEIGHT.
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*/
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static BS_INLINE void
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write_wd33c93(bsc, addr, data)
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struct bs_softc *bsc;
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u_int addr;
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u_int8_t data;
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{
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BUS_IOW(addr_port, addr);
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BUS_IOW(ctrl_port, data);
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}
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static BS_INLINE u_int8_t
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read_wd33c93(bsc, addr)
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struct bs_softc *bsc;
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u_int addr;
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{
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BUS_IOW(addr_port, addr);
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return BUS_IOR(ctrl_port);
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}
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/* status */
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static BS_INLINE u_int8_t
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bshw_get_auxstat(bsc)
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struct bs_softc *bsc;
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{
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return BUS_IOR(stat_port);
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}
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static BS_INLINE u_int8_t
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bshw_get_busstat(bsc)
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struct bs_softc *bsc;
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{
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return read_wd33c93(bsc, wd3s_stat);
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}
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static BS_INLINE u_int8_t
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bshw_get_status_insat(bsc)
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struct bs_softc *bsc;
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{
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return read_wd33c93(bsc, wd3s_lun);
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}
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/* data */
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static BS_INLINE u_int8_t
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bshw_read_data(bsc)
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struct bs_softc *bsc;
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{
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return read_wd33c93(bsc, wd3s_data);
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}
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static BS_INLINE void
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bshw_write_data(bsc, data)
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struct bs_softc *bsc;
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u_int8_t data;
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{
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write_wd33c93(bsc, wd3s_data, data);
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}
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/* counter */
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static BS_INLINE void
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bshw_set_count(bsc, count)
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struct bs_softc *bsc;
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u_int count;
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{
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BUS_IOW(addr_port, wd3s_cnt);
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BUS_IOW(ctrl_port, count >> 16);
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BUS_IOW(ctrl_port, count >> 8);
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BUS_IOW(ctrl_port, count);
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}
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static BS_INLINE u_int
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bshw_get_count(bsc)
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struct bs_softc *bsc;
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{
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u_int count;
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BUS_IOW(addr_port, wd3s_cnt);
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count = (((u_int) BUS_IOR(ctrl_port)) << 16);
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count += (((u_int) BUS_IOR(ctrl_port)) << 8);
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count += ((u_int) BUS_IOR(ctrl_port));
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return count;
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}
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/* ID */
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static BS_INLINE void
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bshw_set_lun(bsc, lun)
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struct bs_softc *bsc;
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u_int lun;
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{
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write_wd33c93(bsc, wd3s_lun, lun);
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}
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static BS_INLINE void
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bshw_set_dst_id(bsc, target, lun)
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struct bs_softc *bsc;
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u_int target, lun;
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{
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write_wd33c93(bsc, wd3s_did, target);
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write_wd33c93(bsc, wd3s_lun, lun);
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}
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static BS_INLINE u_int
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bshw_get_src_id(bsc)
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struct bs_softc *bsc;
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{
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return (read_wd33c93(bsc, wd3s_sid) & SIDR_IDM);
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}
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/* phase */
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static BS_INLINE void
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bshw_negate_ack(bsc)
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struct bs_softc *bsc;
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{
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write_wd33c93(bsc, wd3s_cmd, WD3S_NEGATE_ACK);
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}
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static BS_INLINE void
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bshw_assert_atn(bsc)
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struct bs_softc *bsc;
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{
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write_wd33c93(bsc, wd3s_cmd, WD3S_ASSERT_ATN);
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}
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static BS_INLINE void
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bshw_assert_select(bsc)
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struct bs_softc *bsc;
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{
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write_wd33c93(bsc, wd3s_cmd, WD3S_SELECT_ATN);
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}
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static BS_INLINE void
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bshw_start_xfer(bsc)
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struct bs_softc *bsc;
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{
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write_wd33c93(bsc, wd3s_cmd, WD3S_TFR_INFO);
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}
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static BS_INLINE void
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bshw_start_sxfer(bsc)
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struct bs_softc *bsc;
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{
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write_wd33c93(bsc, wd3s_cmd, WD3S_SBT | WD3S_TFR_INFO);
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}
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static BS_INLINE void
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bshw_cmd_pass(bsc, ph)
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struct bs_softc *bsc;
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u_int ph;
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{
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write_wd33c93(bsc, wd3s_cph, ph);
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}
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static BS_INLINE void
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bshw_start_sat(bsc, flag)
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struct bs_softc *bsc;
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u_int flag;
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{
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write_wd33c93(bsc, wd3s_cmd,
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(flag ? WD3S_SELECT_ATN_TFR : WD3S_SELECT_NO_ATN_TFR));
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}
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static BS_INLINE void
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bshw_abort_cmd(bsc)
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struct bs_softc *bsc;
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{
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write_wd33c93(bsc, wd3s_cmd, WD3S_ABORT);
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}
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/* transfer mode */
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static BS_INLINE void
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bshw_set_sync_reg(bsc, val)
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struct bs_softc *bsc;
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u_int val;
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{
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write_wd33c93(bsc, wd3s_synch, val);
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}
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static BS_INLINE void
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bshw_set_poll_trans(bsc, flags)
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struct bs_softc *bsc;
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u_int flags;
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{
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if (bsc->sc_flags & BSDMATRANSFER)
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{
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bsc->sc_flags &= ~BSDMATRANSFER;
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bshw_setup_ctrl_reg(bsc, flags);
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}
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}
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static BS_INLINE void
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bshw_set_dma_trans(bsc, flags)
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struct bs_softc *bsc;
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u_int flags;
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{
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if ((bsc->sc_flags & BSDMATRANSFER) == 0)
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{
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bsc->sc_flags |= BSDMATRANSFER;
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bshw_setup_ctrl_reg(bsc, flags);
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}
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}
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