4c024bbdf8
supports All Cyrix CPUs, IBM Blue Lightning CPU and NexGen (now AMD)
Nx586 CPU, and initialize special registers of Cyrix CPU and msr of
IBM Blue Lightning CPU.
If revision of Cyrix 6x86 CPU < 2.7, CPU cache is enabled in
write-through mode. This can be disabled by kernel configuration
options.
Reviewed by: Bruce Evans <bde@freebsd.org> and
Jordan K. Hubbard <jkh@freebsd.org>
338 lines
7.9 KiB
C
338 lines
7.9 KiB
C
/* $NetBSD$ */
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/*
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* [NetBSD for NEC PC98 series]
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* Copyright (c) 1994, 1995, 1996 NetBSD/pc98 porting staff.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Copyright (c) 1994, 1995, 1996 Naofumi HONDA. All rights reserved.
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*/
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/*********************************************************
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* static declare.
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*********************************************************/
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static BS_INLINE void bshw_dmastart __P((struct bs_softc *));
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static void bshw_dmadone __P((struct bs_softc *));
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/**********************************************
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* UPPER INTERFACE FUNCS (all funcs exported)
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**********************************************/
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void
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bshw_dmaabort(bsc, ti)
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struct bs_softc *bsc;
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struct targ_info *ti;
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{
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bshw_dmadone(bsc);
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bsc->sc_p.seglen = 0;
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bshw_set_count(bsc, 0);
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if (ti == NULL)
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{
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int i;
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struct targ_info *tmpti;
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for (i = 0; i < NTARGETS; i++)
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if (tmpti = bsc->sc_ti[i])
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tmpti->ti_scsp.seglen = 0;
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}
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else
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ti->ti_scsp.seglen = 0;
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}
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/* DMA TRANSFER */
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void
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bs_dma_xfer(ti, direction)
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struct targ_info *ti;
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u_int direction;
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{
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vm_offset_t va, endva, phys, nphys;
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struct bs_softc *bsc = ti->ti_bsc;
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struct sc_p *sp = &bsc->sc_p;
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bsc->sc_dmadir = direction;
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bshw_set_dma_trans(bsc, ti->ti_cfgflags);
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if (sp->seglen == 0)
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{
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phys = vtophys((vm_offset_t) sp->data);
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if (phys >= RAM_END)
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{
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/* setup segaddr */
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sp->segaddr = ti->bounce_phys;
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/* setup seglen */
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sp->seglen = sp->datalen;
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if (sp->seglen > ti->bounce_size)
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sp->seglen = ti->bounce_size;
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/* setup bufp */
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sp->bufp = ti->bounce_addr;
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if (bsc->sc_dmadir != BSHW_READ)
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bcopy(sp->data, sp->bufp, sp->seglen);
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#ifdef BS_STATICS
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bs_bounce_used[ti->ti_id]++;
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#endif /* BS_STATICS */
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}
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else
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{
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/* setup segaddr */
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sp->segaddr = (u_int8_t *) phys;
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/* setup seglen */
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endva = (vm_offset_t)round_page(sp->data + sp->datalen);
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for (va = (vm_offset_t) sp->data; ; phys = nphys)
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{
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if ((va += BSHW_NBPG) >= endva)
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{
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sp->seglen = sp->datalen;
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break;
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}
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nphys = vtophys(va);
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if (phys + BSHW_NBPG != nphys || nphys >= RAM_END)
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{
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sp->seglen =
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(u_int8_t *) trunc_page(va) - sp->data;
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break;
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}
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}
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/* setup bufp */
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sp->bufp = NULL;
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}
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}
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bshw_dmastart(bsc);
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bshw_set_count(bsc, sp->seglen);
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}
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void
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bs_dma_xfer_end(ti)
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struct targ_info *ti;
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{
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struct bs_softc *bsc = ti->ti_bsc;
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struct sc_p *sp = &bsc->sc_p;
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u_int count, transbytes;
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bshw_dmadone(bsc);
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if (ti->ti_phase == DATAPHASE)
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{
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count = bshw_get_count(bsc);
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if (count < (u_int) sp->seglen)
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{
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transbytes = sp->seglen - count;
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if (sp->bufp)
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{
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if (bsc->sc_dmadir == BSHW_READ)
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bcopy(sp->bufp, sp->data, transbytes);
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sp->bufp += transbytes;
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}
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sp->seglen = count;
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sp->segaddr += transbytes;
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sp->data += transbytes;
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sp->datalen -= transbytes;
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return;
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}
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else if (count == (u_int) sp->seglen)
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{
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return;
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}
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bs_printf(ti, "xfer_end", "strange count");
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printf("port data %x seglen %x\n", count, sp->seglen);
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}
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else
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bs_printf(ti, "xfer_end", "extra dma interrupt");
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ti->ti_error |= BSDMAABNORMAL;
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sp->seglen = ti->ti_scsp.seglen = 0; /* XXX */
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}
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/**********************************************
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* GENERIC DMA FUNCS
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**********************************************/
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static short dmapageport[4] = { 0x27, 0x21, 0x23, 0x25 };
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/* common dma settings */
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#undef DMA1_SMSK
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#define DMA1_SMSK (IO_DMA + 0x14)
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#undef DMA1_MODE
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#define DMA1_MODE (IO_DMA + 0x16)
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#undef DMA1_FFC
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#define DMA1_FFC (IO_DMA + 0x18)
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#undef DMA37SM_SET
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#define DMA37SM_SET 0x04
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#undef DMA1_CHN
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#define DMA1_CHN(c) (IO_DMA + ((c) << 2))
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static BS_INLINE void
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bshw_dmastart(bsc)
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struct bs_softc *bsc;
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{
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int chan = bsc->sc_dmachan;
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int waport;
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u_int8_t *phys = bsc->sc_p.segaddr;
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u_int nbytes = bsc->sc_p.seglen;
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/*
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* Program one of DMA channels 0..3. These are
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* byte mode channels.
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*/
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/* set dma channel mode, and reset address ff */
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#ifdef __FreeBSD__
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if (need_pre_dma_flush)
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wbinvd();
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#else /* NetBSD/pc98 */
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if (cpuspec->cpuspec_cache_flush_before)
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(*cpuspec->cpuspec_cache_flush_before)();
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#endif
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if (bsc->sc_dmadir & BSHW_READ)
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outb(DMA1_MODE, DMA37MD_SINGLE | DMA37MD_WRITE | chan);
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else
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outb(DMA1_MODE, DMA37MD_SINGLE | DMA37MD_READ | chan);
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outb(DMA1_FFC, 0);
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/* send start address */
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waport = DMA1_CHN(chan);
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outb(waport, (u_int) phys);
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outb(waport, ((u_int) phys) >> 8);
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outb(dmapageport[chan], ((u_int) phys) >> 16);
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/* send count */
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outb(waport + 2, --nbytes);
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outb(waport + 2, nbytes >> 8);
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/* vendor unique hook */
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if (bsc->sc_hw->dma_start)
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(*bsc->sc_hw->dma_start)(bsc);
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outb(DMA1_SMSK, chan);
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BUS_IOW(cmd_port, CMDP_DMES);
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bsc->sc_flags |= BSDMASTART;
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}
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static void
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bshw_dmadone(bsc)
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struct bs_softc *bsc;
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{
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outb(DMA1_SMSK, (bsc->sc_dmachan | DMA37SM_SET));
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BUS_IOW(cmd_port, CMDP_DMER);
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/* vendor unique hook */
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if (bsc->sc_hw->dma_stop)
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(*bsc->sc_hw->dma_stop)(bsc);
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#ifdef __FreeBSD__
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if (need_post_dma_flush)
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invd();
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#else
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if (cpuspec->cpuspec_cache_flush_after)
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(*cpuspec->cpuspec_cache_flush_after)();
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#endif
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bsc->sc_flags &= (~BSDMASTART);
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}
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/**********************************************
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* VENDOR UNIQUE DMA FUNCS
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**********************************************/
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static int
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bshw_dma_init_texa(bsc)
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struct bs_softc *bsc;
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{
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u_int8_t regval;
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if ((regval = read_wd33c93(bsc, 0x37)) & 0x08)
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return 0;
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write_wd33c93(bsc, 0x37, regval | 0x08);
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regval = read_wd33c93(bsc, 0x3f);
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write_wd33c93(bsc, 0x3f, regval | 0x08);
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return 1;
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}
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static int
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bshw_dma_init_sc98(bsc)
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struct bs_softc *bsc;
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{
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if (read_wd33c93(bsc, 0x37) & 0x08)
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return 0;
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/* If your card is SC98 with bios ver 1.01 or 1.02 under no PCI */
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write_wd33c93(bsc, 0x37, 0x1a);
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write_wd33c93(bsc, 0x3f, 0x1a);
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#if 0
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/* only valid for IO */
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write_wd33c93(bsc, 0x40, 0xf4);
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write_wd33c93(bsc, 0x41, 0x9);
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write_wd33c93(bsc, 0x43, 0xff);
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write_wd33c93(bsc, 0x46, 0x4e);
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write_wd33c93(bsc, 0x48, 0xf4);
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write_wd33c93(bsc, 0x49, 0x9);
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write_wd33c93(bsc, 0x4b, 0xff);
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write_wd33c93(bsc, 0x4e, 0x4e);
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#endif
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return 1;
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}
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static void
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bshw_dma_start_sc98(bsc)
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struct bs_softc *bsc;
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{
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write_wd33c93(bsc, 0x73, 0x32);
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write_wd33c93(bsc, 0x74, 0x23);
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}
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static void
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bshw_dma_stop_sc98(bsc)
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struct bs_softc *bsc;
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{
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write_wd33c93(bsc, 0x73, 0x43);
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write_wd33c93(bsc, 0x74, 0x34);
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}
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static void
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bshw_dma_start_elecom(bsc)
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struct bs_softc *bsc;
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{
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u_int8_t tmp = read_wd33c93(bsc, 0x4c);
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write_wd33c93(bsc, 0x32, tmp & 0xdf);
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}
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static void
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bshw_dma_stop_elecom(bsc)
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struct bs_softc *bsc;
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{
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u_int8_t tmp = read_wd33c93(bsc, 0x4c);
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write_wd33c93(bsc, 0x32, tmp | 0x20);
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}
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