afa8862328
a heavily stripped down FreeBSD/i386 (brutally stripped down actually) to attempt to get a stable base to start from. There is a lot missing still. Worth noting: - The kernel runs at 1GB in order to cheat with the pmap code. pmap uses a variation of the PAE code in order to avoid having to worry about 4 levels of page tables yet. - It boots in 64 bit "long mode" with a tiny trampoline embedded in the i386 loader. This simplifies locore.s greatly. - There are still quite a few fragments of i386-specific code that have not been translated yet, and some that I cheated and wrote dumb C versions of (bcopy etc). - It has both int 0x80 for syscalls (but using registers for argument passing, as is native on the amd64 ABI), and the 'syscall' instruction for syscalls. int 0x80 preserves all registers, 'syscall' does not. - I have tried to minimize looking at the NetBSD code, except in a couple of places (eg: to find which register they use to replace the trashed %rcx register in the syscall instruction). As a result, there is not a lot of similarity. I did look at NetBSD a few times while debugging to get some ideas about what I might have done wrong in my first attempt.
153 lines
5.3 KiB
C
153 lines
5.3 KiB
C
/*-
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* Copyright (c) 1990 The Regents of the University of California.
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* All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* William Jolitz.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* from: @(#)icu.h 5.6 (Berkeley) 5/9/91
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* $FreeBSD$
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*/
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/*
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* AT/386 Interrupt Control constants
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* W. Jolitz 8/89
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*/
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#ifndef _I386_ISA_ICU_H_
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#define _I386_ISA_ICU_H_
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#ifndef LOCORE
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/*
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* Note:
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* Most of the SMP equivilants of the icu macros are coded
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* elsewhere in an MP-safe fashion.
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* In particular note that the 'imen' variable is opaque.
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* DO NOT access imen directly, use INTREN()/INTRDIS().
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*/
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void INTREN(u_int);
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void INTRDIS(u_int);
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extern unsigned imen; /* interrupt mask enable */
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#endif /* LOCORE */
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/*
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* Interrupt enable bits - in normal order of priority (which we change)
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*/
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#define IRQ0 0x0001 /* highest priority - timer */
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#define IRQ1 0x0002
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#define IRQ_SLAVE 0x0004
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#define IRQ8 0x0100
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#define IRQ9 0x0200
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#define IRQ2 IRQ9
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#define IRQ10 0x0400
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#define IRQ11 0x0800
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#define IRQ12 0x1000
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#define IRQ13 0x2000
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#define IRQ14 0x4000
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#define IRQ15 0x8000
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#define IRQ3 0x0008 /* this is highest after rotation */
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#define IRQ4 0x0010
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#define IRQ5 0x0020
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#define IRQ6 0x0040
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#define IRQ7 0x0080 /* lowest - parallel printer */
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/* Initialization control word 1. Written to even address. */
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#define ICW1_IC4 0x01 /* ICW4 present */
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#define ICW1_SNGL 0x02 /* 1 = single, 0 = cascaded */
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#define ICW1_ADI 0x04 /* 1 = 4, 0 = 8 byte vectors */
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#define ICW1_LTIM 0x08 /* 1 = level trigger, 0 = edge */
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#define ICW1_RESET 0x10 /* must be 1 */
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/* 0x20 - 0x80 - in 8080/8085 mode only */
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/* Initialization control word 2. Written to the odd address. */
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/* No definitions, it is the base vector of the IDT for 8086 mode */
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/* Initialization control word 3. Written to the odd address. */
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/* For a master PIC, bitfield indicating a slave 8259 on given input */
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/* For slave, lower 3 bits are the slave's ID binary id on master */
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/* Initialization control word 4. Written to the odd address. */
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#define ICW4_8086 0x01 /* 1 = 8086, 0 = 8080 */
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#define ICW4_AEOI 0x02 /* 1 = Auto EOI */
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#define ICW4_MS 0x04 /* 1 = buffered master, 0 = slave */
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#define ICW4_BUF 0x08 /* 1 = enable buffer mode */
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#define ICW4_SFNM 0x10 /* 1 = special fully nested mode */
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/* Operation control words. Written after initialization. */
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/* Operation control word type 1 */
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/*
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* No definitions. Written to the odd address. Bitmask for interrupts.
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* 1 = disabled.
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*/
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/* Operation control word type 2. Bit 3 (0x08) must be zero. Even address. */
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#define OCW2_L0 0x01 /* Level */
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#define OCW2_L1 0x02
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#define OCW2_L2 0x04
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/* 0x08 must be 0 to select OCW2 vs OCW3 */
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/* 0x10 must be 0 to select OCW2 vs ICW1 */
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#define OCW2_EOI 0x20 /* 1 = EOI */
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#define OCW2_SL 0x40 /* EOI mode */
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#define OCW2_R 0x80 /* EOI mode */
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/* Operation control word type 3. Bit 3 (0x08) must be set. Even address. */
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#define OCW3_RIS 0x01
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#define OCW3_RR 0x02
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#define OCW3_P 0x04
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/* 0x08 must be 1 to select OCW3 vs OCW2 */
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#define OCW3_SEL 0x08 /* must be 1 */
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/* 0x10 must be 0 to select OCW3 vs ICW1 */
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#define OCW3_SMM 0x20 /* special mode mask */
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#define OCW3_ESMM 0x40 /* enable SMM */
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/*
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* Interrupt Control offset into Interrupt descriptor table (IDT)
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*/
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#define ICU_OFFSET 32 /* 0-31 are processor exceptions */
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#define ICU_LEN 16 /* 32-47 are ISA interrupts */
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#define HWI_MASK 0xffff /* bits for h/w interrupts */
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#define NHWI 16
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#define ICU_IMR_OFFSET 1
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#define ICU_SLAVEID 2
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#define ICU_EOI (OCW2_EOI) /* non-specific EOI */
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#define ICU_SETPRI (OCW2_R | OCW2_SL) /* set rotation priority */
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#define INTRCNT_COUNT (1 + ICU_LEN + 2 * ICU_LEN)
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#endif /* !_I386_ISA_ICU_H_ */
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