b439e431bf
passing a pointer to an opaque clockframe structure and requiring the MD code to supply CLKF_FOO() macros to extract needed values out of the opaque structure, just pass the needed values directly. In practice this means passing the pair (usermode, pc) to hardclock() and profclock() and passing the boolean (usermode) to hardclock_cpu() and hardclock_process(). Other details: - Axe clockframe and CLKF_FOO() macros on all architectures. Basically, all the archs were taking a trapframe and converting it into a clockframe one way or another. Now they can just extract the PC and usermode values directly out of the trapframe and pass it to fooclock(). - Renamed hardclock_process() to hardclock_cpu() as the latter is more accurate. - On Alpha, we now run profclock() at hz (profhz == hz) rather than at the slower stathz. - On Alpha, for the TurboLaser machines that don't have an 8254 timecounter, call hardclock() directly. This removes an extra conditional check from every clock interrupt on Alpha on the BSP. There is probably room for even further pruning here by changing Alpha to use the simplified timecounter we use on x86 with the lapic timer since we don't get interrupts from the 8254 on Alpha anyway. - On x86, clkintr() shouldn't ever be called now unless using_lapic_timer is false, so add a KASSERT() to that affect and remove a condition to slightly optimize the non-lapic case. - Change prototypeof arm_handler_execute() so that it's first arg is a trapframe pointer rather than a void pointer for clarity. - Use KCOUNT macro in profclock() to lookup the kernel profiling bucket. Tested on: alpha, amd64, arm, i386, ia64, sparc64 Reviewed by: bde (mostly)
403 lines
8.3 KiB
C
403 lines
8.3 KiB
C
/* $NetBSD: i80321_timer.c,v 1.7 2003/07/27 04:52:28 thorpej Exp $ */
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/*-
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* Copyright (c) 2001, 2002 Wasabi Systems, Inc.
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* All rights reserved.
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*
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* Written by Jason R. Thorpe for Wasabi Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for the NetBSD Project by
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* Wasabi Systems, Inc.
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* 4. The name of Wasabi Systems, Inc. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Timer/clock support for the Intel i80321 I/O processor.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/time.h>
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#include <sys/bus.h>
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#include <sys/resource.h>
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#include <sys/rman.h>
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#include <sys/timetc.h>
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#include <machine/bus.h>
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#include <machine/cpu.h>
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#include <machine/cpufunc.h>
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#include <machine/frame.h>
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#include <machine/resource.h>
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#include <machine/intr.h>
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#include <arm/xscale/i80321/i80321reg.h>
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#include <arm/xscale/i80321/i80321var.h>
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#include <arm/xscale/xscalevar.h>
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#include "opt_timer.h"
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void (*i80321_hardclock_hook)(void) = NULL;
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struct i80321_timer_softc {
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device_t dev;
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} timer_softc;
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static unsigned i80321_timer_get_timecount(struct timecounter *tc);
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static uint32_t counts_per_hz;
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static int ticked = 0;
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#ifndef COUNTS_PER_SEC
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#define COUNTS_PER_SEC 200000000 /* 200MHz */
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#endif
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#define COUNTS_PER_USEC (COUNTS_PER_SEC / 1000000)
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static struct timecounter i80321_timer_timecounter = {
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i80321_timer_get_timecount, /* get_timecount */
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NULL, /* no poll_pps */
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~0u, /* counter_mask */
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COUNTS_PER_SEC * 3, /* frequency */
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"i80321 timer", /* name */
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1000 /* quality */
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};
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static int
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i80321_timer_probe(device_t dev)
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{
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device_set_desc(dev, "i80321 timer");
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return (0);
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}
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static int
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i80321_timer_attach(device_t dev)
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{
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timer_softc.dev = dev;
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return (0);
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}
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static device_method_t i80321_timer_methods[] = {
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DEVMETHOD(device_probe, i80321_timer_probe),
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DEVMETHOD(device_attach, i80321_timer_attach),
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{0, 0},
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};
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static driver_t i80321_timer_driver = {
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"itimer",
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i80321_timer_methods,
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sizeof(struct i80321_timer_softc),
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};
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static devclass_t i80321_timer_devclass;
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DRIVER_MODULE(itimer, iq, i80321_timer_driver, i80321_timer_devclass, 0, 0);
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void counterhandler(void *);
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void clockhandler(void *);
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static __inline uint32_t
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tmr1_read(void)
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{
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uint32_t rv;
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__asm __volatile("mrc p6, 0, %0, c1, c1, 0"
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: "=r" (rv));
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return (rv);
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}
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static __inline void
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tmr1_write(uint32_t val)
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{
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__asm __volatile("mcr p6, 0, %0, c1, c1, 0"
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:
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: "r" (val));
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}
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static __inline uint32_t
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tcr1_read(void)
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{
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uint32_t rv;
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__asm __volatile("mrc p6, 0, %0, c3, c1, 0"
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: "=r" (rv));
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return (rv);
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}
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static __inline void
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tcr1_write(uint32_t val)
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{
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__asm __volatile("mcr p6, 0, %0, c3, c1, 0"
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:
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: "r" (val));
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}
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static __inline void
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trr1_write(uint32_t val)
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{
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__asm __volatile("mcr p6, 1, %0, c5, c1, 0"
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:
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: "r" (val));
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}
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static __inline uint32_t
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tmr0_read(void)
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{
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uint32_t rv;
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__asm __volatile("mrc p6, 0, %0, c0, c1, 0"
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: "=r" (rv));
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return (rv);
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}
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static __inline void
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tmr0_write(uint32_t val)
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{
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__asm __volatile("mcr p6, 0, %0, c0, c1, 0"
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:
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: "r" (val));
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}
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static __inline uint32_t
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tcr0_read(void)
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{
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uint32_t rv;
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__asm __volatile("mrc p6, 0, %0, c2, c1, 0"
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: "=r" (rv));
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return (rv);
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}
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static __inline void
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tcr0_write(uint32_t val)
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{
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__asm __volatile("mcr p6, 0, %0, c2, c1, 0"
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:
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: "r" (val));
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}
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static __inline void
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trr0_write(uint32_t val)
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{
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__asm __volatile("mcr p6, 0, %0, c4, c1, 0"
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:
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: "r" (val));
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}
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static __inline void
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tisr_write(uint32_t val)
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{
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__asm __volatile("mcr p6, 0, %0, c6, c1, 0"
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:
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: "r" (val));
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}
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static __inline uint32_t
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tisr_read(void)
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{
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int ret;
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__asm __volatile("mrc p6, 0, %0, c6, c1, 0" : "=r" (ret));
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return (ret);
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}
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static unsigned
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i80321_timer_get_timecount(struct timecounter *tc)
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{
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uint32_t ret;
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__asm __volatile("mrc p14, 0, %0, c1, c0, 0\n"
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: "=r" (ret));
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return (ret);
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}
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/*
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* i80321_calibrate_delay:
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*
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* Calibrate the delay loop.
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*/
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void
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i80321_calibrate_delay(void)
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{
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/*
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* Just use hz=100 for now -- we'll adjust it, if necessary,
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* in cpu_initclocks().
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*/
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counts_per_hz = COUNTS_PER_SEC / 100;
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tmr0_write(0); /* stop timer */
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tisr_write(TISR_TMR0); /* clear interrupt */
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trr0_write(counts_per_hz); /* reload value */
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tcr0_write(counts_per_hz); /* current value */
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tmr0_write(TMRx_ENABLE|TMRx_RELOAD|TMRx_CSEL_CORE);
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}
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/*
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* cpu_initclocks:
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*
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* Initialize the clock and get them going.
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*/
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void
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cpu_initclocks(void)
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{
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u_int oldirqstate;
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struct resource *irq;
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int rid = 0;
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void *ihl;
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device_t dev = timer_softc.dev;
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if (hz < 50 || COUNTS_PER_SEC % hz) {
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printf("Cannot get %d Hz clock; using 100 Hz\n", hz);
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hz = 100;
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}
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tick = 1000000 / hz; /* number of microseconds between interrupts */
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/*
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* We only have one timer available; stathz and profhz are
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* always left as 0 (the upper-layer clock code deals with
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* this situation).
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*/
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if (stathz != 0)
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printf("Cannot get %d Hz statclock\n", stathz);
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stathz = 0;
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if (profhz != 0)
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printf("Cannot get %d Hz profclock\n", profhz);
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profhz = 0;
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/* Report the clock frequency. */
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oldirqstate = disable_interrupts(I32_bit);
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irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, ICU_INT_TMR0,
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ICU_INT_TMR0, 1, RF_ACTIVE);
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if (!irq)
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panic("Unable to setup the clock irq handler.\n");
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else
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bus_setup_intr(dev, irq, INTR_TYPE_CLK | INTR_FAST,
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clockhandler, NULL, &ihl);
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tmr0_write(0); /* stop timer */
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tisr_write(TISR_TMR0); /* clear interrupt */
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counts_per_hz = COUNTS_PER_SEC / hz;
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trr0_write(counts_per_hz); /* reload value */
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tcr0_write(counts_per_hz); /* current value */
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tmr0_write(TMRx_ENABLE|TMRx_RELOAD|TMRx_CSEL_CORE);
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tc_init(&i80321_timer_timecounter);
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restore_interrupts(oldirqstate);
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rid = 0;
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/* Enable the clock count register. */
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__asm __volatile("mrc p14, 0, %0, c0, c0, 0\n" : "=r" (rid));
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rid &= ~(1 << 3);
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rid |= (1 << 2) | 1;
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__asm __volatile("mcr p14, 0, %0, c0, c0, 0\n"
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: : "r" (rid));
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}
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/*
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* DELAY:
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*
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* Delay for at least N microseconds.
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*/
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void
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DELAY(int n)
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{
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uint32_t cur, last, delta, usecs;
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/*
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* This works by polling the timer and counting the
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* number of microseconds that go by.
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*/
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last = tcr0_read();
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delta = usecs = 0;
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while (n > usecs) {
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cur = tcr0_read();
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/* Check to see if the timer has wrapped around. */
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if (last < cur)
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delta += (last + (counts_per_hz - cur));
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else
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delta += (last - cur);
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last = cur;
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if (delta >= COUNTS_PER_USEC) {
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usecs += delta / COUNTS_PER_USEC;
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delta %= COUNTS_PER_USEC;
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}
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}
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}
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/*
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* clockhandler:
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*
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* Handle the hardclock interrupt.
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*/
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void
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clockhandler(void *arg)
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{
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struct trapframe *frame = arg;
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ticked++;
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tisr_write(TISR_TMR0);
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hardclock(TRAPF_USERMODE(frame), TRAPF_PC(frame));
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if (i80321_hardclock_hook != NULL)
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(*i80321_hardclock_hook)();
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return;
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}
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void
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cpu_startprofclock(void)
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{
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}
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void
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cpu_stopprofclock(void)
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{
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}
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