6ce70ec7f9
Mainly focus on files that use BSD 2-Clause license, however the tool I was using misidentified many licenses so this was mostly a manual - error prone - task. The Software Package Data Exchange (SPDX) group provides a specification to make it easier for automated tools to detect and summarize well known opensource licenses. We are gradually adopting the specification, noting that the tags are considered only advisory and do not, in any way, superceed or replace the license texts.
765 lines
20 KiB
C
765 lines
20 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD AND BSD-2-Clause-NetBSD
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*
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* Copyright (c) 2004 Scott Long
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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/* $NetBSD: lsi64854.c,v 1.33 2008/04/28 20:23:50 martin Exp $ */
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/*-
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* Copyright (c) 1998 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Paul Kranenburg.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/rman.h>
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#include <machine/bus.h>
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#include <cam/cam.h>
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#include <cam/cam_ccb.h>
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#include <cam/scsi/scsi_all.h>
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#include <sparc64/sbus/lsi64854reg.h>
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#include <sparc64/sbus/lsi64854var.h>
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#include <dev/esp/ncr53c9xreg.h>
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#include <dev/esp/ncr53c9xvar.h>
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#ifdef DEBUG
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#define LDB_SCSI 1
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#define LDB_ENET 2
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#define LDB_PP 4
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#define LDB_ANY 0xff
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int lsi64854debug = 0;
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#define DPRINTF(a,x) \
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do { \
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if ((lsi64854debug & (a)) != 0) \
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printf x; \
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} while (/* CONSTCOND */0)
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#else
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#define DPRINTF(a,x)
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#endif
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/*
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* The rules say we cannot transfer more than the limit of this DMA chip (64k
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* for old and 16Mb for new), and we cannot cross a 16Mb boundary.
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*/
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#define MAX_DMA_SZ (64 * 1024)
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#define BOUNDARY (16 * 1024 * 1024)
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static void lsi64854_reset(struct lsi64854_softc *);
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static void lsi64854_map_scsi(void *, bus_dma_segment_t *, int, int);
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static int lsi64854_setup(struct lsi64854_softc *, void **, size_t *,
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int, size_t *);
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static int lsi64854_scsi_intr(void *);
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static int lsi64854_enet_intr(void *);
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static int lsi64854_setup_pp(struct lsi64854_softc *, void **,
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size_t *, int, size_t *);
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static int lsi64854_pp_intr(void *);
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/*
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* Finish attaching this DMA device.
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* Front-end must fill in these fields:
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* sc_res
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* sc_burst
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* sc_channel (one of SCSI, ENET, PP)
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* sc_client (one of SCSI, ENET, PP `soft_c' pointers)
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*/
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int
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lsi64854_attach(struct lsi64854_softc *sc)
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{
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bus_dma_lock_t *lockfunc;
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struct ncr53c9x_softc *nsc;
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void *lockfuncarg;
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uint32_t csr;
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int error;
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lockfunc = NULL;
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lockfuncarg = NULL;
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sc->sc_maxdmasize = MAX_DMA_SZ;
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switch (sc->sc_channel) {
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case L64854_CHANNEL_SCSI:
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nsc = sc->sc_client;
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if (NCR_LOCK_INITIALIZED(nsc) == 0) {
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device_printf(sc->sc_dev, "mutex not initialized\n");
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return (ENXIO);
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}
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lockfunc = busdma_lock_mutex;
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lockfuncarg = &nsc->sc_lock;
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sc->sc_maxdmasize = nsc->sc_maxxfer;
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sc->intr = lsi64854_scsi_intr;
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sc->setup = lsi64854_setup;
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break;
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case L64854_CHANNEL_ENET:
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sc->intr = lsi64854_enet_intr;
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break;
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case L64854_CHANNEL_PP:
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sc->intr = lsi64854_pp_intr;
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sc->setup = lsi64854_setup_pp;
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break;
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default:
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device_printf(sc->sc_dev, "unknown channel\n");
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}
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sc->reset = lsi64854_reset;
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if (sc->setup != NULL) {
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error = bus_dma_tag_create(
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sc->sc_parent_dmat, /* parent */
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1, BOUNDARY, /* alignment, boundary */
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BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
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BUS_SPACE_MAXADDR, /* highaddr */
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NULL, NULL, /* filter, filterarg */
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sc->sc_maxdmasize, /* maxsize */
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1, /* nsegments */
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sc->sc_maxdmasize, /* maxsegsize */
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BUS_DMA_ALLOCNOW, /* flags */
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lockfunc, lockfuncarg, /* lockfunc, lockfuncarg */
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&sc->sc_buffer_dmat);
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if (error != 0) {
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device_printf(sc->sc_dev,
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"cannot allocate buffer DMA tag\n");
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return (error);
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}
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error = bus_dmamap_create(sc->sc_buffer_dmat, 0,
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&sc->sc_dmamap);
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if (error != 0) {
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device_printf(sc->sc_dev, "DMA map create failed\n");
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bus_dma_tag_destroy(sc->sc_buffer_dmat);
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return (error);
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}
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}
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csr = L64854_GCSR(sc);
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sc->sc_rev = csr & L64854_DEVID;
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if (sc->sc_rev == DMAREV_HME)
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return (0);
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device_printf(sc->sc_dev, "DMA rev. ");
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switch (sc->sc_rev) {
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case DMAREV_0:
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printf("0");
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break;
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case DMAREV_ESC:
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printf("ESC");
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break;
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case DMAREV_1:
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printf("1");
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break;
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case DMAREV_PLUS:
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printf("1+");
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break;
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case DMAREV_2:
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printf("2");
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break;
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default:
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printf("unknown (0x%x)", sc->sc_rev);
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}
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DPRINTF(LDB_ANY, (", burst 0x%x, csr 0x%x", sc->sc_burst, csr));
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printf("\n");
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return (0);
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}
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int
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lsi64854_detach(struct lsi64854_softc *sc)
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{
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if (sc->setup != NULL) {
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bus_dmamap_sync(sc->sc_buffer_dmat, sc->sc_dmamap,
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(L64854_GCSR(sc) & L64854_WRITE) != 0 ?
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BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
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bus_dmamap_unload(sc->sc_buffer_dmat, sc->sc_dmamap);
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bus_dmamap_destroy(sc->sc_buffer_dmat, sc->sc_dmamap);
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bus_dma_tag_destroy(sc->sc_buffer_dmat);
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}
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return (0);
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}
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/*
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* DMAWAIT waits while condition is true.
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*/
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#define DMAWAIT(SC, COND, MSG, DONTPANIC) do if (COND) { \
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int count = 500000; \
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while ((COND) && --count > 0) DELAY(1); \
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if (count == 0) { \
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printf("%s: line %d: CSR = 0x%lx\n", __FILE__, __LINE__, \
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(u_long)L64854_GCSR(SC)); \
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if (DONTPANIC) \
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printf(MSG); \
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else \
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panic(MSG); \
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} \
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} while (/* CONSTCOND */0)
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#define DMA_DRAIN(sc, dontpanic) do { \
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uint32_t csr; \
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/* \
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* DMA rev0 & rev1: we are not allowed to touch the DMA "flush" \
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* and "drain" bits while it is still thinking about a \
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* request. \
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* other revs: D_ESC_R_PEND bit reads as 0 \
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*/ \
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DMAWAIT(sc, L64854_GCSR(sc) & D_ESC_R_PEND, "R_PEND", dontpanic);\
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if (sc->sc_rev != DMAREV_HME) { \
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/* \
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* Select drain bit based on revision \
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* also clears errors and D_TC flag \
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*/ \
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csr = L64854_GCSR(sc); \
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if (sc->sc_rev == DMAREV_1 || sc->sc_rev == DMAREV_0) \
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csr |= D_ESC_DRAIN; \
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else \
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csr |= L64854_INVALIDATE; \
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\
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L64854_SCSR(sc, csr); \
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} \
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/* \
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* Wait for draining to finish \
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* rev0 & rev1 call this PACKCNT \
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*/ \
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DMAWAIT(sc, L64854_GCSR(sc) & L64854_DRAINING, "DRAINING", \
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dontpanic); \
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} while (/* CONSTCOND */0)
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#define DMA_FLUSH(sc, dontpanic) do { \
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uint32_t csr; \
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/* \
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* DMA rev0 & rev1: we are not allowed to touch the DMA "flush" \
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* and "drain" bits while it is still thinking about a \
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* request. \
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* other revs: D_ESC_R_PEND bit reads as 0 \
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*/ \
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DMAWAIT(sc, L64854_GCSR(sc) & D_ESC_R_PEND, "R_PEND", dontpanic);\
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csr = L64854_GCSR(sc); \
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csr &= ~(L64854_WRITE|L64854_EN_DMA); /* no-ops on ENET */ \
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csr |= L64854_INVALIDATE; /* XXX FAS ? */ \
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L64854_SCSR(sc, csr); \
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} while (/* CONSTCOND */0)
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static void
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lsi64854_reset(struct lsi64854_softc *sc)
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{
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bus_dma_tag_t dmat;
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bus_dmamap_t dmam;
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uint32_t csr;
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DMA_FLUSH(sc, 1);
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csr = L64854_GCSR(sc);
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DPRINTF(LDB_ANY, ("%s: csr 0x%x\n", __func__, csr));
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if (sc->sc_dmasize != 0) {
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dmat = sc->sc_buffer_dmat;
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dmam = sc->sc_dmamap;
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bus_dmamap_sync(dmat, dmam, (csr & D_WRITE) != 0 ?
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BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
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bus_dmamap_unload(dmat, dmam);
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}
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if (sc->sc_rev == DMAREV_HME)
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L64854_SCSR(sc, csr | D_HW_RESET_FAS366);
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csr |= L64854_RESET; /* reset DMA */
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L64854_SCSR(sc, csr);
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DELAY(200); /* > 10 Sbus clocks(?) */
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/*DMAWAIT1(sc); why was this here? */
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csr = L64854_GCSR(sc);
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csr &= ~L64854_RESET; /* de-assert reset line */
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L64854_SCSR(sc, csr);
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DELAY(5); /* allow a few ticks to settle */
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csr = L64854_GCSR(sc);
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csr |= L64854_INT_EN; /* enable interrupts */
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if (sc->sc_rev > DMAREV_1 && sc->sc_channel == L64854_CHANNEL_SCSI) {
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if (sc->sc_rev == DMAREV_HME)
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csr |= D_TWO_CYCLE;
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else
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csr |= D_FASTER;
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}
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/* Set burst */
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switch (sc->sc_rev) {
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case DMAREV_HME:
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case DMAREV_2:
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csr &= ~L64854_BURST_SIZE;
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if (sc->sc_burst == 32)
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csr |= L64854_BURST_32;
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else if (sc->sc_burst == 16)
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csr |= L64854_BURST_16;
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else
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csr |= L64854_BURST_0;
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break;
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case DMAREV_ESC:
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csr |= D_ESC_AUTODRAIN; /* Auto-drain */
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if (sc->sc_burst == 32)
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csr &= ~D_ESC_BURST;
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else
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csr |= D_ESC_BURST;
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break;
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default:
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break;
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}
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L64854_SCSR(sc, csr);
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if (sc->sc_rev == DMAREV_HME) {
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bus_write_4(sc->sc_res, L64854_REG_ADDR, 0);
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sc->sc_dmactl = csr;
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}
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sc->sc_active = 0;
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DPRINTF(LDB_ANY, ("%s: done, csr 0x%x\n", __func__, csr));
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}
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static void
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lsi64854_map_scsi(void *arg, bus_dma_segment_t *segs, int nseg, int error)
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{
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struct lsi64854_softc *sc;
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sc = (struct lsi64854_softc *)arg;
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if (error != 0)
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return;
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if (nseg != 1)
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panic("%s: cannot map %d segments\n", __func__, nseg);
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bus_dmamap_sync(sc->sc_buffer_dmat, sc->sc_dmamap,
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sc->sc_datain != 0 ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
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bus_write_4(sc->sc_res, L64854_REG_ADDR, segs[0].ds_addr);
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}
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/*
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* setup a DMA transfer
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*/
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static int
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lsi64854_setup(struct lsi64854_softc *sc, void **addr, size_t *len,
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int datain, size_t *dmasize)
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{
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long bcnt;
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int error;
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uint32_t csr;
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DMA_FLUSH(sc, 0);
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#if 0
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DMACSR(sc) &= ~D_INT_EN;
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#endif
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sc->sc_dmaaddr = addr;
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sc->sc_dmalen = len;
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sc->sc_datain = datain;
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KASSERT(*dmasize <= sc->sc_maxdmasize,
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("%s: transfer size %ld too large", __func__, (long)*dmasize));
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sc->sc_dmasize = *dmasize;
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DPRINTF(LDB_ANY, ("%s: dmasize=%ld\n", __func__, (long)*dmasize));
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/*
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* XXX what length?
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*/
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if (sc->sc_rev == DMAREV_HME) {
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L64854_SCSR(sc, sc->sc_dmactl | L64854_RESET);
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L64854_SCSR(sc, sc->sc_dmactl);
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bus_write_4(sc->sc_res, L64854_REG_CNT, *dmasize);
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}
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/*
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* Load the transfer buffer and program the DMA address.
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* Note that the NCR53C9x core can't handle EINPROGRESS so we set
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* BUS_DMA_NOWAIT.
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*/
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if (*dmasize != 0) {
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error = bus_dmamap_load(sc->sc_buffer_dmat, sc->sc_dmamap,
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*sc->sc_dmaaddr, *dmasize, lsi64854_map_scsi, sc,
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BUS_DMA_NOWAIT);
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if (error != 0)
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return (error);
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}
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if (sc->sc_rev == DMAREV_ESC) {
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/* DMA ESC chip bug work-around */
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bcnt = *dmasize;
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if (((bcnt + (long)*sc->sc_dmaaddr) & PAGE_MASK_8K) != 0)
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bcnt = roundup(bcnt, PAGE_SIZE_8K);
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bus_write_4(sc->sc_res, L64854_REG_CNT, bcnt);
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}
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/* Setup the DMA control register. */
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csr = L64854_GCSR(sc);
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if (datain != 0)
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csr |= L64854_WRITE;
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else
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csr &= ~L64854_WRITE;
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csr |= L64854_INT_EN;
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if (sc->sc_rev == DMAREV_HME)
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csr |= (D_DSBL_SCSI_DRN | D_EN_DMA);
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L64854_SCSR(sc, csr);
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return (0);
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}
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/*
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* Pseudo (chained) interrupt from the esp driver to kick the
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* current running DMA transfer. Called from ncr53c9x_intr()
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* for now.
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*
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* return 1 if it was a DMA continue.
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*/
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static int
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lsi64854_scsi_intr(void *arg)
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{
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struct lsi64854_softc *sc = arg;
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struct ncr53c9x_softc *nsc = sc->sc_client;
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bus_dma_tag_t dmat;
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bus_dmamap_t dmam;
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size_t dmasize;
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int lxfer, resid, trans;
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uint32_t csr;
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csr = L64854_GCSR(sc);
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DPRINTF(LDB_SCSI, ("%s: addr 0x%x, csr %b\n", __func__,
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bus_read_4(sc->sc_res, L64854_REG_ADDR), csr, DDMACSR_BITS));
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if (csr & (D_ERR_PEND | D_SLAVE_ERR)) {
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device_printf(sc->sc_dev, "error: csr=%b\n", csr,
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DDMACSR_BITS);
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csr &= ~D_EN_DMA; /* Stop DMA. */
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/* Invalidate the queue; SLAVE_ERR bit is write-to-clear */
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csr |= D_INVALIDATE | D_SLAVE_ERR;
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L64854_SCSR(sc, csr);
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return (-1);
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}
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/* This is an "assertion" :) */
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if (sc->sc_active == 0)
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panic("%s: DMA wasn't active", __func__);
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DMA_DRAIN(sc, 0);
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/* DMA has stopped */
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csr &= ~D_EN_DMA;
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L64854_SCSR(sc, csr);
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sc->sc_active = 0;
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dmasize = sc->sc_dmasize;
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if (dmasize == 0) {
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/* A "Transfer Pad" operation completed. */
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DPRINTF(LDB_SCSI, ("%s: discarded %d bytes (tcl=%d, "
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"tcm=%d)\n", __func__, NCR_READ_REG(nsc, NCR_TCL) |
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(NCR_READ_REG(nsc, NCR_TCM) << 8),
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NCR_READ_REG(nsc, NCR_TCL), NCR_READ_REG(nsc, NCR_TCM)));
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return (0);
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}
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resid = 0;
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/*
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* If a transfer onto the SCSI bus gets interrupted by the device
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* (e.g. for a SAVEPOINTER message), the data in the FIFO counts
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* as residual since the NCR53C9X counter registers get decremented
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* as bytes are clocked into the FIFO.
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*/
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if ((csr & D_WRITE) == 0 &&
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(resid = (NCR_READ_REG(nsc, NCR_FFLAG) & NCRFIFO_FF)) != 0) {
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DPRINTF(LDB_SCSI, ("%s: empty esp FIFO of %d ", __func__,
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resid));
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if (nsc->sc_rev == NCR_VARIANT_FAS366 &&
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(NCR_READ_REG(nsc, NCR_CFG3) & NCRFASCFG3_EWIDE))
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resid <<= 1;
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}
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if ((nsc->sc_espstat & NCRSTAT_TC) == 0) {
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lxfer = nsc->sc_features & NCR_F_LARGEXFER;
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/*
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* "Terminal count" is off, so read the residue
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* out of the NCR53C9X counter registers.
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*/
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resid += (NCR_READ_REG(nsc, NCR_TCL) |
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(NCR_READ_REG(nsc, NCR_TCM) << 8) |
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(lxfer != 0 ? (NCR_READ_REG(nsc, NCR_TCH) << 16) : 0));
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if (resid == 0 && dmasize == 65536 && lxfer == 0)
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/* A transfer of 64k is encoded as TCL=TCM=0. */
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resid = 65536;
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}
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trans = dmasize - resid;
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if (trans < 0) { /* transferred < 0? */
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#if 0
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/*
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* This situation can happen in perfectly normal operation
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* if the ESP is reselected while using DMA to select
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* another target. As such, don't print the warning.
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*/
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device_printf(sc->sc_dev, "xfer (%d) > req (%d)\n", trans,
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dmasize);
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#endif
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trans = dmasize;
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}
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DPRINTF(LDB_SCSI, ("%s: tcl=%d, tcm=%d, tch=%d; trans=%d, resid=%d\n",
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__func__, NCR_READ_REG(nsc, NCR_TCL), NCR_READ_REG(nsc, NCR_TCM),
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(nsc->sc_features & NCR_F_LARGEXFER) != 0 ?
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NCR_READ_REG(nsc, NCR_TCH) : 0, trans, resid));
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if (dmasize != 0) {
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dmat = sc->sc_buffer_dmat;
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dmam = sc->sc_dmamap;
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bus_dmamap_sync(dmat, dmam, (csr & D_WRITE) != 0 ?
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BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
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bus_dmamap_unload(dmat, dmam);
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}
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*sc->sc_dmalen -= trans;
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*sc->sc_dmaaddr = (char *)*sc->sc_dmaaddr + trans;
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#if 0 /* this is not normal operation just yet */
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if (*sc->sc_dmalen == 0 || nsc->sc_phase != nsc->sc_prevphase)
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return (0);
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/* and again */
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dma_start(sc, sc->sc_dmaaddr, sc->sc_dmalen, DMACSR(sc) & D_WRITE);
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return (1);
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#endif
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return (0);
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}
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/*
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* Pseudo (chained) interrupt to le(4) driver to handle DMA errors
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*/
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static int
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lsi64854_enet_intr(void *arg)
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{
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struct lsi64854_softc *sc = arg;
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uint32_t csr;
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int i, rv;
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csr = L64854_GCSR(sc);
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/* If the DMA logic shows an interrupt, claim it */
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rv = ((csr & E_INT_PEND) != 0) ? 1 : 0;
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if (csr & (E_ERR_PEND | E_SLAVE_ERR)) {
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device_printf(sc->sc_dev, "error: csr=%b\n", csr,
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EDMACSR_BITS);
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csr &= ~L64854_EN_DMA; /* Stop DMA. */
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/* Invalidate the queue; SLAVE_ERR bit is write-to-clear */
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csr |= E_INVALIDATE | E_SLAVE_ERR;
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L64854_SCSR(sc, csr);
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/* Will be drained with the LE_C0_IDON interrupt. */
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sc->sc_dodrain = 1;
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return (-1);
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}
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/* XXX - is this necessary with E_DSBL_WR_INVAL on? */
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if (sc->sc_dodrain) {
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i = 10;
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csr |= E_DRAIN;
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L64854_SCSR(sc, csr);
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while (i-- > 0 && (L64854_GCSR(sc) & E_DRAINING))
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DELAY(1);
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sc->sc_dodrain = 0;
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}
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return (rv);
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}
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static void
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lsi64854_map_pp(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
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{
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struct lsi64854_softc *sc;
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sc = (struct lsi64854_softc *)arg;
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if (error != 0)
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return;
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if (nsegs != 1)
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panic("%s: cannot map %d segments\n", __func__, nsegs);
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bus_dmamap_sync(sc->sc_buffer_dmat, sc->sc_dmamap,
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sc->sc_datain != 0 ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
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bus_write_4(sc->sc_res, L64854_REG_ADDR, segs[0].ds_addr);
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bus_write_4(sc->sc_res, L64854_REG_CNT, sc->sc_dmasize);
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}
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/*
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* Setup a DMA transfer.
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*/
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static int
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lsi64854_setup_pp(struct lsi64854_softc *sc, void **addr, size_t *len,
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int datain, size_t *dmasize)
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{
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int error;
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uint32_t csr;
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DMA_FLUSH(sc, 0);
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sc->sc_dmaaddr = addr;
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sc->sc_dmalen = len;
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sc->sc_datain = datain;
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DPRINTF(LDB_PP, ("%s: pp start %ld@%p,%d\n", __func__,
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(long)*sc->sc_dmalen, *sc->sc_dmaaddr, datain != 0 ? 1 : 0));
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KASSERT(*dmasize <= sc->sc_maxdmasize,
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("%s: transfer size %ld too large", __func__, (long)*dmasize));
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sc->sc_dmasize = *dmasize;
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DPRINTF(LDB_PP, ("%s: dmasize=%ld\n", __func__, (long)*dmasize));
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/* Load the transfer buffer and program the DMA address. */
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if (*dmasize != 0) {
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error = bus_dmamap_load(sc->sc_buffer_dmat, sc->sc_dmamap,
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*sc->sc_dmaaddr, *dmasize, lsi64854_map_pp, sc,
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BUS_DMA_NOWAIT);
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if (error != 0)
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return (error);
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}
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/* Setup the DMA control register. */
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csr = L64854_GCSR(sc);
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csr &= ~L64854_BURST_SIZE;
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if (sc->sc_burst == 32)
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csr |= L64854_BURST_32;
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else if (sc->sc_burst == 16)
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csr |= L64854_BURST_16;
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else
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csr |= L64854_BURST_0;
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csr |= P_EN_DMA | P_INT_EN | P_EN_CNT;
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#if 0
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/* This bit is read-only in PP csr register. */
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if (datain != 0)
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csr |= P_WRITE;
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else
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csr &= ~P_WRITE;
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#endif
|
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L64854_SCSR(sc, csr);
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|
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return (0);
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}
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|
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/*
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* Parallel port DMA interrupt
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*/
|
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static int
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lsi64854_pp_intr(void *arg)
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{
|
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struct lsi64854_softc *sc = arg;
|
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bus_dma_tag_t dmat;
|
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bus_dmamap_t dmam;
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size_t dmasize;
|
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int ret, trans, resid = 0;
|
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uint32_t csr;
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|
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csr = L64854_GCSR(sc);
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|
|
DPRINTF(LDB_PP, ("%s: addr 0x%x, csr %b\n", __func__,
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bus_read_4(sc->sc_res, L64854_REG_ADDR), csr, PDMACSR_BITS));
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if ((csr & (P_ERR_PEND | P_SLAVE_ERR)) != 0) {
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resid = bus_read_4(sc->sc_res, L64854_REG_CNT);
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device_printf(sc->sc_dev, "error: resid %d csr=%b\n", resid,
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csr, PDMACSR_BITS);
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csr &= ~P_EN_DMA; /* Stop DMA. */
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|
/* Invalidate the queue; SLAVE_ERR bit is write-to-clear */
|
|
csr |= P_INVALIDATE | P_SLAVE_ERR;
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L64854_SCSR(sc, csr);
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return (-1);
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}
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|
|
ret = (csr & P_INT_PEND) != 0;
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|
|
if (sc->sc_active != 0) {
|
|
DMA_DRAIN(sc, 0);
|
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resid = bus_read_4(sc->sc_res, L64854_REG_CNT);
|
|
}
|
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|
|
/* DMA has stopped */
|
|
csr &= ~D_EN_DMA;
|
|
L64854_SCSR(sc, csr);
|
|
sc->sc_active = 0;
|
|
|
|
dmasize = sc->sc_dmasize;
|
|
trans = dmasize - resid;
|
|
if (trans < 0) /* transferred < 0? */
|
|
trans = dmasize;
|
|
*sc->sc_dmalen -= trans;
|
|
*sc->sc_dmaaddr = (char *)*sc->sc_dmaaddr + trans;
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|
|
|
if (dmasize != 0) {
|
|
dmat = sc->sc_buffer_dmat;
|
|
dmam = sc->sc_dmamap;
|
|
bus_dmamap_sync(dmat, dmam, (csr & D_WRITE) != 0 ?
|
|
BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
|
|
bus_dmamap_unload(dmat, dmam);
|
|
}
|
|
|
|
return (ret != 0);
|
|
}
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