8c8a1169df
1. At least some Netra t1 models have PCI buses with no associated interrupt map, but obviously expect the PCI swizzle to be done with the interrupt number from the higher level as intpin. In this case, the mapping also needs to continue at parent bus nodes. To handle that, add a quirk table based on the "name" property of the root node to avoid breaking other boxen. This property is now retrieved and printed at boot. 2. On SPARCengine Ultra AX machines, interrupt numbers are not mapped at all, and full interrupt numbers (not just INOs) are given in the interrupt properties. This is more or less cosmetical; the PCI interrupt numbers would be wrong, but the psycho resource allocation method would pass the right numbers on anyway. Tested by: mux (1), Maxim Mazurok <maxim@km.ua> (2)
83 lines
2.7 KiB
C
83 lines
2.7 KiB
C
/*
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* Copyright (c) 1999, 2000 Matthew R. Green
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* All rights reserved.
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* Copyright 2001 by Thomas Moestl <tmm@FreeBSD.org>. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* from: NetBSD: psychoreg.h,v 1.8 2001/09/10 16:17:06 eeh Exp
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*
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* $FreeBSD$
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*/
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#ifndef _SPARC64_PCI_OFW_PCI_H_
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#define _SPARC64_PCI_OFW_PCI_H_
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#include <machine/ofw_bus.h>
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/* PCI range child spaces. XXX: are these MI? */
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#define PCI_CS_CONFIG 0x00
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#define PCI_CS_IO 0x01
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#define PCI_CS_MEM32 0x02
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#define PCI_CS_MEM64 0x03
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struct ofw_pci_imap {
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u_int32_t phys_hi;
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u_int32_t phys_mid;
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u_int32_t phys_lo;
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u_int32_t intr;
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int32_t child_node;
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u_int32_t child_intr;
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};
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struct ofw_pci_imap_msk {
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u_int32_t phys_hi;
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u_int32_t phys_mid;
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u_int32_t phys_lo;
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u_int32_t intr;
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};
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struct ofw_pci_bdesc;
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typedef void ofw_pci_binit_t(device_t, struct ofw_pci_bdesc *);
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struct ofw_pci_bdesc {
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u_int obd_bus;
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u_int obd_slot;
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u_int obd_func;
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u_int obd_secbus;
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u_int obd_subbus;
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ofw_pci_binit_t *obd_init;
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struct ofw_pci_bdesc *obd_super;
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};
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u_int32_t ofw_pci_route_intr(phandle_t, u_int32_t);
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obr_callback_t ofw_pci_orb_callback;
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u_int8_t ofw_pci_alloc_busno(phandle_t);
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ofw_pci_binit_t ofw_pci_binit;
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void ofw_pci_init(device_t, phandle_t, u_int32_t, struct ofw_pci_bdesc *);
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phandle_t ofw_pci_find_node(int, int, int);
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phandle_t ofw_pci_node(device_t);
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#endif /* ! _SPARC64_PCI_OFW_PCI_H_ */
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