0e69f431d4
These are needed for some particular port configurations where the default speed isn't suitable for all link speed types. (Ie, changing 10/100/1000MBit PLL rate requires a similar MII clock rate, rather than a fixed MII rate.) This is: * only currently implemented for the ar71xx; * isn't used anywhere (yet), as the final interface for this hasn't yet been determined.
225 lines
5.1 KiB
C
225 lines
5.1 KiB
C
/*-
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* Copyright (c) 2010 Adrian Chadd
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include "opt_ddb.h"
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#include <sys/param.h>
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#include <sys/conf.h>
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#include <sys/kernel.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/cons.h>
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#include <sys/kdb.h>
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#include <sys/reboot.h>
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#include <vm/vm.h>
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#include <vm/vm_page.h>
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#include <net/ethernet.h>
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#include <machine/clock.h>
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#include <machine/cpu.h>
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#include <machine/cpuregs.h>
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#include <machine/hwfunc.h>
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#include <machine/md_var.h>
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#include <machine/trap.h>
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#include <machine/vmparam.h>
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#include <mips/atheros/ar71xxreg.h>
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#include <mips/atheros/ar71xx_cpudef.h>
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#include <mips/atheros/ar91xxreg.h>
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#include <mips/atheros/ar91xx_chip.h>
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#include <mips/sentry5/s5reg.h>
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static void
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ar91xx_chip_detect_mem_size(void)
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{
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}
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static void
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ar91xx_chip_detect_sys_frequency(void)
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{
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uint32_t pll;
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uint32_t freq;
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uint32_t div;
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pll = ATH_READ_REG(AR91XX_PLL_REG_CPU_CONFIG);
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div = ((pll >> AR91XX_PLL_DIV_SHIFT) & AR91XX_PLL_DIV_MASK);
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freq = div * AR91XX_BASE_FREQ;
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u_ar71xx_cpu_freq = freq;
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div = ((pll >> AR91XX_DDR_DIV_SHIFT) & AR91XX_DDR_DIV_MASK) + 1;
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u_ar71xx_ddr_freq = freq / div;
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div = (((pll >> AR91XX_AHB_DIV_SHIFT) & AR91XX_AHB_DIV_MASK) + 1) * 2;
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u_ar71xx_ahb_freq = u_ar71xx_cpu_freq / div;
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}
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static void
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ar91xx_chip_device_stop(uint32_t mask)
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{
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uint32_t reg;
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reg = ATH_READ_REG(AR91XX_RESET_REG_RESET_MODULE);
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ATH_WRITE_REG(AR91XX_RESET_REG_RESET_MODULE, reg | mask);
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}
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static void
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ar91xx_chip_device_start(uint32_t mask)
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{
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uint32_t reg;
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reg = ATH_READ_REG(AR91XX_RESET_REG_RESET_MODULE);
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ATH_WRITE_REG(AR91XX_RESET_REG_RESET_MODULE, reg & ~mask);
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}
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static int
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ar91xx_chip_device_stopped(uint32_t mask)
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{
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uint32_t reg;
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reg = ATH_READ_REG(AR91XX_RESET_REG_RESET_MODULE);
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return ((reg & mask) == mask);
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}
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static void
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ar91xx_chip_set_mii_speed(uint32_t unit, uint32_t speed)
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{
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/* XXX TODO */
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}
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static void
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ar91xx_chip_set_pll_ge(int unit, int speed)
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{
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uint32_t pll;
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switch(speed) {
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case 10:
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pll = AR91XX_PLL_VAL_10;
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break;
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case 100:
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pll = AR91XX_PLL_VAL_100;
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break;
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case 1000:
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pll = AR91XX_PLL_VAL_1000;
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break;
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default:
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printf("%s%d: invalid speed %d\n",
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__func__, unit, speed);
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return;
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}
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switch (unit) {
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case 0:
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ar71xx_write_pll(AR91XX_PLL_REG_ETH_CONFIG,
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AR91XX_PLL_REG_ETH0_INT_CLOCK, pll,
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AR91XX_ETH0_PLL_SHIFT);
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break;
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case 1:
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ar71xx_write_pll(AR91XX_PLL_REG_ETH_CONFIG,
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AR91XX_PLL_REG_ETH1_INT_CLOCK, pll,
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AR91XX_ETH1_PLL_SHIFT);
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break;
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default:
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printf("%s: invalid PLL set for arge unit: %d\n",
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__func__, unit);
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return;
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}
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}
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static void
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ar91xx_chip_ddr_flush_ge(int unit)
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{
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switch (unit) {
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case 0:
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ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_GE0);
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break;
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case 1:
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ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_GE1);
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break;
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default:
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printf("%s: invalid DDR flush for arge unit: %d\n",
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__func__, unit);
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return;
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}
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}
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static void
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ar91xx_chip_ddr_flush_ip2(void)
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{
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ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_WMAC);
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}
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static uint32_t
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ar91xx_chip_get_eth_pll(unsigned int mac, int speed)
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{
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return 0;
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}
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static void
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ar91xx_chip_init_usb_peripheral(void)
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{
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ar71xx_device_stop(AR91XX_RST_RESET_MODULE_USBSUS_OVERRIDE);
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DELAY(100);
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ar71xx_device_start(RST_RESET_USB_HOST);
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DELAY(100);
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ar71xx_device_start(RST_RESET_USB_PHY);
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DELAY(100);
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/* Wireless */
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ar71xx_device_stop(AR91XX_RST_RESET_MODULE_AMBA2WMAC);
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DELAY(1000);
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ar71xx_device_start(AR91XX_RST_RESET_MODULE_AMBA2WMAC);
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DELAY(1000);
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}
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struct ar71xx_cpu_def ar91xx_chip_def = {
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&ar91xx_chip_detect_mem_size,
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&ar91xx_chip_detect_sys_frequency,
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&ar91xx_chip_device_stop,
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&ar91xx_chip_device_start,
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&ar91xx_chip_device_stopped,
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&ar91xx_chip_set_pll_ge,
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&ar91xx_chip_set_mii_speed,
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&ar91xx_chip_ddr_flush_ge,
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&ar91xx_chip_get_eth_pll,
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&ar91xx_chip_ddr_flush_ip2,
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&ar91xx_chip_init_usb_peripheral,
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};
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