5351742ea2
1. Implement a large set of ioctl shims so that the Linux management apps from LSI will work. This includes infrastructure to support adding, deleting and rescanning arrays at runtime. This is based on work from Doug Ambrosko, heavily augmented by LSI and Yahoo. 2. Implement full 64-bit DMA support. Systems with more than 4GB of RAM can now operate without the cost of bounce buffers. Cards that cannot do 64-bit DMA will automatically revert to using bounce buffers. This option can be forced off by setting the 'hw.amr.force_sg32" tunable in the loader. It should only be turned off for debugging purposes. This work was sponsored by Yahoo. 3. Streamline the command delivery and interrupt handler paths after much discussion with Dell and LSI. The logic now closely matches the intended design, making it both more robust and much faster. Certain i/o failures under heavy load should be fixed with this. 4. Optimize the locking. In the interrupt handler, the card can be checked for completed commands without any locks held, due to the handler being implicitely serialized and there being no need to look at any shared data. Only grab the lock to return the command structure to the free pool. A small optimization can still be made to collect all of the completions together and then free them together under a single lock. Items 3 and 4 significantly increase the performance of the driver. On an LSI 320-2X card, transactions per second went from 13,000 to 31,000 in my testing with these changes. However, these changes are still fairly experimental and shouldn't be merged to 6.x until there is more testing. Thanks to Doug Ambrosko, LSI, Dell, and Yahoo for contributing towards this.
678 lines
20 KiB
C
678 lines
20 KiB
C
/*-
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* Copyright (c) 1999,2000 Michael Smith
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* Copyright (c) 2000 BSDi
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*-
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* Copyright (c) 2002 Eric Moore
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* Copyright (c) 2002, 2004 LSI Logic Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The party using or redistributing the source code and binary forms
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* agrees to the disclaimer below and the terms and conditions set forth
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* herein.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/sysctl.h>
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#include <sys/bio.h>
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#include <sys/bus.h>
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#include <sys/conf.h>
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#include <machine/bus.h>
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#include <machine/resource.h>
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#include <sys/rman.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcivar.h>
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#include <dev/amr/amrio.h>
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#include <dev/amr/amrreg.h>
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#include <dev/amr/amrvar.h>
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static int amr_pci_probe(device_t dev);
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static int amr_pci_attach(device_t dev);
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static int amr_pci_detach(device_t dev);
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static int amr_pci_shutdown(device_t dev);
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static int amr_pci_suspend(device_t dev);
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static int amr_pci_resume(device_t dev);
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static void amr_pci_intr(void *arg);
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static void amr_pci_free(struct amr_softc *sc);
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static void amr_sglist_map_helper(void *arg, bus_dma_segment_t *segs, int nseg, int error);
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static int amr_sglist_map(struct amr_softc *sc);
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static void amr_setup_mbox_helper(void *arg, bus_dma_segment_t *segs, int nseg, int error);
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static int amr_setup_mbox(struct amr_softc *sc);
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static u_int amr_force_sg32 = 0;
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TUNABLE_INT("hw.amr.force_sg32", &amr_force_sg32);
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SYSCTL_DECL(_hw_amr);
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SYSCTL_UINT(_hw_amr, OID_AUTO, force_sg32, CTLFLAG_RDTUN, &amr_force_sg32, 0,
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"Force the AMR driver to use 32bit scatter gather");
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static device_method_t amr_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, amr_pci_probe),
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DEVMETHOD(device_attach, amr_pci_attach),
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DEVMETHOD(device_detach, amr_pci_detach),
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DEVMETHOD(device_shutdown, amr_pci_shutdown),
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DEVMETHOD(device_suspend, amr_pci_suspend),
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DEVMETHOD(device_resume, amr_pci_resume),
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DEVMETHOD(bus_print_child, bus_generic_print_child),
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DEVMETHOD(bus_driver_added, bus_generic_driver_added),
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{ 0, 0 }
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};
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static driver_t amr_pci_driver = {
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"amr",
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amr_methods,
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sizeof(struct amr_softc)
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};
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static devclass_t amr_devclass;
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DRIVER_MODULE(amr, pci, amr_pci_driver, amr_devclass, 0, 0);
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static struct amr_ident
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{
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int vendor;
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int device;
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int flags;
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#define AMR_ID_PROBE_SIG (1<<0) /* generic i960RD, check signature */
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#define AMR_ID_DO_SG64 (1<<1)
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#define AMR_ID_QUARTZ (1<<2)
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} amr_device_ids[] = {
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{0x101e, 0x9010, 0},
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{0x101e, 0x9060, 0},
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{0x8086, 0x1960, AMR_ID_QUARTZ | AMR_ID_PROBE_SIG},
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{0x101e, 0x1960, AMR_ID_QUARTZ},
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{0x1000, 0x1960, AMR_ID_QUARTZ | AMR_ID_PROBE_SIG},
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{0x1000, 0x0407, AMR_ID_QUARTZ | AMR_ID_DO_SG64},
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{0x1000, 0x0408, AMR_ID_QUARTZ | AMR_ID_DO_SG64},
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{0x1000, 0x0409, AMR_ID_QUARTZ | AMR_ID_DO_SG64},
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{0x1028, 0x000e, AMR_ID_QUARTZ | AMR_ID_DO_SG64 | AMR_ID_PROBE_SIG}, /* perc4/di i960 */
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{0x1028, 0x000f, AMR_ID_QUARTZ | AMR_ID_DO_SG64}, /* perc4/di Verde*/
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{0x1028, 0x0013, AMR_ID_QUARTZ | AMR_ID_DO_SG64}, /* perc4/di */
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{0, 0, 0}
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};
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static struct amr_ident *
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amr_find_ident(device_t dev)
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{
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struct amr_ident *id;
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int sig;
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for (id = amr_device_ids; id->vendor != 0; id++) {
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if ((pci_get_vendor(dev) == id->vendor) &&
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(pci_get_device(dev) == id->device)) {
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/* do we need to test for a signature? */
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if (id->flags & AMR_ID_PROBE_SIG) {
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sig = pci_read_config(dev, AMR_CFG_SIG, 2);
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if ((sig != AMR_SIGNATURE_1) && (sig != AMR_SIGNATURE_2))
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continue;
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}
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return (id);
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}
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}
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return (NULL);
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}
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static int
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amr_pci_probe(device_t dev)
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{
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debug_called(1);
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if (amr_find_ident(dev) != NULL) {
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device_set_desc(dev, LSI_DESC_PCI);
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return(BUS_PROBE_DEFAULT);
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}
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return(ENXIO);
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}
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static int
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amr_pci_attach(device_t dev)
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{
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struct amr_softc *sc;
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struct amr_ident *id;
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int rid, rtype, error;
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u_int32_t command;
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debug_called(1);
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/*
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* Initialise softc.
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*/
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sc = device_get_softc(dev);
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bzero(sc, sizeof(*sc));
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sc->amr_dev = dev;
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/* assume failure is 'not configured' */
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error = ENXIO;
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/*
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* Determine board type.
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*/
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if ((id = amr_find_ident(dev)) == NULL)
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return (ENXIO);
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command = pci_read_config(dev, PCIR_COMMAND, 1);
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if (id->flags & AMR_ID_QUARTZ) {
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/*
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* Make sure we are going to be able to talk to this board.
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*/
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if ((command & PCIM_CMD_MEMEN) == 0) {
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device_printf(dev, "memory window not available\n");
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return (ENXIO);
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}
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sc->amr_type |= AMR_TYPE_QUARTZ;
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} else {
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/*
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* Make sure we are going to be able to talk to this board.
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*/
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if ((command & PCIM_CMD_PORTEN) == 0) {
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device_printf(dev, "I/O window not available\n");
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return (ENXIO);
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}
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}
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if ((amr_force_sg32 == 0) && (id->flags & AMR_ID_DO_SG64) &&
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(sizeof(vm_paddr_t) > 4)) {
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device_printf(dev, "Using 64-bit DMA\n");
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sc->amr_type |= AMR_TYPE_SG64;
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}
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/* force the busmaster enable bit on */
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if (!(command & PCIM_CMD_BUSMASTEREN)) {
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device_printf(dev, "busmaster bit not set, enabling\n");
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command |= PCIM_CMD_BUSMASTEREN;
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pci_write_config(dev, PCIR_COMMAND, command, 2);
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}
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/*
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* Allocate the PCI register window.
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*/
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rid = PCIR_BAR(0);
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rtype = AMR_IS_QUARTZ(sc) ? SYS_RES_MEMORY : SYS_RES_IOPORT;
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sc->amr_reg = bus_alloc_resource_any(dev, rtype, &rid, RF_ACTIVE);
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if (sc->amr_reg == NULL) {
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device_printf(sc->amr_dev, "can't allocate register window\n");
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goto out;
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}
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sc->amr_btag = rman_get_bustag(sc->amr_reg);
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sc->amr_bhandle = rman_get_bushandle(sc->amr_reg);
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/*
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* Allocate and connect our interrupt.
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*/
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rid = 0;
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sc->amr_irq = bus_alloc_resource_any(sc->amr_dev, SYS_RES_IRQ, &rid,
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RF_SHAREABLE | RF_ACTIVE);
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if (sc->amr_irq == NULL) {
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device_printf(sc->amr_dev, "can't allocate interrupt\n");
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goto out;
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}
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if (bus_setup_intr(sc->amr_dev, sc->amr_irq,
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INTR_TYPE_BIO | INTR_ENTROPY | INTR_MPSAFE, amr_pci_intr,
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sc, &sc->amr_intr)) {
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device_printf(sc->amr_dev, "can't set up interrupt\n");
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goto out;
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}
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debug(2, "interrupt attached");
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/* assume failure is 'out of memory' */
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error = ENOMEM;
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/*
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* Allocate the parent bus DMA tag appropriate for PCI.
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*/
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if (bus_dma_tag_create(NULL, /* parent */
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1, 0, /* alignment,boundary */
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AMR_IS_SG64(sc) ?
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BUS_SPACE_MAXADDR :
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BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
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BUS_SPACE_MAXADDR, /* highaddr */
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NULL, NULL, /* filter, filterarg */
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MAXBSIZE, AMR_NSEG, /* maxsize, nsegments */
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BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
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0, /* flags */
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NULL, NULL, /* lockfunc, lockarg */
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&sc->amr_parent_dmat)) {
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device_printf(dev, "can't allocate parent DMA tag\n");
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goto out;
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}
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/*
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* Create DMA tag for mapping buffers into controller-addressable space.
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*/
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if (bus_dma_tag_create(sc->amr_parent_dmat, /* parent */
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1, 0, /* alignment,boundary */
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BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
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BUS_SPACE_MAXADDR, /* highaddr */
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NULL, NULL, /* filter, filterarg */
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MAXBSIZE, AMR_NSEG, /* maxsize, nsegments */
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MAXBSIZE, /* maxsegsize */
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BUS_DMA_ALLOCNOW, /* flags */
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busdma_lock_mutex, /* lockfunc */
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&sc->amr_list_lock, /* lockarg */
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&sc->amr_buffer_dmat)) {
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device_printf(sc->amr_dev, "can't allocate buffer DMA tag\n");
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goto out;
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}
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if (bus_dma_tag_create(sc->amr_parent_dmat, /* parent */
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1, 0, /* alignment,boundary */
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BUS_SPACE_MAXADDR, /* lowaddr */
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BUS_SPACE_MAXADDR, /* highaddr */
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NULL, NULL, /* filter, filterarg */
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MAXBSIZE, AMR_NSEG, /* maxsize, nsegments */
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MAXBSIZE, /* maxsegsize */
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BUS_DMA_ALLOCNOW, /* flags */
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busdma_lock_mutex, /* lockfunc */
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&sc->amr_list_lock, /* lockarg */
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&sc->amr_buffer64_dmat)) {
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device_printf(sc->amr_dev, "can't allocate buffer DMA tag\n");
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goto out;
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}
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debug(2, "dma tag done");
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/*
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* Allocate and set up mailbox in a bus-visible fashion.
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*/
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mtx_init(&sc->amr_list_lock, "AMR List Lock", NULL, MTX_DEF);
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mtx_init(&sc->amr_hw_lock, "AMR HW Lock", NULL, MTX_DEF);
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if ((error = amr_setup_mbox(sc)) != 0)
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goto out;
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debug(2, "mailbox setup");
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/*
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* Build the scatter/gather buffers.
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*/
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if (amr_sglist_map(sc))
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goto out;
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debug(2, "s/g list mapped");
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/*
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* Do bus-independant initialisation, bring controller online.
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*/
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error = amr_attach(sc);
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out:
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if (error)
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amr_pci_free(sc);
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return(error);
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}
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/********************************************************************************
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* Disconnect from the controller completely, in preparation for unload.
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*/
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static int
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amr_pci_detach(device_t dev)
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{
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struct amr_softc *sc = device_get_softc(dev);
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int error;
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debug_called(1);
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if (sc->amr_state & AMR_STATE_OPEN)
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return(EBUSY);
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if ((error = amr_pci_shutdown(dev)))
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return(error);
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amr_pci_free(sc);
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return(0);
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}
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/********************************************************************************
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* Bring the controller down to a dormant state and detach all child devices.
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*
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* This function is called before detach, system shutdown, or before performing
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* an operation which may add or delete system disks. (Call amr_startup to
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* resume normal operation.)
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*
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* Note that we can assume that the bioq on the controller is empty, as we won't
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* allow shutdown if any device is open.
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*/
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static int
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amr_pci_shutdown(device_t dev)
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{
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struct amr_softc *sc = device_get_softc(dev);
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int i,error;
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debug_called(1);
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/* mark ourselves as in-shutdown */
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sc->amr_state |= AMR_STATE_SHUTDOWN;
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/* flush controller */
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device_printf(sc->amr_dev, "flushing cache...");
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printf("%s\n", amr_flush(sc) ? "failed" : "done");
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error = 0;
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/* delete all our child devices */
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for(i = 0 ; i < AMR_MAXLD; i++) {
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if( sc->amr_drive[i].al_disk != 0) {
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if((error = device_delete_child(sc->amr_dev,sc->amr_drive[i].al_disk)) != 0)
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goto shutdown_out;
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sc->amr_drive[i].al_disk = 0;
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}
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}
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/* XXX disable interrupts? */
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shutdown_out:
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return(error);
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}
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|
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/********************************************************************************
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* Bring the controller to a quiescent state, ready for system suspend.
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*/
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static int
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amr_pci_suspend(device_t dev)
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{
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struct amr_softc *sc = device_get_softc(dev);
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debug_called(1);
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sc->amr_state |= AMR_STATE_SUSPEND;
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/* flush controller */
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device_printf(sc->amr_dev, "flushing cache...");
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printf("%s\n", amr_flush(sc) ? "failed" : "done");
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/* XXX disable interrupts? */
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return(0);
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}
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|
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/********************************************************************************
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* Bring the controller back to a state ready for operation.
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*/
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static int
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amr_pci_resume(device_t dev)
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{
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struct amr_softc *sc = device_get_softc(dev);
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debug_called(1);
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sc->amr_state &= ~AMR_STATE_SUSPEND;
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/* XXX enable interrupts? */
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return(0);
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}
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/*******************************************************************************
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* Take an interrupt, or be poked by other code to look for interrupt-worthy
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* status.
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*/
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static void
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amr_pci_intr(void *arg)
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{
|
|
struct amr_softc *sc = (struct amr_softc *)arg;
|
|
|
|
debug_called(2);
|
|
|
|
/* collect finished commands, queue anything waiting */
|
|
amr_done(sc);
|
|
}
|
|
|
|
/********************************************************************************
|
|
* Free all of the resources associated with (sc)
|
|
*
|
|
* Should not be called if the controller is active.
|
|
*/
|
|
static void
|
|
amr_pci_free(struct amr_softc *sc)
|
|
{
|
|
u_int8_t *p
|
|
|
|
debug_called(1);
|
|
|
|
amr_free(sc);
|
|
|
|
/* destroy data-transfer DMA tag */
|
|
if (sc->amr_buffer_dmat)
|
|
bus_dma_tag_destroy(sc->amr_buffer_dmat);
|
|
if (sc->amr_buffer64_dmat)
|
|
bus_dma_tag_destroy(sc->amr_buffer64_dmat);
|
|
|
|
/* free and destroy DMA memory and tag for s/g lists */
|
|
if (sc->amr_sgtable)
|
|
bus_dmamem_free(sc->amr_sg_dmat, sc->amr_sgtable, sc->amr_sg_dmamap);
|
|
if (sc->amr_sg_dmat)
|
|
bus_dma_tag_destroy(sc->amr_sg_dmat);
|
|
|
|
/* free and destroy DMA memory and tag for mailbox */
|
|
/* XXX Brain damaged GCC Alert! */
|
|
p = (u_int8_t *)(uintptr_t)(volatile void *)sc->amr_mailbox64;
|
|
if (sc->amr_mailbox) {
|
|
bus_dmamem_free(sc->amr_mailbox_dmat, p, sc->amr_mailbox_dmamap);
|
|
}
|
|
if (sc->amr_mailbox_dmat)
|
|
bus_dma_tag_destroy(sc->amr_mailbox_dmat);
|
|
|
|
/* disconnect the interrupt handler */
|
|
if (sc->amr_intr)
|
|
bus_teardown_intr(sc->amr_dev, sc->amr_irq, sc->amr_intr);
|
|
if (sc->amr_irq != NULL)
|
|
bus_release_resource(sc->amr_dev, SYS_RES_IRQ, 0, sc->amr_irq);
|
|
|
|
/* destroy the parent DMA tag */
|
|
if (sc->amr_parent_dmat)
|
|
bus_dma_tag_destroy(sc->amr_parent_dmat);
|
|
|
|
/* release the register window mapping */
|
|
if (sc->amr_reg != NULL)
|
|
bus_release_resource(sc->amr_dev,
|
|
AMR_IS_QUARTZ(sc) ? SYS_RES_MEMORY : SYS_RES_IOPORT,
|
|
PCIR_BAR(0), sc->amr_reg);
|
|
}
|
|
|
|
/********************************************************************************
|
|
* Allocate and map the scatter/gather table in bus space.
|
|
*/
|
|
static void
|
|
amr_sglist_map_helper(void *arg, bus_dma_segment_t *segs, int nseg, int error)
|
|
{
|
|
struct amr_softc *sc = (struct amr_softc *)arg;
|
|
|
|
debug_called(1);
|
|
|
|
/* save base of s/g table's address in bus space */
|
|
sc->amr_sgbusaddr = segs->ds_addr;
|
|
}
|
|
|
|
static int
|
|
amr_sglist_map(struct amr_softc *sc)
|
|
{
|
|
size_t segsize;
|
|
u_int8_t *p;
|
|
int error;
|
|
|
|
debug_called(1);
|
|
|
|
/*
|
|
* Create a single tag describing a region large enough to hold all of
|
|
* the s/g lists we will need.
|
|
*
|
|
* Note that we could probably use AMR_LIMITCMD here, but that may become
|
|
* tunable.
|
|
*/
|
|
if (AMR_IS_SG64(sc))
|
|
segsize = sizeof(struct amr_sg64entry) * AMR_NSEG * AMR_MAXCMD;
|
|
else
|
|
segsize = sizeof(struct amr_sgentry) * AMR_NSEG * AMR_MAXCMD;
|
|
|
|
error = bus_dma_tag_create(sc->amr_parent_dmat, /* parent */
|
|
1, 0, /* alignment,boundary */
|
|
BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
|
|
BUS_SPACE_MAXADDR, /* highaddr */
|
|
NULL, NULL, /* filter, filterarg */
|
|
segsize, 1, /* maxsize, nsegments */
|
|
BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
|
|
0, /* flags */
|
|
NULL, NULL, /* lockfunc, lockarg */
|
|
&sc->amr_sg_dmat);
|
|
if (error != 0) {
|
|
device_printf(sc->amr_dev, "can't allocate scatter/gather DMA tag\n");
|
|
return(ENOMEM);
|
|
}
|
|
|
|
/*
|
|
* Allocate enough s/g maps for all commands and permanently map them into
|
|
* controller-visible space.
|
|
*
|
|
* XXX this assumes we can get enough space for all the s/g maps in one
|
|
* contiguous slab. We may need to switch to a more complex arrangement
|
|
* where we allocate in smaller chunks and keep a lookup table from slot
|
|
* to bus address.
|
|
*
|
|
* XXX HACK ALERT: at least some controllers don't like the s/g memory
|
|
* being allocated below 0x2000. We leak some memory if
|
|
* we get some below this mark and allocate again. We
|
|
* should be able to avoid this with the tag setup, but
|
|
* that does't seem to work.
|
|
*/
|
|
retry:
|
|
error = bus_dmamem_alloc(sc->amr_sg_dmat, (void **)&p, BUS_DMA_NOWAIT, &sc->amr_sg_dmamap);
|
|
if (error) {
|
|
device_printf(sc->amr_dev, "can't allocate s/g table\n");
|
|
return(ENOMEM);
|
|
}
|
|
bus_dmamap_load(sc->amr_sg_dmat, sc->amr_sg_dmamap, p, segsize, amr_sglist_map_helper, sc, 0);
|
|
if (sc->amr_sgbusaddr < 0x2000) {
|
|
debug(1, "s/g table too low (0x%x), reallocating\n", sc->amr_sgbusaddr);
|
|
goto retry;
|
|
}
|
|
|
|
if (AMR_IS_SG64(sc))
|
|
sc->amr_sg64table = (struct amr_sg64entry *)p;
|
|
sc->amr_sgtable = (struct amr_sgentry *)p;
|
|
|
|
return(0);
|
|
}
|
|
|
|
/********************************************************************************
|
|
* Allocate and set up mailbox areas for the controller (sc)
|
|
*
|
|
* The basic mailbox structure should be 16-byte aligned. This means that the
|
|
* mailbox64 structure has 4 bytes hanging off the bottom.
|
|
*/
|
|
static void
|
|
amr_setup_mbox_helper(void *arg, bus_dma_segment_t *segs, int nseg, int error)
|
|
{
|
|
struct amr_softc *sc = (struct amr_softc *)arg;
|
|
|
|
debug_called(1);
|
|
|
|
/* save phsyical base of the basic mailbox structure */
|
|
sc->amr_mailboxphys = segs->ds_addr + offsetof(struct amr_mailbox64, mb);
|
|
}
|
|
|
|
static int
|
|
amr_setup_mbox(struct amr_softc *sc)
|
|
{
|
|
int error;
|
|
u_int8_t *p;
|
|
|
|
debug_called(1);
|
|
|
|
/*
|
|
* Create a single tag describing a region large enough to hold the entire
|
|
* mailbox.
|
|
*/
|
|
error = bus_dma_tag_create(sc->amr_parent_dmat, /* parent */
|
|
16, 0, /* alignment,boundary */
|
|
BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
|
|
BUS_SPACE_MAXADDR, /* highaddr */
|
|
NULL, NULL, /* filter, filterarg */
|
|
sizeof(struct amr_mailbox64), /* maxsize */
|
|
1, /* nsegments */
|
|
BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
|
|
0, /* flags */
|
|
NULL, NULL, /* lockfunc, lockarg */
|
|
&sc->amr_mailbox_dmat);
|
|
if (error != 0) {
|
|
device_printf(sc->amr_dev, "can't allocate mailbox tag\n");
|
|
return(ENOMEM);
|
|
}
|
|
|
|
/*
|
|
* Allocate the mailbox structure and permanently map it into
|
|
* controller-visible space.
|
|
*/
|
|
error = bus_dmamem_alloc(sc->amr_mailbox_dmat, (void **)&p, BUS_DMA_NOWAIT,
|
|
&sc->amr_mailbox_dmamap);
|
|
if (error) {
|
|
device_printf(sc->amr_dev, "can't allocate mailbox memory\n");
|
|
return(ENOMEM);
|
|
}
|
|
bus_dmamap_load(sc->amr_mailbox_dmat, sc->amr_mailbox_dmamap, p,
|
|
sizeof(struct amr_mailbox64), amr_setup_mbox_helper, sc, 0);
|
|
/*
|
|
* Conventional mailbox is inside the mailbox64 region.
|
|
*/
|
|
bzero(p, sizeof(struct amr_mailbox64));
|
|
sc->amr_mailbox64 = (struct amr_mailbox64 *)p;
|
|
sc->amr_mailbox = &sc->amr_mailbox64->mb;
|
|
|
|
return(0);
|
|
}
|