0f34084f95
mmc(4). For the most part, this consists of support for:
- Switching the signal voltage (VCCQ) to 1.8 V or (if supported
by the host controller) to 1.2 V,
- setting the UHS mode as appropriate in the SDHCI_HOST_CONTROL2
register,
- setting the power class in the eMMC device according to the
core supply voltage (VCC),
- using different bits for enabling a bus width of 4 and 8 bits
in the the eMMC device at DDR or higher timings respectively,
- arbitrating timings faster than high speed if there actually
are additional devices on the same MMC bus.
Given that support for DDR52 is not denoted by SDHCI capability
registers, availability of that timing is indicated by a new
quirk SDHCI_QUIRK_MMC_DDR52 and only enabled for Intel SDHCI
controllers so far. Generally, what it takes for a sdhci(4)
front-end to enable support for DDR52 is to hook up the bridge
method mmcbr_switch_vccq (which especially for 1.2 V signaling
support is chip/board specific) and the sdhci_set_uhs_timing
sdhci(4) method.
As a side-effect, this change also fixes communication with
some eMMC devices at SDR high speed mode with 52 MHz due to
the signaling voltage and UHS bits in the SDHCI controller no
longer being left in an inappropriate state.
Compared to 52 MHz at SDR high speed which typically yields
~45 MB/s with the eMMC chips tested, throughput goes up to
~80 MB/s at DDR52.
Additionally, this change already adds infrastructure and quite
some code for modes up to HS400ES and SDR104 respectively (I did
not want to add to much stuff at a time, though). Essentially,
what is still missing in order to be able to activate support
for these latter is is support for and handling of (re-)tuning.
o In sdhci(4), add two tunables hw.sdhci.quirk_clear as well as
hw.sdhci.quirk_set, which (when hooked up in the front-end)
allow to set/clear sdhci(4) quirks for debugging and testing
purposes. However, especially for SDHCI controllers on the
PCI bus which have no specific support code so far and, thus,
are picked up as generic SDHCI controllers, hw.sdhci.quirk_set
allows for setting the necessary quirks (if required).
o In mmc(4), check and handle the return values of some more
function calls instead of assuming that everything went right.
In case failures actually are not problematic, indicate that
by casting the return value to void.
Reviewed by: jmcneill
189 lines
7.8 KiB
C
189 lines
7.8 KiB
C
/*-
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* Copyright (c) 2006 M. Warner Losh. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Portions of this software may have been developed with reference to
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* the SD Simplified Specification. The following disclaimer may apply:
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*
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* The following conditions apply to the release of the simplified
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* specification ("Simplified Specification") by the SD Card Association and
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* the SD Group. The Simplified Specification is a subset of the complete SD
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* Specification which is owned by the SD Card Association and the SD
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* Group. This Simplified Specification is provided on a non-confidential
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* basis subject to the disclaimers below. Any implementation of the
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* Simplified Specification may require a license from the SD Card
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* Association, SD Group, SD-3C LLC or other third parties.
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*
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* Disclaimers:
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*
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* The information contained in the Simplified Specification is presented only
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* as a standard specification for SD Cards and SD Host/Ancillary products and
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* is provided "AS-IS" without any representations or warranties of any
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* kind. No responsibility is assumed by the SD Group, SD-3C LLC or the SD
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* Card Association for any damages, any infringements of patents or other
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* right of the SD Group, SD-3C LLC, the SD Card Association or any third
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* parties, which may result from its use. No license is granted by
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* implication, estoppel or otherwise under any patent or other rights of the
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* SD Group, SD-3C LLC, the SD Card Association or any third party. Nothing
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* herein shall be construed as an obligation by the SD Group, the SD-3C LLC
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* or the SD Card Association to disclose or distribute any technical
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* information, know-how or other confidential information to any third party.
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*
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* $FreeBSD$
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*/
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#ifndef DEV_MMC_BRIDGE_H
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#define DEV_MMC_BRIDGE_H
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#include <sys/bus.h>
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/*
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* This file defines interfaces for the mmc bridge. The names chosen
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* are similar to or the same as the names used in Linux to allow for
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* easy porting of what Linux calls mmc host drivers. I use the
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* FreeBSD terminology of bridge and bus for consistency with other
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* drivers in the system. This file corresponds roughly to the Linux
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* linux/mmc/host.h file.
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*
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* A mmc bridge is a chipset that can have one or more mmc and/or sd
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* cards attached to it. mmc cards are attached on a bus topology,
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* while sd and sdio cards are attached using a star topology (meaning
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* in practice each sd card has its own, independent slot). Each
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* mmcbr is assumed to be derived from the mmcbr. This is done to
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* allow for easier addition of bridges (as each bridge does not need
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* to be added to the mmcbus file).
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*
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* Attached to the mmc bridge is an mmcbus. The mmcbus is described
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* in dev/mmc/mmcbus_if.m.
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*/
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/*
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* mmc_ios is a structure that is used to store the state of the mmc/sd
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* bus configuration. This include the bus' clock speed, its voltage,
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* the bus mode for command output, the SPI chip select, some power
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* states and the bus width.
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*/
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enum mmc_vdd {
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vdd_150 = 0, vdd_155, vdd_160, vdd_165, vdd_170, vdd_180,
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vdd_190, vdd_200, vdd_210, vdd_220, vdd_230, vdd_240, vdd_250,
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vdd_260, vdd_270, vdd_280, vdd_290, vdd_300, vdd_310, vdd_320,
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vdd_330, vdd_340, vdd_350, vdd_360
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};
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enum mmc_vccq {
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vccq_120 = 0, vccq_180, vccq_330
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};
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enum mmc_power_mode {
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power_off = 0, power_up, power_on
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};
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enum mmc_bus_mode {
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opendrain = 1, pushpull
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};
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enum mmc_chip_select {
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cs_dontcare = 0, cs_high, cs_low
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};
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enum mmc_bus_width {
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bus_width_1 = 0, bus_width_4 = 2, bus_width_8 = 3
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};
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enum mmc_drv_type {
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drv_type_b = 0, drv_type_a, drv_type_c, drv_type_d
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};
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enum mmc_bus_timing {
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bus_timing_normal = 0, bus_timing_hs, bus_timing_uhs_sdr12,
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bus_timing_uhs_sdr25, bus_timing_uhs_sdr50, bus_timing_uhs_ddr50,
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bus_timing_uhs_sdr104, bus_timing_mmc_ddr52, bus_timing_mmc_hs200,
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bus_timing_mmc_hs400, bus_timing_mmc_hs400es, bus_timing_max =
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bus_timing_mmc_hs400es
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};
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struct mmc_ios {
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uint32_t clock; /* Speed of the clock in Hz to move data */
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enum mmc_vdd vdd; /* Voltage to apply to the power pins */
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enum mmc_vccq vccq; /* Voltage to use for signaling */
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enum mmc_bus_mode bus_mode;
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enum mmc_chip_select chip_select;
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enum mmc_bus_width bus_width;
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enum mmc_power_mode power_mode;
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enum mmc_bus_timing timing;
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enum mmc_drv_type drv_type;
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};
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enum mmc_card_mode {
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mode_mmc, mode_sd
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};
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struct mmc_host {
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int f_min;
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int f_max;
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uint32_t host_ocr;
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uint32_t ocr;
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uint32_t caps;
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#define MMC_CAP_4_BIT_DATA (1 << 0) /* Can do 4-bit data transfers */
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#define MMC_CAP_8_BIT_DATA (1 << 1) /* Can do 8-bit data transfers */
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#define MMC_CAP_HSPEED (1 << 2) /* Can do High Speed transfers */
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#define MMC_CAP_BOOT_NOACC (1 << 4) /* Cannot access boot partitions */
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#define MMC_CAP_WAIT_WHILE_BUSY (1 << 5) /* Host waits for busy responses */
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#define MMC_CAP_UHS_SDR12 (1 << 6) /* Can do UHS SDR12 */
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#define MMC_CAP_UHS_SDR25 (1 << 7) /* Can do UHS SDR25 */
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#define MMC_CAP_UHS_SDR50 (1 << 8) /* Can do UHS SDR50 */
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#define MMC_CAP_UHS_SDR104 (1 << 9) /* Can do UHS SDR104 */
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#define MMC_CAP_UHS_DDR50 (1 << 10) /* Can do UHS DDR50 */
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#define MMC_CAP_MMC_DDR52_120 (1 << 11) /* Can do eMMC DDR52 at 1.2 V */
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#define MMC_CAP_MMC_DDR52_180 (1 << 12) /* Can do eMMC DDR52 at 1.8 V */
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#define MMC_CAP_MMC_DDR52 (MMC_CAP_MMC_DDR52_120 | MMC_CAP_MMC_DDR52_180)
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#define MMC_CAP_MMC_HS200_120 (1 << 13) /* Can do eMMC HS200 at 1.2 V */
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#define MMC_CAP_MMC_HS200_180 (1 << 14) /* Can do eMMC HS200 at 1.8 V */
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#define MMC_CAP_MMC_HS200 (MMC_CAP_MMC_HS200_120| MMC_CAP_MMC_HS200_180)
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#define MMC_CAP_MMC_HS400_120 (1 << 15) /* Can do eMMC HS400 at 1.2 V */
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#define MMC_CAP_MMC_HS400_180 (1 << 16) /* Can do eMMC HS400 at 1.8 V */
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#define MMC_CAP_MMC_HS400 (MMC_CAP_MMC_HS400_120 | MMC_CAP_MMC_HS400_180)
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#define MMC_CAP_MMC_HSX00_120 (MMC_CAP_MMC_HS200_120 | MMC_CAP_MMC_HS400_120)
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#define MMC_CAP_MMC_ENH_STROBE (1 << 17) /* Can do eMMC Enhanced Strobe */
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#define MMC_CAP_SIGNALING_120 (1 << 18) /* Can do signaling at 1.2 V */
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#define MMC_CAP_SIGNALING_180 (1 << 19) /* Can do signaling at 1.8 V */
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#define MMC_CAP_SIGNALING_330 (1 << 20) /* Can do signaling at 3.3 V */
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#define MMC_CAP_DRIVER_TYPE_A (1 << 21) /* Can do Driver Type A */
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#define MMC_CAP_DRIVER_TYPE_C (1 << 22) /* Can do Driver Type C */
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#define MMC_CAP_DRIVER_TYPE_D (1 << 23) /* Can do Driver Type D */
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enum mmc_card_mode mode;
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struct mmc_ios ios; /* Current state of the host */
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};
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extern driver_t mmc_driver;
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extern devclass_t mmc_devclass;
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#define MMC_VERSION 3
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#define MMC_DECLARE_BRIDGE(name) \
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DRIVER_MODULE(mmc, name, mmc_driver, mmc_devclass, NULL, NULL); \
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MODULE_DEPEND(name, mmc, MMC_VERSION, MMC_VERSION, MMC_VERSION);
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#define MMC_DEPEND(name) \
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MODULE_DEPEND(name, mmc, MMC_VERSION, MMC_VERSION, MMC_VERSION);
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#endif /* DEV_MMC_BRIDGE_H */
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