576 lines
15 KiB
C++
576 lines
15 KiB
C++
//===- SIMachineFunctionInfo.h - SIMachineFunctionInfo interface -*- C++ -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AMDGPU_SIMACHINEFUNCTIONINFO_H
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#define LLVM_LIB_TARGET_AMDGPU_SIMACHINEFUNCTIONINFO_H
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#include "AMDGPUMachineFunction.h"
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#include "SIRegisterInfo.h"
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#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
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#include "llvm/CodeGen/PseudoSourceValue.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/Support/ErrorHandling.h"
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#include <array>
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#include <cassert>
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#include <map>
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#include <utility>
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namespace llvm {
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class AMDGPUImagePseudoSourceValue : public PseudoSourceValue {
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public:
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explicit AMDGPUImagePseudoSourceValue() :
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PseudoSourceValue(PseudoSourceValue::TargetCustom) { }
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bool isConstant(const MachineFrameInfo *) const override {
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// This should probably be true for most images, but we will start by being
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// conservative.
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return false;
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}
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bool isAliased(const MachineFrameInfo *) const override {
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// FIXME: If we ever change image intrinsics to accept fat pointers, then
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// this could be true for some cases.
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return false;
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}
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bool mayAlias(const MachineFrameInfo*) const override {
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// FIXME: If we ever change image intrinsics to accept fat pointers, then
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// this could be true for some cases.
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return false;
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}
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};
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class AMDGPUBufferPseudoSourceValue : public PseudoSourceValue {
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public:
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explicit AMDGPUBufferPseudoSourceValue() :
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PseudoSourceValue(PseudoSourceValue::TargetCustom) { }
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bool isConstant(const MachineFrameInfo *) const override {
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// This should probably be true for most images, but we will start by being
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// conservative.
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return false;
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}
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bool isAliased(const MachineFrameInfo *) const override {
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// FIXME: If we ever change image intrinsics to accept fat pointers, then
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// this could be true for some cases.
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return false;
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}
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bool mayAlias(const MachineFrameInfo*) const override {
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// FIXME: If we ever change image intrinsics to accept fat pointers, then
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// this could be true for some cases.
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return false;
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}
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};
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/// This class keeps track of the SPI_SP_INPUT_ADDR config register, which
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/// tells the hardware which interpolation parameters to load.
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class SIMachineFunctionInfo final : public AMDGPUMachineFunction {
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// FIXME: This should be removed and getPreloadedValue moved here.
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friend class SIRegisterInfo;
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unsigned TIDReg;
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// Registers that may be reserved for spilling purposes. These may be the same
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// as the input registers.
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unsigned ScratchRSrcReg;
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unsigned ScratchWaveOffsetReg;
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// This is the current function's incremented size from the kernel's scratch
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// wave offset register. For an entry function, this is exactly the same as
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// the ScratchWaveOffsetReg.
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unsigned FrameOffsetReg;
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// Top of the stack SGPR offset derived from the ScratchWaveOffsetReg.
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unsigned StackPtrOffsetReg;
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// Input registers for non-HSA ABI
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unsigned PrivateMemoryPtrUserSGPR;
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// Input registers setup for the HSA ABI.
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// User SGPRs in allocation order.
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unsigned PrivateSegmentBufferUserSGPR;
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unsigned DispatchPtrUserSGPR;
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unsigned QueuePtrUserSGPR;
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unsigned KernargSegmentPtrUserSGPR;
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unsigned DispatchIDUserSGPR;
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unsigned FlatScratchInitUserSGPR;
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unsigned PrivateSegmentSizeUserSGPR;
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unsigned GridWorkGroupCountXUserSGPR;
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unsigned GridWorkGroupCountYUserSGPR;
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unsigned GridWorkGroupCountZUserSGPR;
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// System SGPRs in allocation order.
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unsigned WorkGroupIDXSystemSGPR;
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unsigned WorkGroupIDYSystemSGPR;
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unsigned WorkGroupIDZSystemSGPR;
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unsigned WorkGroupInfoSystemSGPR;
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unsigned PrivateSegmentWaveByteOffsetSystemSGPR;
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// Graphics info.
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unsigned PSInputAddr;
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unsigned PSInputEnable;
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bool ReturnsVoid;
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// A pair of default/requested minimum/maximum flat work group sizes.
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// Minimum - first, maximum - second.
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std::pair<unsigned, unsigned> FlatWorkGroupSizes;
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// A pair of default/requested minimum/maximum number of waves per execution
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// unit. Minimum - first, maximum - second.
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std::pair<unsigned, unsigned> WavesPerEU;
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// Stack object indices for work group IDs.
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std::array<int, 3> DebuggerWorkGroupIDStackObjectIndices;
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// Stack object indices for work item IDs.
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std::array<int, 3> DebuggerWorkItemIDStackObjectIndices;
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AMDGPUBufferPseudoSourceValue BufferPSV;
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AMDGPUImagePseudoSourceValue ImagePSV;
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private:
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unsigned LDSWaveSpillSize;
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unsigned ScratchOffsetReg;
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unsigned NumUserSGPRs;
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unsigned NumSystemSGPRs;
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bool HasSpilledSGPRs;
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bool HasSpilledVGPRs;
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bool HasNonSpillStackObjects;
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unsigned NumSpilledSGPRs;
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unsigned NumSpilledVGPRs;
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// Feature bits required for inputs passed in user SGPRs.
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bool PrivateSegmentBuffer : 1;
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bool DispatchPtr : 1;
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bool QueuePtr : 1;
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bool KernargSegmentPtr : 1;
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bool DispatchID : 1;
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bool FlatScratchInit : 1;
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bool GridWorkgroupCountX : 1;
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bool GridWorkgroupCountY : 1;
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bool GridWorkgroupCountZ : 1;
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// Feature bits required for inputs passed in system SGPRs.
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bool WorkGroupIDX : 1; // Always initialized.
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bool WorkGroupIDY : 1;
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bool WorkGroupIDZ : 1;
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bool WorkGroupInfo : 1;
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bool PrivateSegmentWaveByteOffset : 1;
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bool WorkItemIDX : 1; // Always initialized.
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bool WorkItemIDY : 1;
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bool WorkItemIDZ : 1;
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// Private memory buffer
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// Compute directly in sgpr[0:1]
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// Other shaders indirect 64-bits at sgpr[0:1]
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bool PrivateMemoryInputPtr : 1;
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MCPhysReg getNextUserSGPR() const {
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assert(NumSystemSGPRs == 0 && "System SGPRs must be added after user SGPRs");
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return AMDGPU::SGPR0 + NumUserSGPRs;
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}
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MCPhysReg getNextSystemSGPR() const {
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return AMDGPU::SGPR0 + NumUserSGPRs + NumSystemSGPRs;
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}
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public:
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struct SpilledReg {
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unsigned VGPR = AMDGPU::NoRegister;
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int Lane = -1;
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SpilledReg() = default;
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SpilledReg(unsigned R, int L) : VGPR (R), Lane (L) { }
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bool hasLane() { return Lane != -1;}
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bool hasReg() { return VGPR != AMDGPU::NoRegister;}
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};
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private:
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// SGPR->VGPR spilling support.
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typedef std::pair<unsigned, unsigned> SpillRegMask;
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// Track VGPR + wave index for each subregister of the SGPR spilled to
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// frameindex key.
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DenseMap<int, std::vector<SpilledReg>> SGPRToVGPRSpills;
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unsigned NumVGPRSpillLanes = 0;
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SmallVector<unsigned, 2> SpillVGPRs;
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public:
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SIMachineFunctionInfo(const MachineFunction &MF);
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ArrayRef<SpilledReg> getSGPRToVGPRSpills(int FrameIndex) const {
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auto I = SGPRToVGPRSpills.find(FrameIndex);
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return (I == SGPRToVGPRSpills.end()) ?
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ArrayRef<SpilledReg>() : makeArrayRef(I->second);
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}
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bool allocateSGPRSpillToVGPR(MachineFunction &MF, int FI);
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void removeSGPRToVGPRFrameIndices(MachineFrameInfo &MFI);
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bool hasCalculatedTID() const { return TIDReg != AMDGPU::NoRegister; };
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unsigned getTIDReg() const { return TIDReg; };
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void setTIDReg(unsigned Reg) { TIDReg = Reg; }
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// Add user SGPRs.
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unsigned addPrivateSegmentBuffer(const SIRegisterInfo &TRI);
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unsigned addDispatchPtr(const SIRegisterInfo &TRI);
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unsigned addQueuePtr(const SIRegisterInfo &TRI);
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unsigned addKernargSegmentPtr(const SIRegisterInfo &TRI);
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unsigned addDispatchID(const SIRegisterInfo &TRI);
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unsigned addFlatScratchInit(const SIRegisterInfo &TRI);
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unsigned addPrivateMemoryPtr(const SIRegisterInfo &TRI);
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// Add system SGPRs.
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unsigned addWorkGroupIDX() {
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WorkGroupIDXSystemSGPR = getNextSystemSGPR();
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NumSystemSGPRs += 1;
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return WorkGroupIDXSystemSGPR;
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}
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unsigned addWorkGroupIDY() {
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WorkGroupIDYSystemSGPR = getNextSystemSGPR();
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NumSystemSGPRs += 1;
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return WorkGroupIDYSystemSGPR;
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}
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unsigned addWorkGroupIDZ() {
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WorkGroupIDZSystemSGPR = getNextSystemSGPR();
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NumSystemSGPRs += 1;
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return WorkGroupIDZSystemSGPR;
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}
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unsigned addWorkGroupInfo() {
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WorkGroupInfoSystemSGPR = getNextSystemSGPR();
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NumSystemSGPRs += 1;
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return WorkGroupInfoSystemSGPR;
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}
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unsigned addPrivateSegmentWaveByteOffset() {
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PrivateSegmentWaveByteOffsetSystemSGPR = getNextSystemSGPR();
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NumSystemSGPRs += 1;
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return PrivateSegmentWaveByteOffsetSystemSGPR;
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}
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void setPrivateSegmentWaveByteOffset(unsigned Reg) {
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PrivateSegmentWaveByteOffsetSystemSGPR = Reg;
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}
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bool hasPrivateSegmentBuffer() const {
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return PrivateSegmentBuffer;
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}
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bool hasDispatchPtr() const {
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return DispatchPtr;
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}
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bool hasQueuePtr() const {
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return QueuePtr;
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}
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bool hasKernargSegmentPtr() const {
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return KernargSegmentPtr;
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}
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bool hasDispatchID() const {
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return DispatchID;
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}
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bool hasFlatScratchInit() const {
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return FlatScratchInit;
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}
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bool hasGridWorkgroupCountX() const {
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return GridWorkgroupCountX;
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}
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bool hasGridWorkgroupCountY() const {
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return GridWorkgroupCountY;
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}
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bool hasGridWorkgroupCountZ() const {
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return GridWorkgroupCountZ;
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}
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bool hasWorkGroupIDX() const {
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return WorkGroupIDX;
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}
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bool hasWorkGroupIDY() const {
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return WorkGroupIDY;
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}
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bool hasWorkGroupIDZ() const {
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return WorkGroupIDZ;
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}
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bool hasWorkGroupInfo() const {
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return WorkGroupInfo;
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}
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bool hasPrivateSegmentWaveByteOffset() const {
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return PrivateSegmentWaveByteOffset;
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}
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bool hasWorkItemIDX() const {
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return WorkItemIDX;
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}
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bool hasWorkItemIDY() const {
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return WorkItemIDY;
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}
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bool hasWorkItemIDZ() const {
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return WorkItemIDZ;
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}
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bool hasPrivateMemoryInputPtr() const {
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return PrivateMemoryInputPtr;
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}
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unsigned getNumUserSGPRs() const {
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return NumUserSGPRs;
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}
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unsigned getNumPreloadedSGPRs() const {
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return NumUserSGPRs + NumSystemSGPRs;
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}
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unsigned getPrivateSegmentWaveByteOffsetSystemSGPR() const {
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return PrivateSegmentWaveByteOffsetSystemSGPR;
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}
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/// \brief Returns the physical register reserved for use as the resource
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/// descriptor for scratch accesses.
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unsigned getScratchRSrcReg() const {
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return ScratchRSrcReg;
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}
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void setScratchRSrcReg(unsigned Reg) {
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assert(Reg != AMDGPU::NoRegister && "Should never be unset");
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ScratchRSrcReg = Reg;
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}
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unsigned getScratchWaveOffsetReg() const {
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return ScratchWaveOffsetReg;
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}
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unsigned getFrameOffsetReg() const {
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return FrameOffsetReg;
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}
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void setStackPtrOffsetReg(unsigned Reg) {
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assert(Reg != AMDGPU::NoRegister && "Should never be unset");
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StackPtrOffsetReg = Reg;
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}
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unsigned getStackPtrOffsetReg() const {
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return StackPtrOffsetReg;
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}
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void setScratchWaveOffsetReg(unsigned Reg) {
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assert(Reg != AMDGPU::NoRegister && "Should never be unset");
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ScratchWaveOffsetReg = Reg;
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// FIXME: Only for entry functions.
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FrameOffsetReg = ScratchWaveOffsetReg;
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}
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unsigned getQueuePtrUserSGPR() const {
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return QueuePtrUserSGPR;
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}
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unsigned getPrivateMemoryPtrUserSGPR() const {
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return PrivateMemoryPtrUserSGPR;
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}
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bool hasSpilledSGPRs() const {
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return HasSpilledSGPRs;
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}
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void setHasSpilledSGPRs(bool Spill = true) {
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HasSpilledSGPRs = Spill;
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}
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bool hasSpilledVGPRs() const {
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return HasSpilledVGPRs;
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}
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void setHasSpilledVGPRs(bool Spill = true) {
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HasSpilledVGPRs = Spill;
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}
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bool hasNonSpillStackObjects() const {
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return HasNonSpillStackObjects;
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}
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void setHasNonSpillStackObjects(bool StackObject = true) {
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HasNonSpillStackObjects = StackObject;
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}
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unsigned getNumSpilledSGPRs() const {
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return NumSpilledSGPRs;
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}
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unsigned getNumSpilledVGPRs() const {
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return NumSpilledVGPRs;
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}
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void addToSpilledSGPRs(unsigned num) {
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NumSpilledSGPRs += num;
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}
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void addToSpilledVGPRs(unsigned num) {
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NumSpilledVGPRs += num;
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}
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unsigned getPSInputAddr() const {
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return PSInputAddr;
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}
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unsigned getPSInputEnable() const {
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return PSInputEnable;
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}
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bool isPSInputAllocated(unsigned Index) const {
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return PSInputAddr & (1 << Index);
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}
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void markPSInputAllocated(unsigned Index) {
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PSInputAddr |= 1 << Index;
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}
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void markPSInputEnabled(unsigned Index) {
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PSInputEnable |= 1 << Index;
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}
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bool returnsVoid() const {
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return ReturnsVoid;
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}
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void setIfReturnsVoid(bool Value) {
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ReturnsVoid = Value;
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}
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/// \returns A pair of default/requested minimum/maximum flat work group sizes
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/// for this function.
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std::pair<unsigned, unsigned> getFlatWorkGroupSizes() const {
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return FlatWorkGroupSizes;
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}
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/// \returns Default/requested minimum flat work group size for this function.
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unsigned getMinFlatWorkGroupSize() const {
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return FlatWorkGroupSizes.first;
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}
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/// \returns Default/requested maximum flat work group size for this function.
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unsigned getMaxFlatWorkGroupSize() const {
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return FlatWorkGroupSizes.second;
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}
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/// \returns A pair of default/requested minimum/maximum number of waves per
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/// execution unit.
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std::pair<unsigned, unsigned> getWavesPerEU() const {
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return WavesPerEU;
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}
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/// \returns Default/requested minimum number of waves per execution unit.
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unsigned getMinWavesPerEU() const {
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return WavesPerEU.first;
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}
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/// \returns Default/requested maximum number of waves per execution unit.
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unsigned getMaxWavesPerEU() const {
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return WavesPerEU.second;
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}
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/// \returns Stack object index for \p Dim's work group ID.
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int getDebuggerWorkGroupIDStackObjectIndex(unsigned Dim) const {
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assert(Dim < 3);
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return DebuggerWorkGroupIDStackObjectIndices[Dim];
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}
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/// \brief Sets stack object index for \p Dim's work group ID to \p ObjectIdx.
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void setDebuggerWorkGroupIDStackObjectIndex(unsigned Dim, int ObjectIdx) {
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assert(Dim < 3);
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DebuggerWorkGroupIDStackObjectIndices[Dim] = ObjectIdx;
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}
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/// \returns Stack object index for \p Dim's work item ID.
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int getDebuggerWorkItemIDStackObjectIndex(unsigned Dim) const {
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assert(Dim < 3);
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return DebuggerWorkItemIDStackObjectIndices[Dim];
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}
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/// \brief Sets stack object index for \p Dim's work item ID to \p ObjectIdx.
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void setDebuggerWorkItemIDStackObjectIndex(unsigned Dim, int ObjectIdx) {
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assert(Dim < 3);
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DebuggerWorkItemIDStackObjectIndices[Dim] = ObjectIdx;
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}
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/// \returns SGPR used for \p Dim's work group ID.
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unsigned getWorkGroupIDSGPR(unsigned Dim) const {
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switch (Dim) {
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case 0:
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assert(hasWorkGroupIDX());
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return WorkGroupIDXSystemSGPR;
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case 1:
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assert(hasWorkGroupIDY());
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return WorkGroupIDYSystemSGPR;
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case 2:
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assert(hasWorkGroupIDZ());
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return WorkGroupIDZSystemSGPR;
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}
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llvm_unreachable("unexpected dimension");
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}
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/// \returns VGPR used for \p Dim' work item ID.
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unsigned getWorkItemIDVGPR(unsigned Dim) const {
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switch (Dim) {
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case 0:
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assert(hasWorkItemIDX());
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return AMDGPU::VGPR0;
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case 1:
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assert(hasWorkItemIDY());
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return AMDGPU::VGPR1;
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case 2:
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assert(hasWorkItemIDZ());
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return AMDGPU::VGPR2;
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}
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llvm_unreachable("unexpected dimension");
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}
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unsigned getLDSWaveSpillSize() const {
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return LDSWaveSpillSize;
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}
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const AMDGPUBufferPseudoSourceValue *getBufferPSV() const {
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return &BufferPSV;
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}
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const AMDGPUImagePseudoSourceValue *getImagePSV() const {
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return &ImagePSV;
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}
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};
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} // end namespace llvm
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#endif // LLVM_LIB_TARGET_AMDGPU_SIMACHINEFUNCTIONINFO_H
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