770 lines
29 KiB
C++
770 lines
29 KiB
C++
//===-- MipsSEInstrInfo.cpp - Mips32/64 Instruction Information -----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Mips32/64 implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "MipsSEInstrInfo.h"
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#include "InstPrinter/MipsInstPrinter.h"
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#include "MipsAnalyzeImmediate.h"
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#include "MipsMachineFunction.h"
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#include "MipsTargetMachine.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/MathExtras.h"
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#include "llvm/Support/TargetRegistry.h"
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using namespace llvm;
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MipsSEInstrInfo::MipsSEInstrInfo(const MipsSubtarget &STI)
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: MipsInstrInfo(STI, STI.isPositionIndependent() ? Mips::B : Mips::J),
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RI() {}
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const MipsRegisterInfo &MipsSEInstrInfo::getRegisterInfo() const {
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return RI;
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}
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/// isLoadFromStackSlot - If the specified machine instruction is a direct
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/// load from a stack slot, return the virtual or physical register number of
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/// the destination along with the FrameIndex of the loaded stack slot. If
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/// not, return 0. This predicate must return 0 if the instruction has
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/// any side effects other than loading from the stack slot.
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unsigned MipsSEInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
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int &FrameIndex) const {
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unsigned Opc = MI.getOpcode();
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if ((Opc == Mips::LW) || (Opc == Mips::LD) ||
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(Opc == Mips::LWC1) || (Opc == Mips::LDC1) || (Opc == Mips::LDC164)) {
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if ((MI.getOperand(1).isFI()) && // is a stack slot
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(MI.getOperand(2).isImm()) && // the imm is zero
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(isZeroImm(MI.getOperand(2)))) {
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FrameIndex = MI.getOperand(1).getIndex();
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return MI.getOperand(0).getReg();
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}
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}
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return 0;
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}
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/// isStoreToStackSlot - If the specified machine instruction is a direct
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/// store to a stack slot, return the virtual or physical register number of
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/// the source reg along with the FrameIndex of the loaded stack slot. If
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/// not, return 0. This predicate must return 0 if the instruction has
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/// any side effects other than storing to the stack slot.
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unsigned MipsSEInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
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int &FrameIndex) const {
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unsigned Opc = MI.getOpcode();
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if ((Opc == Mips::SW) || (Opc == Mips::SD) ||
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(Opc == Mips::SWC1) || (Opc == Mips::SDC1) || (Opc == Mips::SDC164)) {
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if ((MI.getOperand(1).isFI()) && // is a stack slot
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(MI.getOperand(2).isImm()) && // the imm is zero
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(isZeroImm(MI.getOperand(2)))) {
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FrameIndex = MI.getOperand(1).getIndex();
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return MI.getOperand(0).getReg();
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}
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}
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return 0;
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}
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void MipsSEInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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const DebugLoc &DL, unsigned DestReg,
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unsigned SrcReg, bool KillSrc) const {
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unsigned Opc = 0, ZeroReg = 0;
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bool isMicroMips = Subtarget.inMicroMipsMode();
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if (Mips::GPR32RegClass.contains(DestReg)) { // Copy to CPU Reg.
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if (Mips::GPR32RegClass.contains(SrcReg)) {
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if (isMicroMips)
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Opc = Mips::MOVE16_MM;
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else
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Opc = Mips::OR, ZeroReg = Mips::ZERO;
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} else if (Mips::CCRRegClass.contains(SrcReg))
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Opc = Mips::CFC1;
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else if (Mips::FGR32RegClass.contains(SrcReg))
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Opc = Mips::MFC1;
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else if (Mips::HI32RegClass.contains(SrcReg)) {
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Opc = isMicroMips ? Mips::MFHI16_MM : Mips::MFHI;
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SrcReg = 0;
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} else if (Mips::LO32RegClass.contains(SrcReg)) {
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Opc = isMicroMips ? Mips::MFLO16_MM : Mips::MFLO;
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SrcReg = 0;
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} else if (Mips::HI32DSPRegClass.contains(SrcReg))
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Opc = Mips::MFHI_DSP;
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else if (Mips::LO32DSPRegClass.contains(SrcReg))
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Opc = Mips::MFLO_DSP;
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else if (Mips::DSPCCRegClass.contains(SrcReg)) {
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BuildMI(MBB, I, DL, get(Mips::RDDSP), DestReg).addImm(1 << 4)
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.addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc));
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return;
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}
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else if (Mips::MSACtrlRegClass.contains(SrcReg))
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Opc = Mips::CFCMSA;
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}
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else if (Mips::GPR32RegClass.contains(SrcReg)) { // Copy from CPU Reg.
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if (Mips::CCRRegClass.contains(DestReg))
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Opc = Mips::CTC1;
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else if (Mips::FGR32RegClass.contains(DestReg))
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Opc = Mips::MTC1;
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else if (Mips::HI32RegClass.contains(DestReg))
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Opc = Mips::MTHI, DestReg = 0;
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else if (Mips::LO32RegClass.contains(DestReg))
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Opc = Mips::MTLO, DestReg = 0;
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else if (Mips::HI32DSPRegClass.contains(DestReg))
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Opc = Mips::MTHI_DSP;
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else if (Mips::LO32DSPRegClass.contains(DestReg))
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Opc = Mips::MTLO_DSP;
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else if (Mips::DSPCCRegClass.contains(DestReg)) {
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BuildMI(MBB, I, DL, get(Mips::WRDSP))
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.addReg(SrcReg, getKillRegState(KillSrc)).addImm(1 << 4)
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.addReg(DestReg, RegState::ImplicitDefine);
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return;
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} else if (Mips::MSACtrlRegClass.contains(DestReg)) {
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BuildMI(MBB, I, DL, get(Mips::CTCMSA))
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.addReg(DestReg)
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.addReg(SrcReg, getKillRegState(KillSrc));
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return;
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}
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}
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else if (Mips::FGR32RegClass.contains(DestReg, SrcReg))
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Opc = Mips::FMOV_S;
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else if (Mips::AFGR64RegClass.contains(DestReg, SrcReg))
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Opc = Mips::FMOV_D32;
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else if (Mips::FGR64RegClass.contains(DestReg, SrcReg))
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Opc = Mips::FMOV_D64;
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else if (Mips::GPR64RegClass.contains(DestReg)) { // Copy to CPU64 Reg.
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if (Mips::GPR64RegClass.contains(SrcReg))
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Opc = Mips::OR64, ZeroReg = Mips::ZERO_64;
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else if (Mips::HI64RegClass.contains(SrcReg))
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Opc = Mips::MFHI64, SrcReg = 0;
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else if (Mips::LO64RegClass.contains(SrcReg))
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Opc = Mips::MFLO64, SrcReg = 0;
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else if (Mips::FGR64RegClass.contains(SrcReg))
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Opc = Mips::DMFC1;
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}
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else if (Mips::GPR64RegClass.contains(SrcReg)) { // Copy from CPU64 Reg.
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if (Mips::HI64RegClass.contains(DestReg))
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Opc = Mips::MTHI64, DestReg = 0;
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else if (Mips::LO64RegClass.contains(DestReg))
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Opc = Mips::MTLO64, DestReg = 0;
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else if (Mips::FGR64RegClass.contains(DestReg))
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Opc = Mips::DMTC1;
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}
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else if (Mips::MSA128BRegClass.contains(DestReg)) { // Copy to MSA reg
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if (Mips::MSA128BRegClass.contains(SrcReg))
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Opc = Mips::MOVE_V;
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}
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assert(Opc && "Cannot copy registers");
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MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
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if (DestReg)
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MIB.addReg(DestReg, RegState::Define);
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if (SrcReg)
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MIB.addReg(SrcReg, getKillRegState(KillSrc));
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if (ZeroReg)
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MIB.addReg(ZeroReg);
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}
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void MipsSEInstrInfo::
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storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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unsigned SrcReg, bool isKill, int FI,
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const TargetRegisterClass *RC, const TargetRegisterInfo *TRI,
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int64_t Offset) const {
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DebugLoc DL;
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MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOStore);
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unsigned Opc = 0;
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if (Mips::GPR32RegClass.hasSubClassEq(RC))
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Opc = Mips::SW;
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else if (Mips::GPR64RegClass.hasSubClassEq(RC))
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Opc = Mips::SD;
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else if (Mips::ACC64RegClass.hasSubClassEq(RC))
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Opc = Mips::STORE_ACC64;
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else if (Mips::ACC64DSPRegClass.hasSubClassEq(RC))
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Opc = Mips::STORE_ACC64DSP;
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else if (Mips::ACC128RegClass.hasSubClassEq(RC))
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Opc = Mips::STORE_ACC128;
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else if (Mips::DSPCCRegClass.hasSubClassEq(RC))
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Opc = Mips::STORE_CCOND_DSP;
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else if (Mips::FGR32RegClass.hasSubClassEq(RC))
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Opc = Mips::SWC1;
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else if (Mips::AFGR64RegClass.hasSubClassEq(RC))
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Opc = Mips::SDC1;
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else if (Mips::FGR64RegClass.hasSubClassEq(RC))
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Opc = Mips::SDC164;
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else if (TRI->isTypeLegalForClass(*RC, MVT::v16i8))
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Opc = Mips::ST_B;
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else if (TRI->isTypeLegalForClass(*RC, MVT::v8i16) ||
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TRI->isTypeLegalForClass(*RC, MVT::v8f16))
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Opc = Mips::ST_H;
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else if (TRI->isTypeLegalForClass(*RC, MVT::v4i32) ||
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TRI->isTypeLegalForClass(*RC, MVT::v4f32))
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Opc = Mips::ST_W;
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else if (TRI->isTypeLegalForClass(*RC, MVT::v2i64) ||
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TRI->isTypeLegalForClass(*RC, MVT::v2f64))
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Opc = Mips::ST_D;
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else if (Mips::LO32RegClass.hasSubClassEq(RC))
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Opc = Mips::SW;
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else if (Mips::LO64RegClass.hasSubClassEq(RC))
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Opc = Mips::SD;
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else if (Mips::HI32RegClass.hasSubClassEq(RC))
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Opc = Mips::SW;
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else if (Mips::HI64RegClass.hasSubClassEq(RC))
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Opc = Mips::SD;
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// Hi, Lo are normally caller save but they are callee save
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// for interrupt handling.
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const Function *Func = MBB.getParent()->getFunction();
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if (Func->hasFnAttribute("interrupt")) {
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if (Mips::HI32RegClass.hasSubClassEq(RC)) {
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BuildMI(MBB, I, DL, get(Mips::MFHI), Mips::K0);
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SrcReg = Mips::K0;
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} else if (Mips::HI64RegClass.hasSubClassEq(RC)) {
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BuildMI(MBB, I, DL, get(Mips::MFHI64), Mips::K0_64);
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SrcReg = Mips::K0_64;
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} else if (Mips::LO32RegClass.hasSubClassEq(RC)) {
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BuildMI(MBB, I, DL, get(Mips::MFLO), Mips::K0);
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SrcReg = Mips::K0;
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} else if (Mips::LO64RegClass.hasSubClassEq(RC)) {
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BuildMI(MBB, I, DL, get(Mips::MFLO64), Mips::K0_64);
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SrcReg = Mips::K0_64;
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}
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}
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assert(Opc && "Register class not handled!");
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BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill))
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.addFrameIndex(FI).addImm(Offset).addMemOperand(MMO);
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}
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void MipsSEInstrInfo::
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loadRegFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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unsigned DestReg, int FI, const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI, int64_t Offset) const {
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DebugLoc DL;
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if (I != MBB.end()) DL = I->getDebugLoc();
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MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOLoad);
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unsigned Opc = 0;
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const Function *Func = MBB.getParent()->getFunction();
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bool ReqIndirectLoad = Func->hasFnAttribute("interrupt") &&
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(DestReg == Mips::LO0 || DestReg == Mips::LO0_64 ||
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DestReg == Mips::HI0 || DestReg == Mips::HI0_64);
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if (Mips::GPR32RegClass.hasSubClassEq(RC))
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Opc = Mips::LW;
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else if (Mips::GPR64RegClass.hasSubClassEq(RC))
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Opc = Mips::LD;
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else if (Mips::ACC64RegClass.hasSubClassEq(RC))
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Opc = Mips::LOAD_ACC64;
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else if (Mips::ACC64DSPRegClass.hasSubClassEq(RC))
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Opc = Mips::LOAD_ACC64DSP;
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else if (Mips::ACC128RegClass.hasSubClassEq(RC))
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Opc = Mips::LOAD_ACC128;
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else if (Mips::DSPCCRegClass.hasSubClassEq(RC))
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Opc = Mips::LOAD_CCOND_DSP;
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else if (Mips::FGR32RegClass.hasSubClassEq(RC))
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Opc = Mips::LWC1;
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else if (Mips::AFGR64RegClass.hasSubClassEq(RC))
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Opc = Mips::LDC1;
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else if (Mips::FGR64RegClass.hasSubClassEq(RC))
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Opc = Mips::LDC164;
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else if (TRI->isTypeLegalForClass(*RC, MVT::v16i8))
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Opc = Mips::LD_B;
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else if (TRI->isTypeLegalForClass(*RC, MVT::v8i16) ||
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TRI->isTypeLegalForClass(*RC, MVT::v8f16))
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Opc = Mips::LD_H;
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else if (TRI->isTypeLegalForClass(*RC, MVT::v4i32) ||
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TRI->isTypeLegalForClass(*RC, MVT::v4f32))
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Opc = Mips::LD_W;
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else if (TRI->isTypeLegalForClass(*RC, MVT::v2i64) ||
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TRI->isTypeLegalForClass(*RC, MVT::v2f64))
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Opc = Mips::LD_D;
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else if (Mips::HI32RegClass.hasSubClassEq(RC))
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Opc = Mips::LW;
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else if (Mips::HI64RegClass.hasSubClassEq(RC))
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Opc = Mips::LD;
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else if (Mips::LO32RegClass.hasSubClassEq(RC))
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Opc = Mips::LW;
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else if (Mips::LO64RegClass.hasSubClassEq(RC))
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Opc = Mips::LD;
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assert(Opc && "Register class not handled!");
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if (!ReqIndirectLoad)
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BuildMI(MBB, I, DL, get(Opc), DestReg)
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.addFrameIndex(FI)
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.addImm(Offset)
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.addMemOperand(MMO);
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else {
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// Load HI/LO through K0. Notably the DestReg is encoded into the
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// instruction itself.
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unsigned Reg = Mips::K0;
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unsigned LdOp = Mips::MTLO;
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if (DestReg == Mips::HI0)
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LdOp = Mips::MTHI;
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if (Subtarget.getABI().ArePtrs64bit()) {
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Reg = Mips::K0_64;
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if (DestReg == Mips::HI0_64)
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LdOp = Mips::MTHI64;
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else
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LdOp = Mips::MTLO64;
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}
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BuildMI(MBB, I, DL, get(Opc), Reg)
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.addFrameIndex(FI)
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.addImm(Offset)
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.addMemOperand(MMO);
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BuildMI(MBB, I, DL, get(LdOp)).addReg(Reg);
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}
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}
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bool MipsSEInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
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MachineBasicBlock &MBB = *MI.getParent();
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bool isMicroMips = Subtarget.inMicroMipsMode();
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unsigned Opc;
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switch (MI.getDesc().getOpcode()) {
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default:
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return false;
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case Mips::RetRA:
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expandRetRA(MBB, MI);
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break;
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case Mips::ERet:
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expandERet(MBB, MI);
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break;
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case Mips::PseudoMFHI:
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Opc = isMicroMips ? Mips::MFHI16_MM : Mips::MFHI;
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expandPseudoMFHiLo(MBB, MI, Opc);
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break;
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case Mips::PseudoMFLO:
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Opc = isMicroMips ? Mips::MFLO16_MM : Mips::MFLO;
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expandPseudoMFHiLo(MBB, MI, Opc);
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break;
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case Mips::PseudoMFHI64:
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expandPseudoMFHiLo(MBB, MI, Mips::MFHI64);
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break;
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case Mips::PseudoMFLO64:
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expandPseudoMFHiLo(MBB, MI, Mips::MFLO64);
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break;
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case Mips::PseudoMTLOHI:
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expandPseudoMTLoHi(MBB, MI, Mips::MTLO, Mips::MTHI, false);
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break;
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case Mips::PseudoMTLOHI64:
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expandPseudoMTLoHi(MBB, MI, Mips::MTLO64, Mips::MTHI64, false);
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break;
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case Mips::PseudoMTLOHI_DSP:
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expandPseudoMTLoHi(MBB, MI, Mips::MTLO_DSP, Mips::MTHI_DSP, true);
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break;
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case Mips::PseudoCVT_S_W:
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expandCvtFPInt(MBB, MI, Mips::CVT_S_W, Mips::MTC1, false);
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break;
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case Mips::PseudoCVT_D32_W:
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expandCvtFPInt(MBB, MI, Mips::CVT_D32_W, Mips::MTC1, false);
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break;
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case Mips::PseudoCVT_S_L:
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expandCvtFPInt(MBB, MI, Mips::CVT_S_L, Mips::DMTC1, true);
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break;
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case Mips::PseudoCVT_D64_W:
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expandCvtFPInt(MBB, MI, Mips::CVT_D64_W, Mips::MTC1, true);
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break;
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case Mips::PseudoCVT_D64_L:
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expandCvtFPInt(MBB, MI, Mips::CVT_D64_L, Mips::DMTC1, true);
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break;
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case Mips::BuildPairF64:
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expandBuildPairF64(MBB, MI, false);
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break;
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case Mips::BuildPairF64_64:
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expandBuildPairF64(MBB, MI, true);
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break;
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case Mips::ExtractElementF64:
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expandExtractElementF64(MBB, MI, false);
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break;
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case Mips::ExtractElementF64_64:
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expandExtractElementF64(MBB, MI, true);
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break;
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case Mips::MIPSeh_return32:
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case Mips::MIPSeh_return64:
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expandEhReturn(MBB, MI);
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break;
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}
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MBB.erase(MI);
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return true;
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}
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/// getOppositeBranchOpc - Return the inverse of the specified
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/// opcode, e.g. turning BEQ to BNE.
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unsigned MipsSEInstrInfo::getOppositeBranchOpc(unsigned Opc) const {
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switch (Opc) {
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default: llvm_unreachable("Illegal opcode!");
|
|
case Mips::BEQ: return Mips::BNE;
|
|
case Mips::BEQ_MM: return Mips::BNE_MM;
|
|
case Mips::BNE: return Mips::BEQ;
|
|
case Mips::BNE_MM: return Mips::BEQ_MM;
|
|
case Mips::BGTZ: return Mips::BLEZ;
|
|
case Mips::BGEZ: return Mips::BLTZ;
|
|
case Mips::BLTZ: return Mips::BGEZ;
|
|
case Mips::BLEZ: return Mips::BGTZ;
|
|
case Mips::BEQ64: return Mips::BNE64;
|
|
case Mips::BNE64: return Mips::BEQ64;
|
|
case Mips::BGTZ64: return Mips::BLEZ64;
|
|
case Mips::BGEZ64: return Mips::BLTZ64;
|
|
case Mips::BLTZ64: return Mips::BGEZ64;
|
|
case Mips::BLEZ64: return Mips::BGTZ64;
|
|
case Mips::BC1T: return Mips::BC1F;
|
|
case Mips::BC1F: return Mips::BC1T;
|
|
case Mips::BEQZC_MM: return Mips::BNEZC_MM;
|
|
case Mips::BNEZC_MM: return Mips::BEQZC_MM;
|
|
case Mips::BEQZC: return Mips::BNEZC;
|
|
case Mips::BNEZC: return Mips::BEQZC;
|
|
case Mips::BEQC: return Mips::BNEC;
|
|
case Mips::BNEC: return Mips::BEQC;
|
|
case Mips::BGTZC: return Mips::BLEZC;
|
|
case Mips::BGEZC: return Mips::BLTZC;
|
|
case Mips::BLTZC: return Mips::BGEZC;
|
|
case Mips::BLEZC: return Mips::BGTZC;
|
|
case Mips::BEQZC64: return Mips::BNEZC64;
|
|
case Mips::BNEZC64: return Mips::BEQZC64;
|
|
case Mips::BEQC64: return Mips::BNEC64;
|
|
case Mips::BNEC64: return Mips::BEQC64;
|
|
case Mips::BGEC64: return Mips::BLTC64;
|
|
case Mips::BGEUC64: return Mips::BLTUC64;
|
|
case Mips::BLTC64: return Mips::BGEC64;
|
|
case Mips::BLTUC64: return Mips::BGEUC64;
|
|
case Mips::BGTZC64: return Mips::BLEZC64;
|
|
case Mips::BGEZC64: return Mips::BLTZC64;
|
|
case Mips::BLTZC64: return Mips::BGEZC64;
|
|
case Mips::BLEZC64: return Mips::BGTZC64;
|
|
}
|
|
}
|
|
|
|
/// Adjust SP by Amount bytes.
|
|
void MipsSEInstrInfo::adjustStackPtr(unsigned SP, int64_t Amount,
|
|
MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator I) const {
|
|
MipsABIInfo ABI = Subtarget.getABI();
|
|
DebugLoc DL;
|
|
unsigned ADDiu = ABI.GetPtrAddiuOp();
|
|
|
|
if (Amount == 0)
|
|
return;
|
|
|
|
if (isInt<16>(Amount)) {
|
|
// addi sp, sp, amount
|
|
BuildMI(MBB, I, DL, get(ADDiu), SP).addReg(SP).addImm(Amount);
|
|
} else {
|
|
// For numbers which are not 16bit integers we synthesize Amount inline
|
|
// then add or subtract it from sp.
|
|
unsigned Opc = ABI.GetPtrAdduOp();
|
|
if (Amount < 0) {
|
|
Opc = ABI.GetPtrSubuOp();
|
|
Amount = -Amount;
|
|
}
|
|
unsigned Reg = loadImmediate(Amount, MBB, I, DL, nullptr);
|
|
BuildMI(MBB, I, DL, get(Opc), SP).addReg(SP).addReg(Reg, RegState::Kill);
|
|
}
|
|
}
|
|
|
|
/// This function generates the sequence of instructions needed to get the
|
|
/// result of adding register REG and immediate IMM.
|
|
unsigned MipsSEInstrInfo::loadImmediate(int64_t Imm, MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator II,
|
|
const DebugLoc &DL,
|
|
unsigned *NewImm) const {
|
|
MipsAnalyzeImmediate AnalyzeImm;
|
|
const MipsSubtarget &STI = Subtarget;
|
|
MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
|
|
unsigned Size = STI.isABI_N64() ? 64 : 32;
|
|
unsigned LUi = STI.isABI_N64() ? Mips::LUi64 : Mips::LUi;
|
|
unsigned ZEROReg = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO;
|
|
const TargetRegisterClass *RC = STI.isABI_N64() ?
|
|
&Mips::GPR64RegClass : &Mips::GPR32RegClass;
|
|
bool LastInstrIsADDiu = NewImm;
|
|
|
|
const MipsAnalyzeImmediate::InstSeq &Seq =
|
|
AnalyzeImm.Analyze(Imm, Size, LastInstrIsADDiu);
|
|
MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin();
|
|
|
|
assert(Seq.size() && (!LastInstrIsADDiu || (Seq.size() > 1)));
|
|
|
|
// The first instruction can be a LUi, which is different from other
|
|
// instructions (ADDiu, ORI and SLL) in that it does not have a register
|
|
// operand.
|
|
unsigned Reg = RegInfo.createVirtualRegister(RC);
|
|
|
|
if (Inst->Opc == LUi)
|
|
BuildMI(MBB, II, DL, get(LUi), Reg).addImm(SignExtend64<16>(Inst->ImmOpnd));
|
|
else
|
|
BuildMI(MBB, II, DL, get(Inst->Opc), Reg).addReg(ZEROReg)
|
|
.addImm(SignExtend64<16>(Inst->ImmOpnd));
|
|
|
|
// Build the remaining instructions in Seq.
|
|
for (++Inst; Inst != Seq.end() - LastInstrIsADDiu; ++Inst)
|
|
BuildMI(MBB, II, DL, get(Inst->Opc), Reg).addReg(Reg, RegState::Kill)
|
|
.addImm(SignExtend64<16>(Inst->ImmOpnd));
|
|
|
|
if (LastInstrIsADDiu)
|
|
*NewImm = Inst->ImmOpnd;
|
|
|
|
return Reg;
|
|
}
|
|
|
|
unsigned MipsSEInstrInfo::getAnalyzableBrOpc(unsigned Opc) const {
|
|
return (Opc == Mips::BEQ || Opc == Mips::BEQ_MM || Opc == Mips::BNE ||
|
|
Opc == Mips::BNE_MM || Opc == Mips::BGTZ || Opc == Mips::BGEZ ||
|
|
Opc == Mips::BLTZ || Opc == Mips::BLEZ || Opc == Mips::BEQ64 ||
|
|
Opc == Mips::BNE64 || Opc == Mips::BGTZ64 || Opc == Mips::BGEZ64 ||
|
|
Opc == Mips::BLTZ64 || Opc == Mips::BLEZ64 || Opc == Mips::BC1T ||
|
|
Opc == Mips::BC1F || Opc == Mips::B || Opc == Mips::J ||
|
|
Opc == Mips::BEQZC_MM || Opc == Mips::BNEZC_MM || Opc == Mips::BEQC ||
|
|
Opc == Mips::BNEC || Opc == Mips::BLTC || Opc == Mips::BGEC ||
|
|
Opc == Mips::BLTUC || Opc == Mips::BGEUC || Opc == Mips::BGTZC ||
|
|
Opc == Mips::BLEZC || Opc == Mips::BGEZC || Opc == Mips::BLTZC ||
|
|
Opc == Mips::BEQZC || Opc == Mips::BNEZC || Opc == Mips::BEQZC64 ||
|
|
Opc == Mips::BNEZC64 || Opc == Mips::BEQC64 || Opc == Mips::BNEC64 ||
|
|
Opc == Mips::BGEC64 || Opc == Mips::BGEUC64 || Opc == Mips::BLTC64 ||
|
|
Opc == Mips::BLTUC64 || Opc == Mips::BGTZC64 ||
|
|
Opc == Mips::BGEZC64 || Opc == Mips::BLTZC64 ||
|
|
Opc == Mips::BLEZC64 || Opc == Mips::BC) ? Opc : 0;
|
|
}
|
|
|
|
void MipsSEInstrInfo::expandRetRA(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator I) const {
|
|
|
|
MachineInstrBuilder MIB;
|
|
if (Subtarget.isGP64bit())
|
|
MIB = BuildMI(MBB, I, I->getDebugLoc(), get(Mips::PseudoReturn64))
|
|
.addReg(Mips::RA_64, RegState::Undef);
|
|
else
|
|
MIB = BuildMI(MBB, I, I->getDebugLoc(), get(Mips::PseudoReturn))
|
|
.addReg(Mips::RA, RegState::Undef);
|
|
|
|
// Retain any imp-use flags.
|
|
for (auto & MO : I->operands()) {
|
|
if (MO.isImplicit())
|
|
MIB.add(MO);
|
|
}
|
|
}
|
|
|
|
void MipsSEInstrInfo::expandERet(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator I) const {
|
|
BuildMI(MBB, I, I->getDebugLoc(), get(Mips::ERET));
|
|
}
|
|
|
|
std::pair<bool, bool>
|
|
MipsSEInstrInfo::compareOpndSize(unsigned Opc,
|
|
const MachineFunction &MF) const {
|
|
const MCInstrDesc &Desc = get(Opc);
|
|
assert(Desc.NumOperands == 2 && "Unary instruction expected.");
|
|
const MipsRegisterInfo *RI = &getRegisterInfo();
|
|
unsigned DstRegSize = RI->getRegSizeInBits(*getRegClass(Desc, 0, RI, MF));
|
|
unsigned SrcRegSize = RI->getRegSizeInBits(*getRegClass(Desc, 1, RI, MF));
|
|
|
|
return std::make_pair(DstRegSize > SrcRegSize, DstRegSize < SrcRegSize);
|
|
}
|
|
|
|
void MipsSEInstrInfo::expandPseudoMFHiLo(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator I,
|
|
unsigned NewOpc) const {
|
|
BuildMI(MBB, I, I->getDebugLoc(), get(NewOpc), I->getOperand(0).getReg());
|
|
}
|
|
|
|
void MipsSEInstrInfo::expandPseudoMTLoHi(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator I,
|
|
unsigned LoOpc,
|
|
unsigned HiOpc,
|
|
bool HasExplicitDef) const {
|
|
// Expand
|
|
// lo_hi pseudomtlohi $gpr0, $gpr1
|
|
// to these two instructions:
|
|
// mtlo $gpr0
|
|
// mthi $gpr1
|
|
|
|
DebugLoc DL = I->getDebugLoc();
|
|
const MachineOperand &SrcLo = I->getOperand(1), &SrcHi = I->getOperand(2);
|
|
MachineInstrBuilder LoInst = BuildMI(MBB, I, DL, get(LoOpc));
|
|
MachineInstrBuilder HiInst = BuildMI(MBB, I, DL, get(HiOpc));
|
|
|
|
// Add lo/hi registers if the mtlo/hi instructions created have explicit
|
|
// def registers.
|
|
if (HasExplicitDef) {
|
|
unsigned DstReg = I->getOperand(0).getReg();
|
|
unsigned DstLo = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo);
|
|
unsigned DstHi = getRegisterInfo().getSubReg(DstReg, Mips::sub_hi);
|
|
LoInst.addReg(DstLo, RegState::Define);
|
|
HiInst.addReg(DstHi, RegState::Define);
|
|
}
|
|
|
|
LoInst.addReg(SrcLo.getReg(), getKillRegState(SrcLo.isKill()));
|
|
HiInst.addReg(SrcHi.getReg(), getKillRegState(SrcHi.isKill()));
|
|
}
|
|
|
|
void MipsSEInstrInfo::expandCvtFPInt(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator I,
|
|
unsigned CvtOpc, unsigned MovOpc,
|
|
bool IsI64) const {
|
|
const MCInstrDesc &CvtDesc = get(CvtOpc), &MovDesc = get(MovOpc);
|
|
const MachineOperand &Dst = I->getOperand(0), &Src = I->getOperand(1);
|
|
unsigned DstReg = Dst.getReg(), SrcReg = Src.getReg(), TmpReg = DstReg;
|
|
unsigned KillSrc = getKillRegState(Src.isKill());
|
|
DebugLoc DL = I->getDebugLoc();
|
|
bool DstIsLarger, SrcIsLarger;
|
|
|
|
std::tie(DstIsLarger, SrcIsLarger) =
|
|
compareOpndSize(CvtOpc, *MBB.getParent());
|
|
|
|
if (DstIsLarger)
|
|
TmpReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo);
|
|
|
|
if (SrcIsLarger)
|
|
DstReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo);
|
|
|
|
BuildMI(MBB, I, DL, MovDesc, TmpReg).addReg(SrcReg, KillSrc);
|
|
BuildMI(MBB, I, DL, CvtDesc, DstReg).addReg(TmpReg, RegState::Kill);
|
|
}
|
|
|
|
void MipsSEInstrInfo::expandExtractElementF64(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator I,
|
|
bool FP64) const {
|
|
unsigned DstReg = I->getOperand(0).getReg();
|
|
unsigned SrcReg = I->getOperand(1).getReg();
|
|
unsigned N = I->getOperand(2).getImm();
|
|
DebugLoc dl = I->getDebugLoc();
|
|
|
|
assert(N < 2 && "Invalid immediate");
|
|
unsigned SubIdx = N ? Mips::sub_hi : Mips::sub_lo;
|
|
unsigned SubReg = getRegisterInfo().getSubReg(SrcReg, SubIdx);
|
|
|
|
// FPXX on MIPS-II or MIPS32r1 should have been handled with a spill/reload
|
|
// in MipsSEFrameLowering.cpp.
|
|
assert(!(Subtarget.isABI_FPXX() && !Subtarget.hasMips32r2()));
|
|
|
|
// FP64A (FP64 with nooddspreg) should have been handled with a spill/reload
|
|
// in MipsSEFrameLowering.cpp.
|
|
assert(!(Subtarget.isFP64bit() && !Subtarget.useOddSPReg()));
|
|
|
|
if (SubIdx == Mips::sub_hi && Subtarget.hasMTHC1()) {
|
|
// FIXME: Strictly speaking MFHC1 only reads the top 32-bits however, we
|
|
// claim to read the whole 64-bits as part of a white lie used to
|
|
// temporarily work around a widespread bug in the -mfp64 support.
|
|
// The problem is that none of the 32-bit fpu ops mention the fact
|
|
// that they clobber the upper 32-bits of the 64-bit FPR. Fixing that
|
|
// requires a major overhaul of the FPU implementation which can't
|
|
// be done right now due to time constraints.
|
|
// MFHC1 is one of two instructions that are affected since they are
|
|
// the only instructions that don't read the lower 32-bits.
|
|
// We therefore pretend that it reads the bottom 32-bits to
|
|
// artificially create a dependency and prevent the scheduler
|
|
// changing the behaviour of the code.
|
|
BuildMI(MBB, I, dl, get(FP64 ? Mips::MFHC1_D64 : Mips::MFHC1_D32), DstReg)
|
|
.addReg(SrcReg);
|
|
} else
|
|
BuildMI(MBB, I, dl, get(Mips::MFC1), DstReg).addReg(SubReg);
|
|
}
|
|
|
|
void MipsSEInstrInfo::expandBuildPairF64(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator I,
|
|
bool FP64) const {
|
|
unsigned DstReg = I->getOperand(0).getReg();
|
|
unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg();
|
|
const MCInstrDesc& Mtc1Tdd = get(Mips::MTC1);
|
|
DebugLoc dl = I->getDebugLoc();
|
|
const TargetRegisterInfo &TRI = getRegisterInfo();
|
|
|
|
// When mthc1 is available, use:
|
|
// mtc1 Lo, $fp
|
|
// mthc1 Hi, $fp
|
|
//
|
|
// Otherwise, for O32 FPXX ABI:
|
|
// spill + reload via ldc1
|
|
// This case is handled by the frame lowering code.
|
|
//
|
|
// Otherwise, for FP32:
|
|
// mtc1 Lo, $fp
|
|
// mtc1 Hi, $fp + 1
|
|
//
|
|
// The case where dmtc1 is available doesn't need to be handled here
|
|
// because it never creates a BuildPairF64 node.
|
|
|
|
// FPXX on MIPS-II or MIPS32r1 should have been handled with a spill/reload
|
|
// in MipsSEFrameLowering.cpp.
|
|
assert(!(Subtarget.isABI_FPXX() && !Subtarget.hasMips32r2()));
|
|
|
|
// FP64A (FP64 with nooddspreg) should have been handled with a spill/reload
|
|
// in MipsSEFrameLowering.cpp.
|
|
assert(!(Subtarget.isFP64bit() && !Subtarget.useOddSPReg()));
|
|
|
|
BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_lo))
|
|
.addReg(LoReg);
|
|
|
|
if (Subtarget.hasMTHC1()) {
|
|
// FIXME: The .addReg(DstReg) is a white lie used to temporarily work
|
|
// around a widespread bug in the -mfp64 support.
|
|
// The problem is that none of the 32-bit fpu ops mention the fact
|
|
// that they clobber the upper 32-bits of the 64-bit FPR. Fixing that
|
|
// requires a major overhaul of the FPU implementation which can't
|
|
// be done right now due to time constraints.
|
|
// MTHC1 is one of two instructions that are affected since they are
|
|
// the only instructions that don't read the lower 32-bits.
|
|
// We therefore pretend that it reads the bottom 32-bits to
|
|
// artificially create a dependency and prevent the scheduler
|
|
// changing the behaviour of the code.
|
|
BuildMI(MBB, I, dl, get(FP64 ? Mips::MTHC1_D64 : Mips::MTHC1_D32), DstReg)
|
|
.addReg(DstReg)
|
|
.addReg(HiReg);
|
|
} else if (Subtarget.isABI_FPXX())
|
|
llvm_unreachable("BuildPairF64 not expanded in frame lowering code!");
|
|
else
|
|
BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_hi))
|
|
.addReg(HiReg);
|
|
}
|
|
|
|
void MipsSEInstrInfo::expandEhReturn(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator I) const {
|
|
// This pseudo instruction is generated as part of the lowering of
|
|
// ISD::EH_RETURN. We convert it to a stack increment by OffsetReg, and
|
|
// indirect jump to TargetReg
|
|
MipsABIInfo ABI = Subtarget.getABI();
|
|
unsigned ADDU = ABI.GetPtrAdduOp();
|
|
unsigned SP = Subtarget.isGP64bit() ? Mips::SP_64 : Mips::SP;
|
|
unsigned RA = Subtarget.isGP64bit() ? Mips::RA_64 : Mips::RA;
|
|
unsigned T9 = Subtarget.isGP64bit() ? Mips::T9_64 : Mips::T9;
|
|
unsigned ZERO = Subtarget.isGP64bit() ? Mips::ZERO_64 : Mips::ZERO;
|
|
unsigned OffsetReg = I->getOperand(0).getReg();
|
|
unsigned TargetReg = I->getOperand(1).getReg();
|
|
|
|
// addu $ra, $v0, $zero
|
|
// addu $sp, $sp, $v1
|
|
// jr $ra (via RetRA)
|
|
const TargetMachine &TM = MBB.getParent()->getTarget();
|
|
if (TM.isPositionIndependent())
|
|
BuildMI(MBB, I, I->getDebugLoc(), get(ADDU), T9)
|
|
.addReg(TargetReg)
|
|
.addReg(ZERO);
|
|
BuildMI(MBB, I, I->getDebugLoc(), get(ADDU), RA)
|
|
.addReg(TargetReg)
|
|
.addReg(ZERO);
|
|
BuildMI(MBB, I, I->getDebugLoc(), get(ADDU), SP).addReg(SP).addReg(OffsetReg);
|
|
expandRetRA(MBB, I);
|
|
}
|
|
|
|
const MipsInstrInfo *llvm::createMipsSEInstrInfo(const MipsSubtarget &STI) {
|
|
return new MipsSEInstrInfo(STI);
|
|
}
|