857 lines
30 KiB
C++
857 lines
30 KiB
C++
//===-- SystemZTargetTransformInfo.cpp - SystemZ-specific TTI -------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements a TargetTransformInfo analysis pass specific to the
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// SystemZ target machine. It uses the target's detailed information to provide
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// more precise answers to certain TTI queries, while letting the target
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// independent and default TTI implementations handle the rest.
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//
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//===----------------------------------------------------------------------===//
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#include "SystemZTargetTransformInfo.h"
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#include "llvm/Analysis/TargetTransformInfo.h"
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#include "llvm/CodeGen/BasicTTIImpl.h"
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#include "llvm/IR/IntrinsicInst.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Target/CostTable.h"
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#include "llvm/Target/TargetLowering.h"
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using namespace llvm;
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#define DEBUG_TYPE "systemztti"
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//===----------------------------------------------------------------------===//
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//
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// SystemZ cost model.
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//
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//===----------------------------------------------------------------------===//
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int SystemZTTIImpl::getIntImmCost(const APInt &Imm, Type *Ty) {
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assert(Ty->isIntegerTy());
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unsigned BitSize = Ty->getPrimitiveSizeInBits();
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// There is no cost model for constants with a bit size of 0. Return TCC_Free
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// here, so that constant hoisting will ignore this constant.
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if (BitSize == 0)
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return TTI::TCC_Free;
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// No cost model for operations on integers larger than 64 bit implemented yet.
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if (BitSize > 64)
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return TTI::TCC_Free;
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if (Imm == 0)
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return TTI::TCC_Free;
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if (Imm.getBitWidth() <= 64) {
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// Constants loaded via lgfi.
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if (isInt<32>(Imm.getSExtValue()))
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return TTI::TCC_Basic;
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// Constants loaded via llilf.
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if (isUInt<32>(Imm.getZExtValue()))
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return TTI::TCC_Basic;
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// Constants loaded via llihf:
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if ((Imm.getZExtValue() & 0xffffffff) == 0)
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return TTI::TCC_Basic;
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return 2 * TTI::TCC_Basic;
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}
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return 4 * TTI::TCC_Basic;
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}
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int SystemZTTIImpl::getIntImmCost(unsigned Opcode, unsigned Idx,
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const APInt &Imm, Type *Ty) {
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assert(Ty->isIntegerTy());
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unsigned BitSize = Ty->getPrimitiveSizeInBits();
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// There is no cost model for constants with a bit size of 0. Return TCC_Free
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// here, so that constant hoisting will ignore this constant.
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if (BitSize == 0)
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return TTI::TCC_Free;
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// No cost model for operations on integers larger than 64 bit implemented yet.
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if (BitSize > 64)
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return TTI::TCC_Free;
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switch (Opcode) {
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default:
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return TTI::TCC_Free;
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case Instruction::GetElementPtr:
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// Always hoist the base address of a GetElementPtr. This prevents the
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// creation of new constants for every base constant that gets constant
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// folded with the offset.
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if (Idx == 0)
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return 2 * TTI::TCC_Basic;
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return TTI::TCC_Free;
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case Instruction::Store:
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if (Idx == 0 && Imm.getBitWidth() <= 64) {
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// Any 8-bit immediate store can by implemented via mvi.
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if (BitSize == 8)
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return TTI::TCC_Free;
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// 16-bit immediate values can be stored via mvhhi/mvhi/mvghi.
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if (isInt<16>(Imm.getSExtValue()))
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return TTI::TCC_Free;
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}
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break;
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case Instruction::ICmp:
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if (Idx == 1 && Imm.getBitWidth() <= 64) {
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// Comparisons against signed 32-bit immediates implemented via cgfi.
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if (isInt<32>(Imm.getSExtValue()))
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return TTI::TCC_Free;
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// Comparisons against unsigned 32-bit immediates implemented via clgfi.
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if (isUInt<32>(Imm.getZExtValue()))
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return TTI::TCC_Free;
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}
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break;
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case Instruction::Add:
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case Instruction::Sub:
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if (Idx == 1 && Imm.getBitWidth() <= 64) {
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// We use algfi/slgfi to add/subtract 32-bit unsigned immediates.
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if (isUInt<32>(Imm.getZExtValue()))
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return TTI::TCC_Free;
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// Or their negation, by swapping addition vs. subtraction.
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if (isUInt<32>(-Imm.getSExtValue()))
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return TTI::TCC_Free;
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}
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break;
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case Instruction::Mul:
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if (Idx == 1 && Imm.getBitWidth() <= 64) {
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// We use msgfi to multiply by 32-bit signed immediates.
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if (isInt<32>(Imm.getSExtValue()))
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return TTI::TCC_Free;
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}
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break;
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case Instruction::Or:
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case Instruction::Xor:
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if (Idx == 1 && Imm.getBitWidth() <= 64) {
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// Masks supported by oilf/xilf.
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if (isUInt<32>(Imm.getZExtValue()))
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return TTI::TCC_Free;
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// Masks supported by oihf/xihf.
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if ((Imm.getZExtValue() & 0xffffffff) == 0)
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return TTI::TCC_Free;
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}
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break;
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case Instruction::And:
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if (Idx == 1 && Imm.getBitWidth() <= 64) {
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// Any 32-bit AND operation can by implemented via nilf.
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if (BitSize <= 32)
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return TTI::TCC_Free;
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// 64-bit masks supported by nilf.
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if (isUInt<32>(~Imm.getZExtValue()))
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return TTI::TCC_Free;
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// 64-bit masks supported by nilh.
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if ((Imm.getZExtValue() & 0xffffffff) == 0xffffffff)
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return TTI::TCC_Free;
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// Some 64-bit AND operations can be implemented via risbg.
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const SystemZInstrInfo *TII = ST->getInstrInfo();
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unsigned Start, End;
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if (TII->isRxSBGMask(Imm.getZExtValue(), BitSize, Start, End))
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return TTI::TCC_Free;
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}
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break;
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case Instruction::Shl:
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case Instruction::LShr:
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case Instruction::AShr:
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// Always return TCC_Free for the shift value of a shift instruction.
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if (Idx == 1)
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return TTI::TCC_Free;
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break;
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case Instruction::UDiv:
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case Instruction::SDiv:
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case Instruction::URem:
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case Instruction::SRem:
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case Instruction::Trunc:
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case Instruction::ZExt:
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case Instruction::SExt:
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case Instruction::IntToPtr:
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case Instruction::PtrToInt:
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case Instruction::BitCast:
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case Instruction::PHI:
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case Instruction::Call:
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case Instruction::Select:
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case Instruction::Ret:
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case Instruction::Load:
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break;
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}
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return SystemZTTIImpl::getIntImmCost(Imm, Ty);
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}
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int SystemZTTIImpl::getIntImmCost(Intrinsic::ID IID, unsigned Idx,
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const APInt &Imm, Type *Ty) {
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assert(Ty->isIntegerTy());
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unsigned BitSize = Ty->getPrimitiveSizeInBits();
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// There is no cost model for constants with a bit size of 0. Return TCC_Free
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// here, so that constant hoisting will ignore this constant.
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if (BitSize == 0)
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return TTI::TCC_Free;
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// No cost model for operations on integers larger than 64 bit implemented yet.
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if (BitSize > 64)
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return TTI::TCC_Free;
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switch (IID) {
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default:
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return TTI::TCC_Free;
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case Intrinsic::sadd_with_overflow:
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case Intrinsic::uadd_with_overflow:
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case Intrinsic::ssub_with_overflow:
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case Intrinsic::usub_with_overflow:
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// These get expanded to include a normal addition/subtraction.
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if (Idx == 1 && Imm.getBitWidth() <= 64) {
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if (isUInt<32>(Imm.getZExtValue()))
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return TTI::TCC_Free;
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if (isUInt<32>(-Imm.getSExtValue()))
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return TTI::TCC_Free;
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}
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break;
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case Intrinsic::smul_with_overflow:
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case Intrinsic::umul_with_overflow:
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// These get expanded to include a normal multiplication.
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if (Idx == 1 && Imm.getBitWidth() <= 64) {
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if (isInt<32>(Imm.getSExtValue()))
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return TTI::TCC_Free;
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}
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break;
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case Intrinsic::experimental_stackmap:
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if ((Idx < 2) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue())))
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return TTI::TCC_Free;
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break;
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case Intrinsic::experimental_patchpoint_void:
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case Intrinsic::experimental_patchpoint_i64:
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if ((Idx < 4) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue())))
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return TTI::TCC_Free;
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break;
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}
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return SystemZTTIImpl::getIntImmCost(Imm, Ty);
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}
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TargetTransformInfo::PopcntSupportKind
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SystemZTTIImpl::getPopcntSupport(unsigned TyWidth) {
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assert(isPowerOf2_32(TyWidth) && "Type width must be power of 2");
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if (ST->hasPopulationCount() && TyWidth <= 64)
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return TTI::PSK_FastHardware;
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return TTI::PSK_Software;
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}
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void SystemZTTIImpl::getUnrollingPreferences(Loop *L,
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TTI::UnrollingPreferences &UP) {
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// Find out if L contains a call, what the machine instruction count
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// estimate is, and how many stores there are.
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bool HasCall = false;
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unsigned NumStores = 0;
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for (auto &BB : L->blocks())
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for (auto &I : *BB) {
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if (isa<CallInst>(&I) || isa<InvokeInst>(&I)) {
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ImmutableCallSite CS(&I);
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if (const Function *F = CS.getCalledFunction()) {
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if (isLoweredToCall(F))
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HasCall = true;
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if (F->getIntrinsicID() == Intrinsic::memcpy ||
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F->getIntrinsicID() == Intrinsic::memset)
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NumStores++;
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} else { // indirect call.
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HasCall = true;
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}
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}
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if (isa<StoreInst>(&I)) {
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Type *MemAccessTy = I.getOperand(0)->getType();
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NumStores += getMemoryOpCost(Instruction::Store, MemAccessTy, 0, 0);
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}
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}
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// The z13 processor will run out of store tags if too many stores
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// are fed into it too quickly. Therefore make sure there are not
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// too many stores in the resulting unrolled loop.
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unsigned const Max = (NumStores ? (12 / NumStores) : UINT_MAX);
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if (HasCall) {
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// Only allow full unrolling if loop has any calls.
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UP.FullUnrollMaxCount = Max;
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UP.MaxCount = 1;
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return;
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}
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UP.MaxCount = Max;
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if (UP.MaxCount <= 1)
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return;
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// Allow partial and runtime trip count unrolling.
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UP.Partial = UP.Runtime = true;
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UP.PartialThreshold = 75;
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UP.DefaultUnrollRuntimeCount = 4;
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// Allow expensive instructions in the pre-header of the loop.
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UP.AllowExpensiveTripCount = true;
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UP.Force = true;
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}
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unsigned SystemZTTIImpl::getNumberOfRegisters(bool Vector) {
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if (!Vector)
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// Discount the stack pointer. Also leave out %r0, since it can't
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// be used in an address.
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return 14;
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if (ST->hasVector())
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return 32;
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return 0;
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}
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unsigned SystemZTTIImpl::getRegisterBitWidth(bool Vector) {
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if (!Vector)
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return 64;
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if (ST->hasVector())
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return 128;
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return 0;
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}
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int SystemZTTIImpl::getArithmeticInstrCost(
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unsigned Opcode, Type *Ty,
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TTI::OperandValueKind Op1Info, TTI::OperandValueKind Op2Info,
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TTI::OperandValueProperties Opd1PropInfo,
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TTI::OperandValueProperties Opd2PropInfo,
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ArrayRef<const Value *> Args) {
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// TODO: return a good value for BB-VECTORIZER that includes the
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// immediate loads, which we do not want to count for the loop
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// vectorizer, since they are hopefully hoisted out of the loop. This
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// would require a new parameter 'InLoop', but not sure if constant
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// args are common enough to motivate this.
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unsigned ScalarBits = Ty->getScalarSizeInBits();
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if (Ty->isVectorTy()) {
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assert (ST->hasVector() && "getArithmeticInstrCost() called with vector type.");
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unsigned VF = Ty->getVectorNumElements();
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unsigned NumVectors = getNumberOfParts(Ty);
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// These vector operations are custom handled, but are still supported
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// with one instruction per vector, regardless of element size.
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if (Opcode == Instruction::Shl || Opcode == Instruction::LShr ||
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Opcode == Instruction::AShr) {
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return NumVectors;
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}
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// These FP operations are supported with a single vector instruction for
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// double (base implementation assumes float generally costs 2). For
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// FP128, the scalar cost is 1, and there is no overhead since the values
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// are already in scalar registers.
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if (Opcode == Instruction::FAdd || Opcode == Instruction::FSub ||
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Opcode == Instruction::FMul || Opcode == Instruction::FDiv) {
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switch (ScalarBits) {
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case 32: {
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// Return the cost of multiple scalar invocation plus the cost of
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// inserting and extracting the values.
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unsigned ScalarCost = getArithmeticInstrCost(Opcode, Ty->getScalarType());
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unsigned Cost = (VF * ScalarCost) + getScalarizationOverhead(Ty, Args);
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// FIXME: VF 2 for these FP operations are currently just as
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// expensive as for VF 4.
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if (VF == 2)
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Cost *= 2;
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return Cost;
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}
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case 64:
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case 128:
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return NumVectors;
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default:
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break;
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}
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}
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// There is no native support for FRem.
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if (Opcode == Instruction::FRem) {
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unsigned Cost = (VF * LIBCALL_COST) + getScalarizationOverhead(Ty, Args);
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// FIXME: VF 2 for float is currently just as expensive as for VF 4.
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if (VF == 2 && ScalarBits == 32)
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Cost *= 2;
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return Cost;
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}
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}
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else { // Scalar:
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// These FP operations are supported with a dedicated instruction for
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// float, double and fp128 (base implementation assumes float generally
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// costs 2).
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if (Opcode == Instruction::FAdd || Opcode == Instruction::FSub ||
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Opcode == Instruction::FMul || Opcode == Instruction::FDiv)
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return 1;
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// There is no native support for FRem.
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if (Opcode == Instruction::FRem)
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return LIBCALL_COST;
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if (Opcode == Instruction::LShr || Opcode == Instruction::AShr)
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return (ScalarBits >= 32 ? 1 : 2 /*ext*/);
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// Or requires one instruction, although it has custom handling for i64.
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if (Opcode == Instruction::Or)
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return 1;
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if (Opcode == Instruction::Xor && ScalarBits == 1)
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// 2 * ipm sequences ; xor ; shift ; compare
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return 7;
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// An extra extension for narrow types is needed.
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if ((Opcode == Instruction::SDiv || Opcode == Instruction::SRem))
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// sext of op(s) for narrow types
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return (ScalarBits < 32 ? 4 : (ScalarBits == 32 ? 2 : 1));
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if (Opcode == Instruction::UDiv || Opcode == Instruction::URem)
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// Clearing of low 64 bit reg + sext of op(s) for narrow types + dl[g]r
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return (ScalarBits < 32 ? 4 : 2);
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}
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// Fallback to the default implementation.
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return BaseT::getArithmeticInstrCost(Opcode, Ty, Op1Info, Op2Info,
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Opd1PropInfo, Opd2PropInfo, Args);
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}
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int SystemZTTIImpl::getShuffleCost(TTI::ShuffleKind Kind, Type *Tp, int Index,
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Type *SubTp) {
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assert (Tp->isVectorTy());
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assert (ST->hasVector() && "getShuffleCost() called.");
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unsigned NumVectors = getNumberOfParts(Tp);
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// TODO: Since fp32 is expanded, the shuffle cost should always be 0.
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// FP128 values are always in scalar registers, so there is no work
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// involved with a shuffle, except for broadcast. In that case register
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// moves are done with a single instruction per element.
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if (Tp->getScalarType()->isFP128Ty())
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return (Kind == TargetTransformInfo::SK_Broadcast ? NumVectors - 1 : 0);
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switch (Kind) {
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case TargetTransformInfo::SK_ExtractSubvector:
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// ExtractSubvector Index indicates start offset.
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// Extracting a subvector from first index is a noop.
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return (Index == 0 ? 0 : NumVectors);
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case TargetTransformInfo::SK_Broadcast:
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// Loop vectorizer calls here to figure out the extra cost of
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// broadcasting a loaded value to all elements of a vector. Since vlrep
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// loads and replicates with a single instruction, adjust the returned
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// value.
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return NumVectors - 1;
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default:
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// SystemZ supports single instruction permutation / replication.
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return NumVectors;
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}
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return BaseT::getShuffleCost(Kind, Tp, Index, SubTp);
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}
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// Return the log2 difference of the element sizes of the two vector types.
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static unsigned getElSizeLog2Diff(Type *Ty0, Type *Ty1) {
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unsigned Bits0 = Ty0->getScalarSizeInBits();
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unsigned Bits1 = Ty1->getScalarSizeInBits();
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if (Bits1 > Bits0)
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return (Log2_32(Bits1) - Log2_32(Bits0));
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return (Log2_32(Bits0) - Log2_32(Bits1));
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}
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// Return the number of instructions needed to truncate SrcTy to DstTy.
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unsigned SystemZTTIImpl::
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getVectorTruncCost(Type *SrcTy, Type *DstTy) {
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assert (SrcTy->isVectorTy() && DstTy->isVectorTy());
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assert (SrcTy->getPrimitiveSizeInBits() > DstTy->getPrimitiveSizeInBits() &&
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"Packing must reduce size of vector type.");
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assert (SrcTy->getVectorNumElements() == DstTy->getVectorNumElements() &&
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"Packing should not change number of elements.");
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// TODO: Since fp32 is expanded, the extract cost should always be 0.
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unsigned NumParts = getNumberOfParts(SrcTy);
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if (NumParts <= 2)
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// Up to 2 vector registers can be truncated efficiently with pack or
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// permute. The latter requires an immediate mask to be loaded, which
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// typically gets hoisted out of a loop. TODO: return a good value for
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// BB-VECTORIZER that includes the immediate loads, which we do not want
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// to count for the loop vectorizer.
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return 1;
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unsigned Cost = 0;
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unsigned Log2Diff = getElSizeLog2Diff(SrcTy, DstTy);
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unsigned VF = SrcTy->getVectorNumElements();
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for (unsigned P = 0; P < Log2Diff; ++P) {
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if (NumParts > 1)
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NumParts /= 2;
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Cost += NumParts;
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}
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// Currently, a general mix of permutes and pack instructions is output by
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// isel, which follow the cost computation above except for this case which
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// is one instruction less:
|
|
if (VF == 8 && SrcTy->getScalarSizeInBits() == 64 &&
|
|
DstTy->getScalarSizeInBits() == 8)
|
|
Cost--;
|
|
|
|
return Cost;
|
|
}
|
|
|
|
// Return the cost of converting a vector bitmask produced by a compare
|
|
// (SrcTy), to the type of the select or extend instruction (DstTy).
|
|
unsigned SystemZTTIImpl::
|
|
getVectorBitmaskConversionCost(Type *SrcTy, Type *DstTy) {
|
|
assert (SrcTy->isVectorTy() && DstTy->isVectorTy() &&
|
|
"Should only be called with vector types.");
|
|
|
|
unsigned PackCost = 0;
|
|
unsigned SrcScalarBits = SrcTy->getScalarSizeInBits();
|
|
unsigned DstScalarBits = DstTy->getScalarSizeInBits();
|
|
unsigned Log2Diff = getElSizeLog2Diff(SrcTy, DstTy);
|
|
if (SrcScalarBits > DstScalarBits)
|
|
// The bitmask will be truncated.
|
|
PackCost = getVectorTruncCost(SrcTy, DstTy);
|
|
else if (SrcScalarBits < DstScalarBits) {
|
|
unsigned DstNumParts = getNumberOfParts(DstTy);
|
|
// Each vector select needs its part of the bitmask unpacked.
|
|
PackCost = Log2Diff * DstNumParts;
|
|
// Extra cost for moving part of mask before unpacking.
|
|
PackCost += DstNumParts - 1;
|
|
}
|
|
|
|
return PackCost;
|
|
}
|
|
|
|
// Return the type of the compared operands. This is needed to compute the
|
|
// cost for a Select / ZExt or SExt instruction.
|
|
static Type *getCmpOpsType(const Instruction *I, unsigned VF = 1) {
|
|
Type *OpTy = nullptr;
|
|
if (CmpInst *CI = dyn_cast<CmpInst>(I->getOperand(0)))
|
|
OpTy = CI->getOperand(0)->getType();
|
|
else if (Instruction *LogicI = dyn_cast<Instruction>(I->getOperand(0)))
|
|
if (LogicI->getNumOperands() == 2)
|
|
if (CmpInst *CI0 = dyn_cast<CmpInst>(LogicI->getOperand(0)))
|
|
if (isa<CmpInst>(LogicI->getOperand(1)))
|
|
OpTy = CI0->getOperand(0)->getType();
|
|
|
|
if (OpTy != nullptr) {
|
|
if (VF == 1) {
|
|
assert (!OpTy->isVectorTy() && "Expected scalar type");
|
|
return OpTy;
|
|
}
|
|
// Return the potentially vectorized type based on 'I' and 'VF'. 'I' may
|
|
// be either scalar or already vectorized with a same or lesser VF.
|
|
Type *ElTy = OpTy->getScalarType();
|
|
return VectorType::get(ElTy, VF);
|
|
}
|
|
|
|
return nullptr;
|
|
}
|
|
|
|
int SystemZTTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src,
|
|
const Instruction *I) {
|
|
unsigned DstScalarBits = Dst->getScalarSizeInBits();
|
|
unsigned SrcScalarBits = Src->getScalarSizeInBits();
|
|
|
|
if (Src->isVectorTy()) {
|
|
assert (ST->hasVector() && "getCastInstrCost() called with vector type.");
|
|
assert (Dst->isVectorTy());
|
|
unsigned VF = Src->getVectorNumElements();
|
|
unsigned NumDstVectors = getNumberOfParts(Dst);
|
|
unsigned NumSrcVectors = getNumberOfParts(Src);
|
|
|
|
if (Opcode == Instruction::Trunc) {
|
|
if (Src->getScalarSizeInBits() == Dst->getScalarSizeInBits())
|
|
return 0; // Check for NOOP conversions.
|
|
return getVectorTruncCost(Src, Dst);
|
|
}
|
|
|
|
if (Opcode == Instruction::ZExt || Opcode == Instruction::SExt) {
|
|
if (SrcScalarBits >= 8) {
|
|
// ZExt/SExt will be handled with one unpack per doubling of width.
|
|
unsigned NumUnpacks = getElSizeLog2Diff(Src, Dst);
|
|
|
|
// For types that spans multiple vector registers, some additional
|
|
// instructions are used to setup the unpacking.
|
|
unsigned NumSrcVectorOps =
|
|
(NumUnpacks > 1 ? (NumDstVectors - NumSrcVectors)
|
|
: (NumDstVectors / 2));
|
|
|
|
return (NumUnpacks * NumDstVectors) + NumSrcVectorOps;
|
|
}
|
|
else if (SrcScalarBits == 1) {
|
|
// This should be extension of a compare i1 result.
|
|
// If we know what the widths of the compared operands, get the
|
|
// cost of converting it to Dst. Otherwise assume same widths.
|
|
unsigned Cost = 0;
|
|
Type *CmpOpTy = ((I != nullptr) ? getCmpOpsType(I, VF) : nullptr);
|
|
if (CmpOpTy != nullptr)
|
|
Cost = getVectorBitmaskConversionCost(CmpOpTy, Dst);
|
|
if (Opcode == Instruction::ZExt)
|
|
// One 'vn' per dst vector with an immediate mask.
|
|
Cost += NumDstVectors;
|
|
return Cost;
|
|
}
|
|
}
|
|
|
|
if (Opcode == Instruction::SIToFP || Opcode == Instruction::UIToFP ||
|
|
Opcode == Instruction::FPToSI || Opcode == Instruction::FPToUI) {
|
|
// TODO: Fix base implementation which could simplify things a bit here
|
|
// (seems to miss on differentiating on scalar/vector types).
|
|
|
|
// Only 64 bit vector conversions are natively supported.
|
|
if (SrcScalarBits == 64 && DstScalarBits == 64)
|
|
return NumDstVectors;
|
|
|
|
// Return the cost of multiple scalar invocation plus the cost of
|
|
// inserting and extracting the values. Base implementation does not
|
|
// realize float->int gets scalarized.
|
|
unsigned ScalarCost = getCastInstrCost(Opcode, Dst->getScalarType(),
|
|
Src->getScalarType());
|
|
unsigned TotCost = VF * ScalarCost;
|
|
bool NeedsInserts = true, NeedsExtracts = true;
|
|
// FP128 registers do not get inserted or extracted.
|
|
if (DstScalarBits == 128 &&
|
|
(Opcode == Instruction::SIToFP || Opcode == Instruction::UIToFP))
|
|
NeedsInserts = false;
|
|
if (SrcScalarBits == 128 &&
|
|
(Opcode == Instruction::FPToSI || Opcode == Instruction::FPToUI))
|
|
NeedsExtracts = false;
|
|
|
|
TotCost += getScalarizationOverhead(Dst, NeedsInserts, NeedsExtracts);
|
|
|
|
// FIXME: VF 2 for float<->i32 is currently just as expensive as for VF 4.
|
|
if (VF == 2 && SrcScalarBits == 32 && DstScalarBits == 32)
|
|
TotCost *= 2;
|
|
|
|
return TotCost;
|
|
}
|
|
|
|
if (Opcode == Instruction::FPTrunc) {
|
|
if (SrcScalarBits == 128) // fp128 -> double/float + inserts of elements.
|
|
return VF /*ldxbr/lexbr*/ + getScalarizationOverhead(Dst, true, false);
|
|
else // double -> float
|
|
return VF / 2 /*vledb*/ + std::max(1U, VF / 4 /*vperm*/);
|
|
}
|
|
|
|
if (Opcode == Instruction::FPExt) {
|
|
if (SrcScalarBits == 32 && DstScalarBits == 64) {
|
|
// float -> double is very rare and currently unoptimized. Instead of
|
|
// using vldeb, which can do two at a time, all conversions are
|
|
// scalarized.
|
|
return VF * 2;
|
|
}
|
|
// -> fp128. VF * lxdb/lxeb + extraction of elements.
|
|
return VF + getScalarizationOverhead(Src, false, true);
|
|
}
|
|
}
|
|
else { // Scalar
|
|
assert (!Dst->isVectorTy());
|
|
|
|
if (Opcode == Instruction::SIToFP || Opcode == Instruction::UIToFP)
|
|
return (SrcScalarBits >= 32 ? 1 : 2 /*i8/i16 extend*/);
|
|
|
|
if ((Opcode == Instruction::ZExt || Opcode == Instruction::SExt) &&
|
|
Src->isIntegerTy(1)) {
|
|
// This should be extension of a compare i1 result, which is done with
|
|
// ipm and a varying sequence of instructions.
|
|
unsigned Cost = 0;
|
|
if (Opcode == Instruction::SExt)
|
|
Cost = (DstScalarBits < 64 ? 3 : 4);
|
|
if (Opcode == Instruction::ZExt)
|
|
Cost = 3;
|
|
Type *CmpOpTy = ((I != nullptr) ? getCmpOpsType(I) : nullptr);
|
|
if (CmpOpTy != nullptr && CmpOpTy->isFloatingPointTy())
|
|
// If operands of an fp-type was compared, this costs +1.
|
|
Cost++;
|
|
|
|
return Cost;
|
|
}
|
|
}
|
|
|
|
return BaseT::getCastInstrCost(Opcode, Dst, Src, I);
|
|
}
|
|
|
|
int SystemZTTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy,
|
|
const Instruction *I) {
|
|
if (ValTy->isVectorTy()) {
|
|
assert (ST->hasVector() && "getCmpSelInstrCost() called with vector type.");
|
|
unsigned VF = ValTy->getVectorNumElements();
|
|
|
|
// Called with a compare instruction.
|
|
if (Opcode == Instruction::ICmp || Opcode == Instruction::FCmp) {
|
|
unsigned PredicateExtraCost = 0;
|
|
if (I != nullptr) {
|
|
// Some predicates cost one or two extra instructions.
|
|
switch (dyn_cast<CmpInst>(I)->getPredicate()) {
|
|
case CmpInst::Predicate::ICMP_NE:
|
|
case CmpInst::Predicate::ICMP_UGE:
|
|
case CmpInst::Predicate::ICMP_ULE:
|
|
case CmpInst::Predicate::ICMP_SGE:
|
|
case CmpInst::Predicate::ICMP_SLE:
|
|
PredicateExtraCost = 1;
|
|
break;
|
|
case CmpInst::Predicate::FCMP_ONE:
|
|
case CmpInst::Predicate::FCMP_ORD:
|
|
case CmpInst::Predicate::FCMP_UEQ:
|
|
case CmpInst::Predicate::FCMP_UNO:
|
|
PredicateExtraCost = 2;
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
|
|
// Float is handled with 2*vmr[lh]f + 2*vldeb + vfchdb for each pair of
|
|
// floats. FIXME: <2 x float> generates same code as <4 x float>.
|
|
unsigned CmpCostPerVector = (ValTy->getScalarType()->isFloatTy() ? 10 : 1);
|
|
unsigned NumVecs_cmp = getNumberOfParts(ValTy);
|
|
|
|
unsigned Cost = (NumVecs_cmp * (CmpCostPerVector + PredicateExtraCost));
|
|
return Cost;
|
|
}
|
|
else { // Called with a select instruction.
|
|
assert (Opcode == Instruction::Select);
|
|
|
|
// We can figure out the extra cost of packing / unpacking if the
|
|
// instruction was passed and the compare instruction is found.
|
|
unsigned PackCost = 0;
|
|
Type *CmpOpTy = ((I != nullptr) ? getCmpOpsType(I, VF) : nullptr);
|
|
if (CmpOpTy != nullptr)
|
|
PackCost =
|
|
getVectorBitmaskConversionCost(CmpOpTy, ValTy);
|
|
|
|
return getNumberOfParts(ValTy) /*vsel*/ + PackCost;
|
|
}
|
|
}
|
|
else { // Scalar
|
|
switch (Opcode) {
|
|
case Instruction::ICmp: {
|
|
unsigned Cost = 1;
|
|
if (ValTy->isIntegerTy() && ValTy->getScalarSizeInBits() <= 16)
|
|
Cost += 2; // extend both operands
|
|
return Cost;
|
|
}
|
|
case Instruction::Select:
|
|
if (ValTy->isFloatingPointTy())
|
|
return 4; // No load on condition for FP, so this costs a conditional jump.
|
|
return 1; // Load On Condition.
|
|
}
|
|
}
|
|
|
|
return BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy, nullptr);
|
|
}
|
|
|
|
int SystemZTTIImpl::
|
|
getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index) {
|
|
// vlvgp will insert two grs into a vector register, so only count half the
|
|
// number of instructions.
|
|
if (Opcode == Instruction::InsertElement &&
|
|
Val->getScalarType()->isIntegerTy(64))
|
|
return ((Index % 2 == 0) ? 1 : 0);
|
|
|
|
if (Opcode == Instruction::ExtractElement) {
|
|
int Cost = ((Val->getScalarSizeInBits() == 1) ? 2 /*+test-under-mask*/ : 1);
|
|
|
|
// Give a slight penalty for moving out of vector pipeline to FXU unit.
|
|
if (Index == 0 && Val->getScalarType()->isIntegerTy())
|
|
Cost += 1;
|
|
|
|
return Cost;
|
|
}
|
|
|
|
return BaseT::getVectorInstrCost(Opcode, Val, Index);
|
|
}
|
|
|
|
int SystemZTTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src,
|
|
unsigned Alignment, unsigned AddressSpace,
|
|
const Instruction *I) {
|
|
assert(!Src->isVoidTy() && "Invalid type");
|
|
|
|
if (!Src->isVectorTy() && Opcode == Instruction::Load &&
|
|
I != nullptr && I->hasOneUse()) {
|
|
const Instruction *UserI = cast<Instruction>(*I->user_begin());
|
|
unsigned Bits = Src->getScalarSizeInBits();
|
|
bool FoldsLoad = false;
|
|
switch (UserI->getOpcode()) {
|
|
case Instruction::ICmp:
|
|
case Instruction::Add:
|
|
case Instruction::Sub:
|
|
case Instruction::Mul:
|
|
case Instruction::SDiv:
|
|
case Instruction::UDiv:
|
|
case Instruction::And:
|
|
case Instruction::Or:
|
|
case Instruction::Xor:
|
|
// This also makes sense for float operations, but disabled for now due
|
|
// to regressions.
|
|
// case Instruction::FCmp:
|
|
// case Instruction::FAdd:
|
|
// case Instruction::FSub:
|
|
// case Instruction::FMul:
|
|
// case Instruction::FDiv:
|
|
FoldsLoad = (Bits == 32 || Bits == 64);
|
|
break;
|
|
}
|
|
|
|
if (FoldsLoad) {
|
|
assert (UserI->getNumOperands() == 2 &&
|
|
"Expected to only handle binops.");
|
|
|
|
// UserI can't fold two loads, so in that case return 0 cost only
|
|
// half of the time.
|
|
for (unsigned i = 0; i < 2; ++i) {
|
|
if (UserI->getOperand(i) == I)
|
|
continue;
|
|
if (LoadInst *LI = dyn_cast<LoadInst>(UserI->getOperand(i))) {
|
|
if (LI->hasOneUse())
|
|
return i == 0;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
unsigned NumOps = getNumberOfParts(Src);
|
|
|
|
if (Src->getScalarSizeInBits() == 128)
|
|
// 128 bit scalars are held in a pair of two 64 bit registers.
|
|
NumOps *= 2;
|
|
|
|
return NumOps;
|
|
}
|
|
|
|
int SystemZTTIImpl::getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy,
|
|
unsigned Factor,
|
|
ArrayRef<unsigned> Indices,
|
|
unsigned Alignment,
|
|
unsigned AddressSpace) {
|
|
assert(isa<VectorType>(VecTy) &&
|
|
"Expect a vector type for interleaved memory op");
|
|
|
|
unsigned WideBits = (VecTy->isPtrOrPtrVectorTy() ?
|
|
(64U * VecTy->getVectorNumElements()) : VecTy->getPrimitiveSizeInBits());
|
|
assert (WideBits > 0 && "Could not compute size of vector");
|
|
int NumWideParts =
|
|
((WideBits % 128U) ? ((WideBits / 128U) + 1) : (WideBits / 128U));
|
|
|
|
// How many source vectors are handled to produce a vectorized operand?
|
|
int NumElsPerVector = (VecTy->getVectorNumElements() / NumWideParts);
|
|
int NumSrcParts =
|
|
((NumWideParts > NumElsPerVector) ? NumElsPerVector : NumWideParts);
|
|
|
|
// A Load group may have gaps.
|
|
unsigned NumOperands =
|
|
((Opcode == Instruction::Load) ? Indices.size() : Factor);
|
|
|
|
// Each needed permute takes two vectors as input.
|
|
if (NumSrcParts > 1)
|
|
NumSrcParts--;
|
|
int NumPermutes = NumSrcParts * NumOperands;
|
|
|
|
// Cost of load/store operations and the permutations needed.
|
|
return NumWideParts + NumPermutes;
|
|
}
|