63 lines
2.1 KiB
TableGen
63 lines
2.1 KiB
TableGen
//===-- X86InstrSVM.td - SVM Instruction Set Extension -----*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the instructions that make up the AMD SVM instruction
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// set.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// SVM instructions
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// 0F 01 D9
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def VMMCALL : I<0x01, MRM_D9, (outs), (ins), "vmmcall", []>, TB;
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// 0F 01 DC
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def STGI : I<0x01, MRM_DC, (outs), (ins), "stgi", []>, TB;
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// 0F 01 DD
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def CLGI : I<0x01, MRM_DD, (outs), (ins), "clgi", []>, TB;
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// 0F 01 DE
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let Uses = [EAX] in
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def SKINIT : I<0x01, MRM_DE, (outs), (ins), "skinit\t{%eax|eax}", []>, TB;
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// 0F 01 D8
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let Uses = [EAX] in
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def VMRUN32 : I<0x01, MRM_D8, (outs), (ins),
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"vmrun\t{%eax|eax}", []>, TB, Requires<[Not64BitMode]>;
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let Uses = [RAX] in
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def VMRUN64 : I<0x01, MRM_D8, (outs), (ins),
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"vmrun\t{%rax|rax}", []>, TB, Requires<[In64BitMode]>;
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// 0F 01 DA
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let Uses = [EAX] in
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def VMLOAD32 : I<0x01, MRM_DA, (outs), (ins),
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"vmload\t{%eax|eax}", []>, TB, Requires<[Not64BitMode]>;
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let Uses = [RAX] in
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def VMLOAD64 : I<0x01, MRM_DA, (outs), (ins),
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"vmload\t{%rax|rax}", []>, TB, Requires<[In64BitMode]>;
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// 0F 01 DB
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let Uses = [EAX] in
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def VMSAVE32 : I<0x01, MRM_DB, (outs), (ins),
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"vmsave\t{%eax|eax}", []>, TB, Requires<[Not64BitMode]>;
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let Uses = [RAX] in
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def VMSAVE64 : I<0x01, MRM_DB, (outs), (ins),
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"vmsave\t{%rax|rax}", []>, TB, Requires<[In64BitMode]>;
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// 0F 01 DF
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let Uses = [EAX, ECX] in
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def INVLPGA32 : I<0x01, MRM_DF, (outs), (ins),
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"invlpga\t{%ecx, %eax|eax, ecx}", []>, TB, Requires<[Not64BitMode]>;
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let Uses = [RAX, ECX] in
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def INVLPGA64 : I<0x01, MRM_DF, (outs), (ins),
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"invlpga\t{%ecx, %rax|rax, ecx}", []>, TB, Requires<[In64BitMode]>;
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