571 lines
18 KiB
C++
571 lines
18 KiB
C++
//===- X86InstructionSelector.cpp ----------------------------*- C++ -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This file implements the targeting of the InstructionSelector class for
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/// X86.
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/// \todo This should be generated by TableGen.
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//===----------------------------------------------------------------------===//
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#include "X86InstrBuilder.h"
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#include "X86InstrInfo.h"
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#include "X86RegisterBankInfo.h"
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#include "X86RegisterInfo.h"
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#include "X86Subtarget.h"
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#include "X86TargetMachine.h"
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#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineOperand.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/IR/Type.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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#define DEBUG_TYPE "X86-isel"
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using namespace llvm;
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#ifndef LLVM_BUILD_GLOBAL_ISEL
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#error "You shouldn't build this"
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#endif
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namespace {
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#define GET_GLOBALISEL_PREDICATE_BITSET
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#include "X86GenGlobalISel.inc"
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#undef GET_GLOBALISEL_PREDICATE_BITSET
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class X86InstructionSelector : public InstructionSelector {
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public:
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X86InstructionSelector(const X86TargetMachine &TM, const X86Subtarget &STI,
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const X86RegisterBankInfo &RBI);
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bool select(MachineInstr &I) const override;
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private:
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/// tblgen-erated 'select' implementation, used as the initial selector for
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/// the patterns that don't require complex C++.
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bool selectImpl(MachineInstr &I) const;
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// TODO: remove after suported by Tablegen-erated instruction selection.
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unsigned getFAddOp(LLT &Ty, const RegisterBank &RB) const;
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unsigned getFSubOp(LLT &Ty, const RegisterBank &RB) const;
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unsigned getLoadStoreOp(LLT &Ty, const RegisterBank &RB, unsigned Opc,
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uint64_t Alignment) const;
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bool selectBinaryOp(MachineInstr &I, MachineRegisterInfo &MRI,
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MachineFunction &MF) const;
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bool selectLoadStoreOp(MachineInstr &I, MachineRegisterInfo &MRI,
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MachineFunction &MF) const;
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bool selectFrameIndexOrGep(MachineInstr &I, MachineRegisterInfo &MRI,
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MachineFunction &MF) const;
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bool selectConstant(MachineInstr &I, MachineRegisterInfo &MRI,
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MachineFunction &MF) const;
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bool selectTrunc(MachineInstr &I, MachineRegisterInfo &MRI,
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MachineFunction &MF) const;
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const X86TargetMachine &TM;
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const X86Subtarget &STI;
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const X86InstrInfo &TII;
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const X86RegisterInfo &TRI;
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const X86RegisterBankInfo &RBI;
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#define GET_GLOBALISEL_PREDICATES_DECL
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#include "X86GenGlobalISel.inc"
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#undef GET_GLOBALISEL_PREDICATES_DECL
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#define GET_GLOBALISEL_TEMPORARIES_DECL
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#include "X86GenGlobalISel.inc"
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#undef GET_GLOBALISEL_TEMPORARIES_DECL
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};
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} // end anonymous namespace
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#define GET_GLOBALISEL_IMPL
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#include "X86GenGlobalISel.inc"
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#undef GET_GLOBALISEL_IMPL
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X86InstructionSelector::X86InstructionSelector(const X86TargetMachine &TM,
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const X86Subtarget &STI,
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const X86RegisterBankInfo &RBI)
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: InstructionSelector(), TM(TM), STI(STI), TII(*STI.getInstrInfo()),
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TRI(*STI.getRegisterInfo()), RBI(RBI),
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#define GET_GLOBALISEL_PREDICATES_INIT
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#include "X86GenGlobalISel.inc"
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#undef GET_GLOBALISEL_PREDICATES_INIT
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#define GET_GLOBALISEL_TEMPORARIES_INIT
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#include "X86GenGlobalISel.inc"
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#undef GET_GLOBALISEL_TEMPORARIES_INIT
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{
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}
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// FIXME: This should be target-independent, inferred from the types declared
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// for each class in the bank.
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static const TargetRegisterClass *
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getRegClassForTypeOnBank(LLT Ty, const RegisterBank &RB) {
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if (RB.getID() == X86::GPRRegBankID) {
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if (Ty.getSizeInBits() <= 8)
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return &X86::GR8RegClass;
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if (Ty.getSizeInBits() == 16)
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return &X86::GR16RegClass;
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if (Ty.getSizeInBits() == 32)
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return &X86::GR32RegClass;
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if (Ty.getSizeInBits() == 64)
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return &X86::GR64RegClass;
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}
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if (RB.getID() == X86::VECRRegBankID) {
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if (Ty.getSizeInBits() == 32)
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return &X86::FR32XRegClass;
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if (Ty.getSizeInBits() == 64)
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return &X86::FR64XRegClass;
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if (Ty.getSizeInBits() == 128)
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return &X86::VR128XRegClass;
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if (Ty.getSizeInBits() == 256)
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return &X86::VR256XRegClass;
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if (Ty.getSizeInBits() == 512)
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return &X86::VR512RegClass;
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}
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llvm_unreachable("Unknown RegBank!");
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}
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// Set X86 Opcode and constrain DestReg.
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static bool selectCopy(MachineInstr &I, const TargetInstrInfo &TII,
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MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI,
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const RegisterBankInfo &RBI) {
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unsigned DstReg = I.getOperand(0).getReg();
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if (TargetRegisterInfo::isPhysicalRegister(DstReg)) {
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assert(I.isCopy() && "Generic operators do not allow physical registers");
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return true;
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}
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const RegisterBank &RegBank = *RBI.getRegBank(DstReg, MRI, TRI);
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const unsigned DstSize = MRI.getType(DstReg).getSizeInBits();
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unsigned SrcReg = I.getOperand(1).getReg();
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const unsigned SrcSize = RBI.getSizeInBits(SrcReg, MRI, TRI);
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assert((!TargetRegisterInfo::isPhysicalRegister(SrcReg) || I.isCopy()) &&
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"No phys reg on generic operators");
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assert((DstSize == SrcSize ||
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// Copies are a mean to setup initial types, the number of
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// bits may not exactly match.
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(TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
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DstSize <= RBI.getSizeInBits(SrcReg, MRI, TRI))) &&
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"Copy with different width?!");
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const TargetRegisterClass *RC = nullptr;
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switch (RegBank.getID()) {
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case X86::GPRRegBankID:
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assert((DstSize <= 64) && "GPRs cannot get more than 64-bit width values.");
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RC = getRegClassForTypeOnBank(MRI.getType(DstReg), RegBank);
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// Change the physical register
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if (SrcSize > DstSize && TargetRegisterInfo::isPhysicalRegister(SrcReg)) {
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if (RC == &X86::GR32RegClass)
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I.getOperand(1).setSubReg(X86::sub_32bit);
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else if (RC == &X86::GR16RegClass)
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I.getOperand(1).setSubReg(X86::sub_16bit);
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else if (RC == &X86::GR8RegClass)
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I.getOperand(1).setSubReg(X86::sub_8bit);
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I.getOperand(1).substPhysReg(SrcReg, TRI);
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}
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break;
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case X86::VECRRegBankID:
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RC = getRegClassForTypeOnBank(MRI.getType(DstReg), RegBank);
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break;
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default:
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llvm_unreachable("Unknown RegBank!");
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}
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// No need to constrain SrcReg. It will get constrained when
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// we hit another of its use or its defs.
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// Copies do not have constraints.
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const TargetRegisterClass *OldRC = MRI.getRegClassOrNull(DstReg);
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if (!OldRC || !RC->hasSubClassEq(OldRC)) {
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if (!RBI.constrainGenericRegister(DstReg, *RC, MRI)) {
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DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode())
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<< " operand\n");
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return false;
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}
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}
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I.setDesc(TII.get(X86::COPY));
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return true;
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}
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bool X86InstructionSelector::select(MachineInstr &I) const {
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assert(I.getParent() && "Instruction should be in a basic block!");
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assert(I.getParent()->getParent() && "Instruction should be in a function!");
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MachineBasicBlock &MBB = *I.getParent();
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MachineFunction &MF = *MBB.getParent();
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MachineRegisterInfo &MRI = MF.getRegInfo();
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unsigned Opcode = I.getOpcode();
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if (!isPreISelGenericOpcode(Opcode)) {
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// Certain non-generic instructions also need some special handling.
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if (I.isCopy())
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return selectCopy(I, TII, MRI, TRI, RBI);
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// TODO: handle more cases - LOAD_STACK_GUARD, PHI
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return true;
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}
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assert(I.getNumOperands() == I.getNumExplicitOperands() &&
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"Generic instruction has unexpected implicit operands\n");
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if (selectImpl(I))
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return true;
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DEBUG(dbgs() << " C++ instruction selection: "; I.print(dbgs()));
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// TODO: This should be implemented by tblgen.
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if (selectBinaryOp(I, MRI, MF))
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return true;
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if (selectLoadStoreOp(I, MRI, MF))
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return true;
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if (selectFrameIndexOrGep(I, MRI, MF))
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return true;
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if (selectConstant(I, MRI, MF))
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return true;
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if (selectTrunc(I, MRI, MF))
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return true;
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return false;
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}
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unsigned X86InstructionSelector::getFAddOp(LLT &Ty,
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const RegisterBank &RB) const {
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if (X86::VECRRegBankID != RB.getID())
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return TargetOpcode::G_FADD;
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if (Ty == LLT::scalar(32)) {
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if (STI.hasAVX512()) {
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return X86::VADDSSZrr;
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} else if (STI.hasAVX()) {
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return X86::VADDSSrr;
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} else if (STI.hasSSE1()) {
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return X86::ADDSSrr;
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}
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} else if (Ty == LLT::scalar(64)) {
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if (STI.hasAVX512()) {
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return X86::VADDSDZrr;
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} else if (STI.hasAVX()) {
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return X86::VADDSDrr;
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} else if (STI.hasSSE2()) {
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return X86::ADDSDrr;
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}
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} else if (Ty == LLT::vector(4, 32)) {
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if ((STI.hasAVX512()) && (STI.hasVLX())) {
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return X86::VADDPSZ128rr;
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} else if (STI.hasAVX()) {
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return X86::VADDPSrr;
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} else if (STI.hasSSE1()) {
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return X86::ADDPSrr;
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}
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}
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return TargetOpcode::G_FADD;
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}
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unsigned X86InstructionSelector::getFSubOp(LLT &Ty,
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const RegisterBank &RB) const {
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if (X86::VECRRegBankID != RB.getID())
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return TargetOpcode::G_FSUB;
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if (Ty == LLT::scalar(32)) {
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if (STI.hasAVX512()) {
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return X86::VSUBSSZrr;
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} else if (STI.hasAVX()) {
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return X86::VSUBSSrr;
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} else if (STI.hasSSE1()) {
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return X86::SUBSSrr;
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}
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} else if (Ty == LLT::scalar(64)) {
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if (STI.hasAVX512()) {
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return X86::VSUBSDZrr;
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} else if (STI.hasAVX()) {
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return X86::VSUBSDrr;
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} else if (STI.hasSSE2()) {
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return X86::SUBSDrr;
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}
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} else if (Ty == LLT::vector(4, 32)) {
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if ((STI.hasAVX512()) && (STI.hasVLX())) {
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return X86::VSUBPSZ128rr;
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} else if (STI.hasAVX()) {
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return X86::VSUBPSrr;
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} else if (STI.hasSSE1()) {
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return X86::SUBPSrr;
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}
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}
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return TargetOpcode::G_FSUB;
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}
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bool X86InstructionSelector::selectBinaryOp(MachineInstr &I,
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MachineRegisterInfo &MRI,
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MachineFunction &MF) const {
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const unsigned DefReg = I.getOperand(0).getReg();
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LLT Ty = MRI.getType(DefReg);
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const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI);
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unsigned NewOpc = I.getOpcode();
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switch (NewOpc) {
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case TargetOpcode::G_FADD:
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NewOpc = getFAddOp(Ty, RB);
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break;
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case TargetOpcode::G_FSUB:
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NewOpc = getFSubOp(Ty, RB);
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break;
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default:
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break;
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}
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if (NewOpc == I.getOpcode())
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return false;
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I.setDesc(TII.get(NewOpc));
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return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
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}
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unsigned X86InstructionSelector::getLoadStoreOp(LLT &Ty, const RegisterBank &RB,
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unsigned Opc,
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uint64_t Alignment) const {
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bool Isload = (Opc == TargetOpcode::G_LOAD);
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bool HasAVX = STI.hasAVX();
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bool HasAVX512 = STI.hasAVX512();
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bool HasVLX = STI.hasVLX();
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if (Ty == LLT::scalar(8)) {
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if (X86::GPRRegBankID == RB.getID())
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return Isload ? X86::MOV8rm : X86::MOV8mr;
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} else if (Ty == LLT::scalar(16)) {
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if (X86::GPRRegBankID == RB.getID())
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return Isload ? X86::MOV16rm : X86::MOV16mr;
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} else if (Ty == LLT::scalar(32) || Ty == LLT::pointer(0, 32)) {
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if (X86::GPRRegBankID == RB.getID())
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return Isload ? X86::MOV32rm : X86::MOV32mr;
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if (X86::VECRRegBankID == RB.getID())
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return Isload ? (HasAVX512 ? X86::VMOVSSZrm
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: HasAVX ? X86::VMOVSSrm : X86::MOVSSrm)
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: (HasAVX512 ? X86::VMOVSSZmr
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: HasAVX ? X86::VMOVSSmr : X86::MOVSSmr);
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} else if (Ty == LLT::scalar(64) || Ty == LLT::pointer(0, 64)) {
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if (X86::GPRRegBankID == RB.getID())
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return Isload ? X86::MOV64rm : X86::MOV64mr;
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if (X86::VECRRegBankID == RB.getID())
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return Isload ? (HasAVX512 ? X86::VMOVSDZrm
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: HasAVX ? X86::VMOVSDrm : X86::MOVSDrm)
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: (HasAVX512 ? X86::VMOVSDZmr
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: HasAVX ? X86::VMOVSDmr : X86::MOVSDmr);
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} else if (Ty.isVector() && Ty.getSizeInBits() == 128) {
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if (Alignment >= 16)
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return Isload ? (HasVLX ? X86::VMOVAPSZ128rm
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: HasAVX512
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? X86::VMOVAPSZ128rm_NOVLX
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: HasAVX ? X86::VMOVAPSrm : X86::MOVAPSrm)
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: (HasVLX ? X86::VMOVAPSZ128mr
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: HasAVX512
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? X86::VMOVAPSZ128mr_NOVLX
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: HasAVX ? X86::VMOVAPSmr : X86::MOVAPSmr);
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else
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return Isload ? (HasVLX ? X86::VMOVUPSZ128rm
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: HasAVX512
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? X86::VMOVUPSZ128rm_NOVLX
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: HasAVX ? X86::VMOVUPSrm : X86::MOVUPSrm)
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: (HasVLX ? X86::VMOVUPSZ128mr
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: HasAVX512
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? X86::VMOVUPSZ128mr_NOVLX
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: HasAVX ? X86::VMOVUPSmr : X86::MOVUPSmr);
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}
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return Opc;
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}
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bool X86InstructionSelector::selectLoadStoreOp(MachineInstr &I,
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MachineRegisterInfo &MRI,
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MachineFunction &MF) const {
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unsigned Opc = I.getOpcode();
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if (Opc != TargetOpcode::G_STORE && Opc != TargetOpcode::G_LOAD)
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return false;
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const unsigned DefReg = I.getOperand(0).getReg();
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LLT Ty = MRI.getType(DefReg);
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const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI);
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auto &MemOp = **I.memoperands_begin();
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unsigned NewOpc = getLoadStoreOp(Ty, RB, Opc, MemOp.getAlignment());
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if (NewOpc == Opc)
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return false;
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I.setDesc(TII.get(NewOpc));
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MachineInstrBuilder MIB(MF, I);
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if (Opc == TargetOpcode::G_LOAD)
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addOffset(MIB, 0);
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else {
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// G_STORE (VAL, Addr), X86Store instruction (Addr, VAL)
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I.RemoveOperand(0);
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addOffset(MIB, 0).addUse(DefReg);
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}
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return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
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}
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bool X86InstructionSelector::selectFrameIndexOrGep(MachineInstr &I,
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MachineRegisterInfo &MRI,
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MachineFunction &MF) const {
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unsigned Opc = I.getOpcode();
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if (Opc != TargetOpcode::G_FRAME_INDEX && Opc != TargetOpcode::G_GEP)
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return false;
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const unsigned DefReg = I.getOperand(0).getReg();
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LLT Ty = MRI.getType(DefReg);
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// Use LEA to calculate frame index and GEP
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unsigned NewOpc;
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if (Ty == LLT::pointer(0, 64))
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NewOpc = X86::LEA64r;
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else if (Ty == LLT::pointer(0, 32))
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NewOpc = STI.isTarget64BitILP32() ? X86::LEA64_32r : X86::LEA32r;
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else
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llvm_unreachable("Can't select G_FRAME_INDEX/G_GEP, unsupported type.");
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I.setDesc(TII.get(NewOpc));
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MachineInstrBuilder MIB(MF, I);
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if (Opc == TargetOpcode::G_FRAME_INDEX) {
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addOffset(MIB, 0);
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} else {
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MachineOperand &InxOp = I.getOperand(2);
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I.addOperand(InxOp); // set IndexReg
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InxOp.ChangeToImmediate(1); // set Scale
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MIB.addImm(0).addReg(0);
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}
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return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
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}
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bool X86InstructionSelector::selectConstant(MachineInstr &I,
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MachineRegisterInfo &MRI,
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MachineFunction &MF) const {
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if (I.getOpcode() != TargetOpcode::G_CONSTANT)
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return false;
|
|
|
|
const unsigned DefReg = I.getOperand(0).getReg();
|
|
LLT Ty = MRI.getType(DefReg);
|
|
|
|
assert(Ty.isScalar() && "invalid element type.");
|
|
|
|
uint64_t Val = 0;
|
|
if (I.getOperand(1).isCImm()) {
|
|
Val = I.getOperand(1).getCImm()->getZExtValue();
|
|
I.getOperand(1).ChangeToImmediate(Val);
|
|
} else if (I.getOperand(1).isImm()) {
|
|
Val = I.getOperand(1).getImm();
|
|
} else
|
|
llvm_unreachable("Unsupported operand type.");
|
|
|
|
unsigned NewOpc;
|
|
switch (Ty.getSizeInBits()) {
|
|
case 8:
|
|
NewOpc = X86::MOV8ri;
|
|
break;
|
|
case 16:
|
|
NewOpc = X86::MOV16ri;
|
|
break;
|
|
case 32:
|
|
NewOpc = X86::MOV32ri;
|
|
break;
|
|
case 64: {
|
|
// TODO: in case isUInt<32>(Val), X86::MOV32ri can be used
|
|
if (isInt<32>(Val))
|
|
NewOpc = X86::MOV64ri32;
|
|
else
|
|
NewOpc = X86::MOV64ri;
|
|
break;
|
|
}
|
|
default:
|
|
llvm_unreachable("Can't select G_CONSTANT, unsupported type.");
|
|
}
|
|
|
|
I.setDesc(TII.get(NewOpc));
|
|
return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
|
|
}
|
|
|
|
bool X86InstructionSelector::selectTrunc(MachineInstr &I,
|
|
MachineRegisterInfo &MRI,
|
|
MachineFunction &MF) const {
|
|
if (I.getOpcode() != TargetOpcode::G_TRUNC)
|
|
return false;
|
|
|
|
const unsigned DstReg = I.getOperand(0).getReg();
|
|
const unsigned SrcReg = I.getOperand(1).getReg();
|
|
|
|
const LLT DstTy = MRI.getType(DstReg);
|
|
const LLT SrcTy = MRI.getType(SrcReg);
|
|
|
|
const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI);
|
|
const RegisterBank &SrcRB = *RBI.getRegBank(SrcReg, MRI, TRI);
|
|
|
|
if (DstRB.getID() != SrcRB.getID()) {
|
|
DEBUG(dbgs() << "G_TRUNC input/output on different banks\n");
|
|
return false;
|
|
}
|
|
|
|
if (DstRB.getID() != X86::GPRRegBankID)
|
|
return false;
|
|
|
|
const TargetRegisterClass *DstRC = getRegClassForTypeOnBank(DstTy, DstRB);
|
|
if (!DstRC)
|
|
return false;
|
|
|
|
const TargetRegisterClass *SrcRC = getRegClassForTypeOnBank(SrcTy, SrcRB);
|
|
if (!SrcRC)
|
|
return false;
|
|
|
|
if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI) ||
|
|
!RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) {
|
|
DEBUG(dbgs() << "Failed to constrain G_TRUNC\n");
|
|
return false;
|
|
}
|
|
|
|
if (DstRC == SrcRC) {
|
|
// Nothing to be done
|
|
} else if (DstRC == &X86::GR32RegClass) {
|
|
I.getOperand(1).setSubReg(X86::sub_32bit);
|
|
} else if (DstRC == &X86::GR16RegClass) {
|
|
I.getOperand(1).setSubReg(X86::sub_16bit);
|
|
} else if (DstRC == &X86::GR8RegClass) {
|
|
I.getOperand(1).setSubReg(X86::sub_8bit);
|
|
} else {
|
|
return false;
|
|
}
|
|
|
|
I.setDesc(TII.get(X86::COPY));
|
|
return true;
|
|
}
|
|
|
|
InstructionSelector *
|
|
llvm::createX86InstructionSelector(const X86TargetMachine &TM,
|
|
X86Subtarget &Subtarget,
|
|
X86RegisterBankInfo &RBI) {
|
|
return new X86InstructionSelector(TM, Subtarget, RBI);
|
|
}
|