532 lines
22 KiB
TableGen
532 lines
22 KiB
TableGen
//===- X86RegisterInfo.td - Describe the X86 Register File --*- tablegen -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the X86 Register file, defining the registers themselves,
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// aliases between the registers, and the register classes built out of the
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// registers.
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//
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//===----------------------------------------------------------------------===//
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class X86Reg<string n, bits<16> Enc, list<Register> subregs = []> : Register<n> {
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let Namespace = "X86";
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let HWEncoding = Enc;
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let SubRegs = subregs;
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}
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// Subregister indices.
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let Namespace = "X86" in {
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def sub_8bit : SubRegIndex<8>;
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def sub_8bit_hi : SubRegIndex<8, 8>;
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def sub_16bit : SubRegIndex<16>;
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def sub_32bit : SubRegIndex<32>;
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def sub_xmm : SubRegIndex<128>;
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def sub_ymm : SubRegIndex<256>;
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}
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//===----------------------------------------------------------------------===//
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// Register definitions...
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//
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// In the register alias definitions below, we define which registers alias
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// which others. We only specify which registers the small registers alias,
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// because the register file generator is smart enough to figure out that
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// AL aliases AX if we tell it that AX aliased AL (for example).
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// Dwarf numbering is different for 32-bit and 64-bit, and there are
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// variations by target as well. Currently the first entry is for X86-64,
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// second - for EH on X86-32/Darwin and third is 'generic' one (X86-32/Linux
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// and debug information on X86-32/Darwin)
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// 8-bit registers
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// Low registers
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def AL : X86Reg<"al", 0>;
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def DL : X86Reg<"dl", 2>;
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def CL : X86Reg<"cl", 1>;
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def BL : X86Reg<"bl", 3>;
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// High registers. On x86-64, these cannot be used in any instruction
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// with a REX prefix.
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def AH : X86Reg<"ah", 4>;
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def DH : X86Reg<"dh", 6>;
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def CH : X86Reg<"ch", 5>;
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def BH : X86Reg<"bh", 7>;
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// X86-64 only, requires REX.
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let CostPerUse = 1 in {
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def SIL : X86Reg<"sil", 6>;
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def DIL : X86Reg<"dil", 7>;
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def BPL : X86Reg<"bpl", 5>;
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def SPL : X86Reg<"spl", 4>;
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def R8B : X86Reg<"r8b", 8>;
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def R9B : X86Reg<"r9b", 9>;
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def R10B : X86Reg<"r10b", 10>;
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def R11B : X86Reg<"r11b", 11>;
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def R12B : X86Reg<"r12b", 12>;
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def R13B : X86Reg<"r13b", 13>;
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def R14B : X86Reg<"r14b", 14>;
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def R15B : X86Reg<"r15b", 15>;
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}
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// 16-bit registers
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let SubRegIndices = [sub_8bit, sub_8bit_hi], CoveredBySubRegs = 1 in {
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def AX : X86Reg<"ax", 0, [AL,AH]>;
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def DX : X86Reg<"dx", 2, [DL,DH]>;
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def CX : X86Reg<"cx", 1, [CL,CH]>;
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def BX : X86Reg<"bx", 3, [BL,BH]>;
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}
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let SubRegIndices = [sub_8bit] in {
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def SI : X86Reg<"si", 6, [SIL]>;
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def DI : X86Reg<"di", 7, [DIL]>;
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def BP : X86Reg<"bp", 5, [BPL]>;
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def SP : X86Reg<"sp", 4, [SPL]>;
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}
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def IP : X86Reg<"ip", 0>;
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// X86-64 only, requires REX.
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let SubRegIndices = [sub_8bit], CostPerUse = 1 in {
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def R8W : X86Reg<"r8w", 8, [R8B]>;
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def R9W : X86Reg<"r9w", 9, [R9B]>;
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def R10W : X86Reg<"r10w", 10, [R10B]>;
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def R11W : X86Reg<"r11w", 11, [R11B]>;
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def R12W : X86Reg<"r12w", 12, [R12B]>;
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def R13W : X86Reg<"r13w", 13, [R13B]>;
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def R14W : X86Reg<"r14w", 14, [R14B]>;
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def R15W : X86Reg<"r15w", 15, [R15B]>;
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}
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// 32-bit registers
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let SubRegIndices = [sub_16bit] in {
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def EAX : X86Reg<"eax", 0, [AX]>, DwarfRegNum<[-2, 0, 0]>;
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def EDX : X86Reg<"edx", 2, [DX]>, DwarfRegNum<[-2, 2, 2]>;
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def ECX : X86Reg<"ecx", 1, [CX]>, DwarfRegNum<[-2, 1, 1]>;
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def EBX : X86Reg<"ebx", 3, [BX]>, DwarfRegNum<[-2, 3, 3]>;
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def ESI : X86Reg<"esi", 6, [SI]>, DwarfRegNum<[-2, 6, 6]>;
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def EDI : X86Reg<"edi", 7, [DI]>, DwarfRegNum<[-2, 7, 7]>;
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def EBP : X86Reg<"ebp", 5, [BP]>, DwarfRegNum<[-2, 4, 5]>;
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def ESP : X86Reg<"esp", 4, [SP]>, DwarfRegNum<[-2, 5, 4]>;
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def EIP : X86Reg<"eip", 0, [IP]>, DwarfRegNum<[-2, 8, 8]>;
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// X86-64 only, requires REX
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let CostPerUse = 1 in {
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def R8D : X86Reg<"r8d", 8, [R8W]>;
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def R9D : X86Reg<"r9d", 9, [R9W]>;
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def R10D : X86Reg<"r10d", 10, [R10W]>;
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def R11D : X86Reg<"r11d", 11, [R11W]>;
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def R12D : X86Reg<"r12d", 12, [R12W]>;
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def R13D : X86Reg<"r13d", 13, [R13W]>;
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def R14D : X86Reg<"r14d", 14, [R14W]>;
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def R15D : X86Reg<"r15d", 15, [R15W]>;
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}}
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// 64-bit registers, X86-64 only
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let SubRegIndices = [sub_32bit] in {
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def RAX : X86Reg<"rax", 0, [EAX]>, DwarfRegNum<[0, -2, -2]>;
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def RDX : X86Reg<"rdx", 2, [EDX]>, DwarfRegNum<[1, -2, -2]>;
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def RCX : X86Reg<"rcx", 1, [ECX]>, DwarfRegNum<[2, -2, -2]>;
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def RBX : X86Reg<"rbx", 3, [EBX]>, DwarfRegNum<[3, -2, -2]>;
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def RSI : X86Reg<"rsi", 6, [ESI]>, DwarfRegNum<[4, -2, -2]>;
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def RDI : X86Reg<"rdi", 7, [EDI]>, DwarfRegNum<[5, -2, -2]>;
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def RBP : X86Reg<"rbp", 5, [EBP]>, DwarfRegNum<[6, -2, -2]>;
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def RSP : X86Reg<"rsp", 4, [ESP]>, DwarfRegNum<[7, -2, -2]>;
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// These also require REX.
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let CostPerUse = 1 in {
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def R8 : X86Reg<"r8", 8, [R8D]>, DwarfRegNum<[ 8, -2, -2]>;
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def R9 : X86Reg<"r9", 9, [R9D]>, DwarfRegNum<[ 9, -2, -2]>;
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def R10 : X86Reg<"r10", 10, [R10D]>, DwarfRegNum<[10, -2, -2]>;
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def R11 : X86Reg<"r11", 11, [R11D]>, DwarfRegNum<[11, -2, -2]>;
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def R12 : X86Reg<"r12", 12, [R12D]>, DwarfRegNum<[12, -2, -2]>;
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def R13 : X86Reg<"r13", 13, [R13D]>, DwarfRegNum<[13, -2, -2]>;
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def R14 : X86Reg<"r14", 14, [R14D]>, DwarfRegNum<[14, -2, -2]>;
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def R15 : X86Reg<"r15", 15, [R15D]>, DwarfRegNum<[15, -2, -2]>;
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def RIP : X86Reg<"rip", 0, [EIP]>, DwarfRegNum<[16, -2, -2]>;
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}}
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// MMX Registers. These are actually aliased to ST0 .. ST7
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def MM0 : X86Reg<"mm0", 0>, DwarfRegNum<[41, 29, 29]>;
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def MM1 : X86Reg<"mm1", 1>, DwarfRegNum<[42, 30, 30]>;
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def MM2 : X86Reg<"mm2", 2>, DwarfRegNum<[43, 31, 31]>;
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def MM3 : X86Reg<"mm3", 3>, DwarfRegNum<[44, 32, 32]>;
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def MM4 : X86Reg<"mm4", 4>, DwarfRegNum<[45, 33, 33]>;
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def MM5 : X86Reg<"mm5", 5>, DwarfRegNum<[46, 34, 34]>;
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def MM6 : X86Reg<"mm6", 6>, DwarfRegNum<[47, 35, 35]>;
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def MM7 : X86Reg<"mm7", 7>, DwarfRegNum<[48, 36, 36]>;
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// Pseudo Floating Point registers
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def FP0 : X86Reg<"fp0", 0>;
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def FP1 : X86Reg<"fp1", 0>;
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def FP2 : X86Reg<"fp2", 0>;
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def FP3 : X86Reg<"fp3", 0>;
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def FP4 : X86Reg<"fp4", 0>;
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def FP5 : X86Reg<"fp5", 0>;
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def FP6 : X86Reg<"fp6", 0>;
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def FP7 : X86Reg<"fp7", 0>;
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// XMM Registers, used by the various SSE instruction set extensions.
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def XMM0: X86Reg<"xmm0", 0>, DwarfRegNum<[17, 21, 21]>;
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def XMM1: X86Reg<"xmm1", 1>, DwarfRegNum<[18, 22, 22]>;
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def XMM2: X86Reg<"xmm2", 2>, DwarfRegNum<[19, 23, 23]>;
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def XMM3: X86Reg<"xmm3", 3>, DwarfRegNum<[20, 24, 24]>;
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def XMM4: X86Reg<"xmm4", 4>, DwarfRegNum<[21, 25, 25]>;
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def XMM5: X86Reg<"xmm5", 5>, DwarfRegNum<[22, 26, 26]>;
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def XMM6: X86Reg<"xmm6", 6>, DwarfRegNum<[23, 27, 27]>;
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def XMM7: X86Reg<"xmm7", 7>, DwarfRegNum<[24, 28, 28]>;
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// X86-64 only
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let CostPerUse = 1 in {
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def XMM8: X86Reg<"xmm8", 8>, DwarfRegNum<[25, -2, -2]>;
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def XMM9: X86Reg<"xmm9", 9>, DwarfRegNum<[26, -2, -2]>;
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def XMM10: X86Reg<"xmm10", 10>, DwarfRegNum<[27, -2, -2]>;
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def XMM11: X86Reg<"xmm11", 11>, DwarfRegNum<[28, -2, -2]>;
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def XMM12: X86Reg<"xmm12", 12>, DwarfRegNum<[29, -2, -2]>;
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def XMM13: X86Reg<"xmm13", 13>, DwarfRegNum<[30, -2, -2]>;
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def XMM14: X86Reg<"xmm14", 14>, DwarfRegNum<[31, -2, -2]>;
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def XMM15: X86Reg<"xmm15", 15>, DwarfRegNum<[32, -2, -2]>;
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def XMM16: X86Reg<"xmm16", 16>, DwarfRegNum<[67, -2, -2]>;
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def XMM17: X86Reg<"xmm17", 17>, DwarfRegNum<[68, -2, -2]>;
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def XMM18: X86Reg<"xmm18", 18>, DwarfRegNum<[69, -2, -2]>;
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def XMM19: X86Reg<"xmm19", 19>, DwarfRegNum<[70, -2, -2]>;
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def XMM20: X86Reg<"xmm20", 20>, DwarfRegNum<[71, -2, -2]>;
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def XMM21: X86Reg<"xmm21", 21>, DwarfRegNum<[72, -2, -2]>;
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def XMM22: X86Reg<"xmm22", 22>, DwarfRegNum<[73, -2, -2]>;
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def XMM23: X86Reg<"xmm23", 23>, DwarfRegNum<[74, -2, -2]>;
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def XMM24: X86Reg<"xmm24", 24>, DwarfRegNum<[75, -2, -2]>;
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def XMM25: X86Reg<"xmm25", 25>, DwarfRegNum<[76, -2, -2]>;
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def XMM26: X86Reg<"xmm26", 26>, DwarfRegNum<[77, -2, -2]>;
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def XMM27: X86Reg<"xmm27", 27>, DwarfRegNum<[78, -2, -2]>;
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def XMM28: X86Reg<"xmm28", 28>, DwarfRegNum<[79, -2, -2]>;
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def XMM29: X86Reg<"xmm29", 29>, DwarfRegNum<[80, -2, -2]>;
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def XMM30: X86Reg<"xmm30", 30>, DwarfRegNum<[81, -2, -2]>;
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def XMM31: X86Reg<"xmm31", 31>, DwarfRegNum<[82, -2, -2]>;
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} // CostPerUse
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// YMM0-15 registers, used by AVX instructions and
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// YMM16-31 registers, used by AVX-512 instructions.
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let SubRegIndices = [sub_xmm] in {
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foreach Index = 0-31 in {
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def YMM#Index : X86Reg<"ymm"#Index, Index, [!cast<X86Reg>("XMM"#Index)]>,
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DwarfRegAlias<!cast<X86Reg>("XMM"#Index)>;
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}
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}
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// ZMM Registers, used by AVX-512 instructions.
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let SubRegIndices = [sub_ymm] in {
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foreach Index = 0-31 in {
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def ZMM#Index : X86Reg<"zmm"#Index, Index, [!cast<X86Reg>("YMM"#Index)]>,
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DwarfRegAlias<!cast<X86Reg>("XMM"#Index)>;
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}
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}
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// Mask Registers, used by AVX-512 instructions.
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def K0 : X86Reg<"k0", 0>, DwarfRegNum<[118, 93, 93]>;
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def K1 : X86Reg<"k1", 1>, DwarfRegNum<[119, 94, 94]>;
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def K2 : X86Reg<"k2", 2>, DwarfRegNum<[120, 95, 95]>;
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def K3 : X86Reg<"k3", 3>, DwarfRegNum<[121, 96, 96]>;
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def K4 : X86Reg<"k4", 4>, DwarfRegNum<[122, 97, 97]>;
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def K5 : X86Reg<"k5", 5>, DwarfRegNum<[123, 98, 98]>;
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def K6 : X86Reg<"k6", 6>, DwarfRegNum<[124, 99, 99]>;
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def K7 : X86Reg<"k7", 7>, DwarfRegNum<[125, 100, 100]>;
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// Floating point stack registers. These don't map one-to-one to the FP
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// pseudo registers, but we still mark them as aliasing FP registers. That
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// way both kinds can be live without exceeding the stack depth. ST registers
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// are only live around inline assembly.
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def ST0 : X86Reg<"st(0)", 0>, DwarfRegNum<[33, 12, 11]>;
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def ST1 : X86Reg<"st(1)", 1>, DwarfRegNum<[34, 13, 12]>;
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def ST2 : X86Reg<"st(2)", 2>, DwarfRegNum<[35, 14, 13]>;
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def ST3 : X86Reg<"st(3)", 3>, DwarfRegNum<[36, 15, 14]>;
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def ST4 : X86Reg<"st(4)", 4>, DwarfRegNum<[37, 16, 15]>;
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def ST5 : X86Reg<"st(5)", 5>, DwarfRegNum<[38, 17, 16]>;
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def ST6 : X86Reg<"st(6)", 6>, DwarfRegNum<[39, 18, 17]>;
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def ST7 : X86Reg<"st(7)", 7>, DwarfRegNum<[40, 19, 18]>;
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// Floating-point status word
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def FPSW : X86Reg<"fpsw", 0>;
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// Status flags register
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def EFLAGS : X86Reg<"flags", 0>;
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// Segment registers
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def CS : X86Reg<"cs", 1>;
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def DS : X86Reg<"ds", 3>;
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def SS : X86Reg<"ss", 2>;
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def ES : X86Reg<"es", 0>;
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def FS : X86Reg<"fs", 4>;
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def GS : X86Reg<"gs", 5>;
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// Debug registers
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def DR0 : X86Reg<"dr0", 0>;
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def DR1 : X86Reg<"dr1", 1>;
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def DR2 : X86Reg<"dr2", 2>;
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def DR3 : X86Reg<"dr3", 3>;
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def DR4 : X86Reg<"dr4", 4>;
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def DR5 : X86Reg<"dr5", 5>;
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def DR6 : X86Reg<"dr6", 6>;
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def DR7 : X86Reg<"dr7", 7>;
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def DR8 : X86Reg<"dr8", 8>;
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def DR9 : X86Reg<"dr9", 9>;
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def DR10 : X86Reg<"dr10", 10>;
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def DR11 : X86Reg<"dr11", 11>;
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def DR12 : X86Reg<"dr12", 12>;
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def DR13 : X86Reg<"dr13", 13>;
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def DR14 : X86Reg<"dr14", 14>;
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def DR15 : X86Reg<"dr15", 15>;
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// Control registers
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def CR0 : X86Reg<"cr0", 0>;
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def CR1 : X86Reg<"cr1", 1>;
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def CR2 : X86Reg<"cr2", 2>;
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def CR3 : X86Reg<"cr3", 3>;
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def CR4 : X86Reg<"cr4", 4>;
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def CR5 : X86Reg<"cr5", 5>;
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def CR6 : X86Reg<"cr6", 6>;
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def CR7 : X86Reg<"cr7", 7>;
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def CR8 : X86Reg<"cr8", 8>;
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def CR9 : X86Reg<"cr9", 9>;
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def CR10 : X86Reg<"cr10", 10>;
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def CR11 : X86Reg<"cr11", 11>;
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def CR12 : X86Reg<"cr12", 12>;
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def CR13 : X86Reg<"cr13", 13>;
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def CR14 : X86Reg<"cr14", 14>;
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def CR15 : X86Reg<"cr15", 15>;
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// Pseudo index registers
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def EIZ : X86Reg<"eiz", 4>;
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def RIZ : X86Reg<"riz", 4>;
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// Bound registers, used in MPX instructions
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def BND0 : X86Reg<"bnd0", 0>;
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def BND1 : X86Reg<"bnd1", 1>;
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def BND2 : X86Reg<"bnd2", 2>;
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def BND3 : X86Reg<"bnd3", 3>;
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//===----------------------------------------------------------------------===//
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// Register Class Definitions... now that we have all of the pieces, define the
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// top-level register classes. The order specified in the register list is
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// implicitly defined to be the register allocation order.
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//
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// List call-clobbered registers before callee-save registers. RBX, RBP, (and
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// R12, R13, R14, and R15 for X86-64) are callee-save registers.
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// In 64-mode, there are 12 additional i8 registers, SIL, DIL, BPL, SPL, and
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// R8B, ... R15B.
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// Allocate R12 and R13 last, as these require an extra byte when
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// encoded in x86_64 instructions.
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// FIXME: Allow AH, CH, DH, BH to be used as general-purpose registers in
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// 64-bit mode. The main complication is that they cannot be encoded in an
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// instruction requiring a REX prefix, while SIL, DIL, BPL, R8D, etc.
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// require a REX prefix. For example, "addb %ah, %dil" and "movzbl %ah, %r8d"
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// cannot be encoded.
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def GR8 : RegisterClass<"X86", [i8], 8,
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(add AL, CL, DL, AH, CH, DH, BL, BH, SIL, DIL, BPL, SPL,
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R8B, R9B, R10B, R11B, R14B, R15B, R12B, R13B)> {
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let AltOrders = [(sub GR8, AH, BH, CH, DH)];
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let AltOrderSelect = [{
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return MF.getSubtarget<X86Subtarget>().is64Bit();
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}];
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}
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def GR16 : RegisterClass<"X86", [i16], 16,
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(add AX, CX, DX, SI, DI, BX, BP, SP,
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R8W, R9W, R10W, R11W, R14W, R15W, R12W, R13W)>;
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def GR32 : RegisterClass<"X86", [i32], 32,
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(add EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP,
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R8D, R9D, R10D, R11D, R14D, R15D, R12D, R13D)>;
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// GR64 - 64-bit GPRs. This oddly includes RIP, which isn't accurate, since
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// RIP isn't really a register and it can't be used anywhere except in an
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// address, but it doesn't cause trouble.
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// FIXME: it *does* cause trouble - CheckBaseRegAndIndexReg() has extra
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// tests because of the inclusion of RIP in this register class.
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def GR64 : RegisterClass<"X86", [i64], 64,
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(add RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
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RBX, R14, R15, R12, R13, RBP, RSP, RIP)>;
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// Segment registers for use by MOV instructions (and others) that have a
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// segment register as one operand. Always contain a 16-bit segment
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// descriptor.
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def SEGMENT_REG : RegisterClass<"X86", [i16], 16, (add CS, DS, SS, ES, FS, GS)>;
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// Debug registers.
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def DEBUG_REG : RegisterClass<"X86", [i32], 32, (sequence "DR%u", 0, 7)>;
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// Control registers.
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def CONTROL_REG : RegisterClass<"X86", [i64], 64, (sequence "CR%u", 0, 15)>;
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// GR8_ABCD_L, GR8_ABCD_H, GR16_ABCD, GR32_ABCD, GR64_ABCD - Subclasses of
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// GR8, GR16, GR32, and GR64 which contain just the "a" "b", "c", and "d"
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// registers. On x86-32, GR16_ABCD and GR32_ABCD are classes for registers
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// that support 8-bit subreg operations. On x86-64, GR16_ABCD, GR32_ABCD,
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// and GR64_ABCD are classes for registers that support 8-bit h-register
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// operations.
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def GR8_ABCD_L : RegisterClass<"X86", [i8], 8, (add AL, CL, DL, BL)>;
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def GR8_ABCD_H : RegisterClass<"X86", [i8], 8, (add AH, CH, DH, BH)>;
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def GR16_ABCD : RegisterClass<"X86", [i16], 16, (add AX, CX, DX, BX)>;
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def GR32_ABCD : RegisterClass<"X86", [i32], 32, (add EAX, ECX, EDX, EBX)>;
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def GR64_ABCD : RegisterClass<"X86", [i64], 64, (add RAX, RCX, RDX, RBX)>;
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def GR32_TC : RegisterClass<"X86", [i32], 32, (add EAX, ECX, EDX)>;
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def GR64_TC : RegisterClass<"X86", [i64], 64, (add RAX, RCX, RDX, RSI, RDI,
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R8, R9, R11, RIP)>;
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def GR64_TCW64 : RegisterClass<"X86", [i64], 64, (add RAX, RCX, RDX,
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R8, R9, R10, R11, RIP)>;
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// GR8_NOREX - GR8 registers which do not require a REX prefix.
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def GR8_NOREX : RegisterClass<"X86", [i8], 8,
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(add AL, CL, DL, AH, CH, DH, BL, BH)> {
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let AltOrders = [(sub GR8_NOREX, AH, BH, CH, DH)];
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let AltOrderSelect = [{
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return MF.getSubtarget<X86Subtarget>().is64Bit();
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}];
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}
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// GR16_NOREX - GR16 registers which do not require a REX prefix.
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def GR16_NOREX : RegisterClass<"X86", [i16], 16,
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(add AX, CX, DX, SI, DI, BX, BP, SP)>;
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// GR32_NOREX - GR32 registers which do not require a REX prefix.
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def GR32_NOREX : RegisterClass<"X86", [i32], 32,
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(add EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP)>;
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// GR64_NOREX - GR64 registers which do not require a REX prefix.
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def GR64_NOREX : RegisterClass<"X86", [i64], 64,
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(add RAX, RCX, RDX, RSI, RDI, RBX, RBP, RSP, RIP)>;
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// GR32_NOAX - GR32 registers except EAX. Used by AddRegFrm of XCHG32 in 64-bit
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// mode to prevent encoding using the 0x90 NOP encoding. xchg %eax, %eax needs
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// to clear upper 32-bits of RAX so is not a NOP.
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def GR32_NOAX : RegisterClass<"X86", [i32], 32, (sub GR32, EAX)>;
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// GR32_NOSP - GR32 registers except ESP.
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def GR32_NOSP : RegisterClass<"X86", [i32], 32, (sub GR32, ESP)>;
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// GR64_NOSP - GR64 registers except RSP (and RIP).
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def GR64_NOSP : RegisterClass<"X86", [i64], 64, (sub GR64, RSP, RIP)>;
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// GR32_NOREX_NOSP - GR32 registers which do not require a REX prefix except
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// ESP.
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def GR32_NOREX_NOSP : RegisterClass<"X86", [i32], 32,
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(and GR32_NOREX, GR32_NOSP)>;
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// GR64_NOREX_NOSP - GR64_NOREX registers except RSP.
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def GR64_NOREX_NOSP : RegisterClass<"X86", [i64], 64,
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(and GR64_NOREX, GR64_NOSP)>;
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// Register classes used for ABIs that use 32-bit address accesses,
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// while using the whole x84_64 ISA.
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// In such cases, it is fine to use RIP as we are sure the 32 high
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// bits are not set. We do not need variants for NOSP as RIP is not
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// allowed there.
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// RIP is not spilled anywhere for now, so stick to 32-bit alignment
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// to save on memory space.
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// FIXME: We could allow all 64bit registers, but we would need
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// something to check that the 32 high bits are not set,
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// which we do not have right now.
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def LOW32_ADDR_ACCESS : RegisterClass<"X86", [i32], 32, (add GR32, RIP)>;
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// When RBP is used as a base pointer in a 32-bit addresses environement,
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// this is also safe to use the full register to access addresses.
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// Since RBP will never be spilled, stick to a 32 alignment to save
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// on memory consumption.
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def LOW32_ADDR_ACCESS_RBP : RegisterClass<"X86", [i32], 32,
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(add LOW32_ADDR_ACCESS, RBP)>;
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// A class to support the 'A' assembler constraint: [ER]AX then [ER]DX.
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def GR32_AD : RegisterClass<"X86", [i32], 32, (add EAX, EDX)>;
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def GR64_AD : RegisterClass<"X86", [i64], 64, (add RAX, RDX)>;
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// Scalar SSE2 floating point registers.
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def FR32 : RegisterClass<"X86", [f32], 32, (sequence "XMM%u", 0, 15)>;
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def FR64 : RegisterClass<"X86", [f64], 64, (add FR32)>;
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def FR128 : RegisterClass<"X86", [i128, f128], 128, (add FR32)>;
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// FIXME: This sets up the floating point register files as though they are f64
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// values, though they really are f80 values. This will cause us to spill
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// values as 64-bit quantities instead of 80-bit quantities, which is much much
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// faster on common hardware. In reality, this should be controlled by a
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// command line option or something.
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def RFP32 : RegisterClass<"X86",[f32], 32, (sequence "FP%u", 0, 6)>;
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def RFP64 : RegisterClass<"X86",[f64], 32, (add RFP32)>;
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def RFP80 : RegisterClass<"X86",[f80], 32, (add RFP32)>;
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// Floating point stack registers (these are not allocatable by the
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// register allocator - the floating point stackifier is responsible
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// for transforming FPn allocations to STn registers)
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def RST : RegisterClass<"X86", [f80, f64, f32], 32, (sequence "ST%u", 0, 7)> {
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let isAllocatable = 0;
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}
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// Generic vector registers: VR64 and VR128.
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// Ensure that float types are declared first - only float is legal on SSE1.
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def VR64: RegisterClass<"X86", [x86mmx], 64, (sequence "MM%u", 0, 7)>;
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def VR128 : RegisterClass<"X86", [v4f32, v2f64, v16i8, v8i16, v4i32, v2i64],
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128, (add FR32)>;
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def VR256 : RegisterClass<"X86", [v8f32, v4f64, v32i8, v16i16, v8i32, v4i64],
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256, (sequence "YMM%u", 0, 15)>;
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// Special classes that help the assembly parser choose some alternate
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// instructions to favor 2-byte VEX encodings.
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def VR128L : RegisterClass<"X86", [v4f32, v2f64, v16i8, v8i16, v4i32, v2i64],
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128, (sequence "XMM%u", 0, 7)>;
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def VR128H : RegisterClass<"X86", [v4f32, v2f64, v16i8, v8i16, v4i32, v2i64],
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128, (sequence "XMM%u", 8, 15)>;
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def VR256L : RegisterClass<"X86", [v8f32, v4f64, v32i8, v16i16, v8i32, v4i64],
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256, (sequence "YMM%u", 0, 7)>;
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def VR256H : RegisterClass<"X86", [v8f32, v4f64, v32i8, v16i16, v8i32, v4i64],
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256, (sequence "YMM%u", 8, 15)>;
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// Status flags registers.
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def CCR : RegisterClass<"X86", [i32], 32, (add EFLAGS)> {
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let CopyCost = -1; // Don't allow copying of status registers.
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let isAllocatable = 0;
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}
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def FPCCR : RegisterClass<"X86", [i16], 16, (add FPSW)> {
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let CopyCost = -1; // Don't allow copying of status registers.
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let isAllocatable = 0;
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}
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// AVX-512 vector/mask registers.
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def VR512 : RegisterClass<"X86", [v16f32, v8f64, v64i8, v32i16, v16i32, v8i64],
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512, (sequence "ZMM%u", 0, 31)>;
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// Scalar AVX-512 floating point registers.
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def FR32X : RegisterClass<"X86", [f32], 32, (sequence "XMM%u", 0, 31)>;
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def FR64X : RegisterClass<"X86", [f64], 64, (add FR32X)>;
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// Extended VR128 and VR256 for AVX-512 instructions
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def VR128X : RegisterClass<"X86", [v4f32, v2f64, v16i8, v8i16, v4i32, v2i64],
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128, (add FR32X)>;
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def VR256X : RegisterClass<"X86", [v8f32, v4f64, v32i8, v16i16, v8i32, v4i64],
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256, (sequence "YMM%u", 0, 31)>;
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// Mask registers
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def VK1 : RegisterClass<"X86", [i1], 16, (sequence "K%u", 0, 7)> {let Size = 16;}
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def VK2 : RegisterClass<"X86", [v2i1], 16, (add VK1)> {let Size = 16;}
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def VK4 : RegisterClass<"X86", [v4i1], 16, (add VK2)> {let Size = 16;}
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def VK8 : RegisterClass<"X86", [v8i1], 16, (add VK4)> {let Size = 16;}
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def VK16 : RegisterClass<"X86", [v16i1], 16, (add VK8)> {let Size = 16;}
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def VK32 : RegisterClass<"X86", [v32i1], 32, (add VK16)> {let Size = 32;}
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def VK64 : RegisterClass<"X86", [v64i1], 64, (add VK32)> {let Size = 64;}
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def VK1WM : RegisterClass<"X86", [i1], 16, (sub VK1, K0)> {let Size = 16;}
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def VK2WM : RegisterClass<"X86", [v2i1], 16, (sub VK2, K0)> {let Size = 16;}
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def VK4WM : RegisterClass<"X86", [v4i1], 16, (sub VK4, K0)> {let Size = 16;}
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def VK8WM : RegisterClass<"X86", [v8i1], 16, (sub VK8, K0)> {let Size = 16;}
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def VK16WM : RegisterClass<"X86", [v16i1], 16, (add VK8WM)> {let Size = 16;}
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def VK32WM : RegisterClass<"X86", [v32i1], 32, (add VK16WM)> {let Size = 32;}
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def VK64WM : RegisterClass<"X86", [v64i1], 64, (add VK32WM)> {let Size = 64;}
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// Bound registers
|
|
def BNDR : RegisterClass<"X86", [v2i64], 128, (sequence "BND%u", 0, 3)>;
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