0f5830b045
Review: https://reviews.freebsd.org/D1892 Found by: neel Sponsored by: The FreeBSD Foundation MFC after: 3 days
393 lines
16 KiB
C
393 lines
16 KiB
C
/*-
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* Copyright (c) 2013-2015 The FreeBSD Foundation
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* All rights reserved.
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*
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* This software was developed by Konstantin Belousov <kib@FreeBSD.org>
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* under sponsorship from the FreeBSD Foundation.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef __X86_IOMMU_INTEL_REG_H
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#define __X86_IOMMU_INTEL_REG_H
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#define DMAR_PAGE_SIZE PAGE_SIZE
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#define DMAR_PAGE_MASK (DMAR_PAGE_SIZE - 1)
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#define DMAR_PAGE_SHIFT PAGE_SHIFT
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#define DMAR_NPTEPG (DMAR_PAGE_SIZE / sizeof(dmar_pte_t))
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#define DMAR_NPTEPGSHIFT 9
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#define DMAR_PTEMASK (DMAR_NPTEPG - 1)
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typedef struct dmar_root_entry {
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uint64_t r1;
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uint64_t r2;
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} dmar_root_entry_t;
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#define DMAR_ROOT_R1_P 1 /* Present */
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#define DMAR_ROOT_R1_CTP_MASK 0xfffffffffffff000 /* Mask for Context-Entry
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Table Pointer */
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#define DMAR_CTX_CNT (DMAR_PAGE_SIZE / sizeof(dmar_root_entry_t))
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typedef struct dmar_ctx_entry {
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uint64_t ctx1;
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uint64_t ctx2;
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} dmar_ctx_entry_t;
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#define DMAR_CTX1_P 1 /* Present */
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#define DMAR_CTX1_FPD 2 /* Fault Processing Disable */
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/* Translation Type: */
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#define DMAR_CTX1_T_UNTR 0 /* only Untranslated */
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#define DMAR_CTX1_T_TR 4 /* both Untranslated
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and Translated */
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#define DMAR_CTX1_T_PASS 8 /* Pass-Through */
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#define DMAR_CTX1_ASR_MASK 0xfffffffffffff000 /* Mask for the Address
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Space Root */
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#define DMAR_CTX2_AW_2LVL 0 /* 2-level page tables */
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#define DMAR_CTX2_AW_3LVL 1 /* 3-level page tables */
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#define DMAR_CTX2_AW_4LVL 2 /* 4-level page tables */
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#define DMAR_CTX2_AW_5LVL 3 /* 5-level page tables */
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#define DMAR_CTX2_AW_6LVL 4 /* 6-level page tables */
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#define DMAR_CTX2_DID(x) ((x) << 8) /* Domain Identifier */
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typedef struct dmar_pte {
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uint64_t pte;
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} dmar_pte_t;
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#define DMAR_PTE_R 1 /* Read */
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#define DMAR_PTE_W (1 << 1) /* Write */
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#define DMAR_PTE_SP (1 << 7) /* Super Page */
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#define DMAR_PTE_SNP (1 << 11) /* Snoop Behaviour */
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#define DMAR_PTE_ADDR_MASK 0xffffffffff000 /* Address Mask */
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#define DMAR_PTE_TM (1ULL << 62) /* Transient Mapping */
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typedef struct dmar_irte {
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uint64_t irte1;
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uint64_t irte2;
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} dmar_irte_t;
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/* Source Validation Type */
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#define DMAR_IRTE2_SVT_NONE (0ULL << (82 - 64))
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#define DMAR_IRTE2_SVT_RID (1ULL << (82 - 64))
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#define DMAR_IRTE2_SVT_BUS (2ULL << (82 - 64))
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/* Source-id Qualifier */
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#define DMAR_IRTE2_SQ_RID (0ULL << (80 - 64))
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#define DMAR_IRTE2_SQ_RID_N2 (1ULL << (80 - 64))
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#define DMAR_IRTE2_SQ_RID_N21 (2ULL << (80 - 64))
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#define DMAR_IRTE2_SQ_RID_N210 (3ULL << (80 - 64))
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/* Source Identifier */
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#define DMAR_IRTE2_SID_RID(x) ((uint64_t)(x))
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#define DMAR_IRTE2_SID_BUS(start, end) ((((uint64_t)(start)) << 8) | (end))
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/* Destination Id */
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#define DMAR_IRTE1_DST_xAPIC(x) (((uint64_t)(x)) << 40)
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#define DMAR_IRTE1_DST_x2APIC(x) (((uint64_t)(x)) << 32)
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/* Vector */
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#define DMAR_IRTE1_V(x) (((uint64_t)x) << 16)
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#define DMAR_IRTE1_IM_POSTED (1ULL << 15) /* Posted */
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/* Delivery Mode */
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#define DMAR_IRTE1_DLM_FM (0ULL << 5)
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#define DMAR_IRTE1_DLM_LP (1ULL << 5)
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#define DMAR_IRTE1_DLM_SMI (2ULL << 5)
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#define DMAR_IRTE1_DLM_NMI (4ULL << 5)
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#define DMAR_IRTE1_DLM_INIT (5ULL << 5)
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#define DMAR_IRTE1_DLM_ExtINT (7ULL << 5)
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/* Trigger Mode */
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#define DMAR_IRTE1_TM_EDGE (0ULL << 4)
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#define DMAR_IRTE1_TM_LEVEL (1ULL << 4)
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/* Redirection Hint */
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#define DMAR_IRTE1_RH_DIRECT (0ULL << 3)
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#define DMAR_IRTE1_RH_SELECT (1ULL << 3)
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/* Destination Mode */
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#define DMAR_IRTE1_DM_PHYSICAL (0ULL << 2)
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#define DMAR_IRTE1_DM_LOGICAL (1ULL << 2)
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#define DMAR_IRTE1_FPD (1ULL << 1) /* Fault Processing Disable */
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#define DMAR_IRTE1_P (1ULL) /* Present */
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/* Version register */
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#define DMAR_VER_REG 0
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#define DMAR_MAJOR_VER(x) (((x) >> 4) & 0xf)
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#define DMAR_MINOR_VER(x) ((x) & 0xf)
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/* Capabilities register */
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#define DMAR_CAP_REG 0x8
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#define DMAR_CAP_PI (1ULL << 59) /* Posted Interrupts */
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#define DMAR_CAP_FL1GP (1ULL << 56) /* First Level 1GByte Page */
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#define DMAR_CAP_DRD (1ULL << 55) /* DMA Read Draining */
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#define DMAR_CAP_DWD (1ULL << 54) /* DMA Write Draining */
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#define DMAR_CAP_MAMV(x) ((u_int)(((x) >> 48) & 0x3f))
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/* Maximum Address Mask */
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#define DMAR_CAP_NFR(x) ((u_int)(((x) >> 40) & 0xff) + 1)
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/* Num of Fault-recording regs */
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#define DMAR_CAP_PSI (1ULL << 39) /* Page Selective Invalidation */
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#define DMAR_CAP_SPS(x) ((u_int)(((x) >> 34) & 0xf)) /* Super-Page Support */
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#define DMAR_CAP_SPS_2M 0x1
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#define DMAR_CAP_SPS_1G 0x2
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#define DMAR_CAP_SPS_512G 0x4
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#define DMAR_CAP_SPS_1T 0x8
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#define DMAR_CAP_FRO(x) ((u_int)(((x) >> 24) & 0x1ff))
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/* Fault-recording reg offset */
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#define DMAR_CAP_ISOCH (1 << 23) /* Isochrony */
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#define DMAR_CAP_ZLR (1 << 22) /* Zero-length reads */
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#define DMAR_CAP_MGAW(x) ((u_int)(((x) >> 16) & 0x3f))
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/* Max Guest Address Width */
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#define DMAR_CAP_SAGAW(x) ((u_int)(((x) >> 8) & 0x1f))
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/* Adjusted Guest Address Width */
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#define DMAR_CAP_SAGAW_2LVL 0x01
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#define DMAR_CAP_SAGAW_3LVL 0x02
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#define DMAR_CAP_SAGAW_4LVL 0x04
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#define DMAR_CAP_SAGAW_5LVL 0x08
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#define DMAR_CAP_SAGAW_6LVL 0x10
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#define DMAR_CAP_CM (1 << 7) /* Caching mode */
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#define DMAR_CAP_PHMR (1 << 6) /* Protected High-mem Region */
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#define DMAR_CAP_PLMR (1 << 5) /* Protected Low-mem Region */
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#define DMAR_CAP_RWBF (1 << 4) /* Required Write-Buffer Flushing */
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#define DMAR_CAP_AFL (1 << 3) /* Advanced Fault Logging */
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#define DMAR_CAP_ND(x) ((u_int)((x) & 0x3)) /* Number of domains */
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/* Extended Capabilities register */
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#define DMAR_ECAP_REG 0x10
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#define DMAR_ECAP_PSS(x) (((x) >> 35) & 0xf) /* PASID Size Supported */
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#define DMAR_ECAP_EAFS (1ULL << 34) /* Extended Accessed Flag */
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#define DMAR_ECAP_NWFS (1ULL << 33) /* No Write Flag */
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#define DMAR_ECAP_SRS (1ULL << 31) /* Supervisor Request */
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#define DMAR_ECAP_ERS (1ULL << 30) /* Execute Request */
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#define DMAR_ECAP_PRS (1ULL << 29) /* Page Request */
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#define DMAR_ECAP_PASID (1ULL << 28) /* Process Address Space Id */
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#define DMAR_ECAP_DIS (1ULL << 27) /* Deferred Invalidate */
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#define DMAR_ECAP_NEST (1ULL << 26) /* Nested Translation */
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#define DMAR_ECAP_MTS (1ULL << 25) /* Memory Type */
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#define DMAR_ECAP_ECS (1ULL << 24) /* Extended Context */
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#define DMAR_ECAP_MHMV(x) ((u_int)(((x) >> 20) & 0xf))
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/* Maximum Handle Mask Value */
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#define DMAR_ECAP_IRO(x) ((u_int)(((x) >> 8) & 0x3ff))
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/* IOTLB Register Offset */
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#define DMAR_ECAP_SC (1 << 7) /* Snoop Control */
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#define DMAR_ECAP_PT (1 << 6) /* Pass Through */
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#define DMAR_ECAP_EIM (1 << 4) /* Extended Interrupt Mode */
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#define DMAR_ECAP_IR (1 << 3) /* Interrupt Remapping */
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#define DMAR_ECAP_DI (1 << 2) /* Device IOTLB */
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#define DMAR_ECAP_QI (1 << 1) /* Queued Invalidation */
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#define DMAR_ECAP_C (1 << 0) /* Coherency */
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/* Global Command register */
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#define DMAR_GCMD_REG 0x18
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#define DMAR_GCMD_TE (1U << 31) /* Translation Enable */
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#define DMAR_GCMD_SRTP (1 << 30) /* Set Root Table Pointer */
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#define DMAR_GCMD_SFL (1 << 29) /* Set Fault Log */
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#define DMAR_GCMD_EAFL (1 << 28) /* Enable Advanced Fault Logging */
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#define DMAR_GCMD_WBF (1 << 27) /* Write Buffer Flush */
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#define DMAR_GCMD_QIE (1 << 26) /* Queued Invalidation Enable */
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#define DMAR_GCMD_IRE (1 << 25) /* Interrupt Remapping Enable */
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#define DMAR_GCMD_SIRTP (1 << 24) /* Set Interrupt Remap Table Pointer */
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#define DMAR_GCMD_CFI (1 << 23) /* Compatibility Format Interrupt */
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/* Global Status register */
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#define DMAR_GSTS_REG 0x1c
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#define DMAR_GSTS_TES (1U << 31) /* Translation Enable Status */
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#define DMAR_GSTS_RTPS (1 << 30) /* Root Table Pointer Status */
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#define DMAR_GSTS_FLS (1 << 29) /* Fault Log Status */
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#define DMAR_GSTS_AFLS (1 << 28) /* Advanced Fault Logging Status */
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#define DMAR_GSTS_WBFS (1 << 27) /* Write Buffer Flush Status */
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#define DMAR_GSTS_QIES (1 << 26) /* Queued Invalidation Enable Status */
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#define DMAR_GSTS_IRES (1 << 25) /* Interrupt Remapping Enable Status */
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#define DMAR_GSTS_IRTPS (1 << 24) /* Interrupt Remapping Table
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Pointer Status */
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#define DMAR_GSTS_CFIS (1 << 23) /* Compatibility Format
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Interrupt Status */
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/* Root-Entry Table Address register */
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#define DMAR_RTADDR_REG 0x20
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/* Context Command register */
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#define DMAR_CCMD_REG 0x28
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#define DMAR_CCMD_ICC (1ULL << 63) /* Invalidate Context-Cache */
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#define DMAR_CCMD_ICC32 (1U << 31)
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#define DMAR_CCMD_CIRG_MASK (0x3ULL << 61) /* Context Invalidation
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Request Granularity */
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#define DMAR_CCMD_CIRG_GLOB (0x1ULL << 61) /* Global */
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#define DMAR_CCMD_CIRG_DOM (0x2ULL << 61) /* Domain */
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#define DMAR_CCMD_CIRG_DEV (0x3ULL << 61) /* Device */
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#define DMAR_CCMD_CAIG(x) (((x) >> 59) & 0x3) /* Context Actual
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Invalidation Granularity */
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#define DMAR_CCMD_CAIG_GLOB 0x1 /* Global */
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#define DMAR_CCMD_CAIG_DOM 0x2 /* Domain */
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#define DMAR_CCMD_CAIG_DEV 0x3 /* Device */
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#define DMAR_CCMD_FM (0x3UUL << 32) /* Function Mask */
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#define DMAR_CCMD_SID(x) (((x) & 0xffff) << 16) /* Source-ID */
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#define DMAR_CCMD_DID(x) ((x) & 0xffff) /* Domain-ID */
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/* Invalidate Address register */
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#define DMAR_IVA_REG_OFF 0
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#define DMAR_IVA_IH (1 << 6) /* Invalidation Hint */
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#define DMAR_IVA_AM(x) ((x) & 0x1f) /* Address Mask */
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#define DMAR_IVA_ADDR(x) ((x) & ~0xfffULL) /* Address */
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/* IOTLB Invalidate register */
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#define DMAR_IOTLB_REG_OFF 0x8
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#define DMAR_IOTLB_IVT (1ULL << 63) /* Invalidate IOTLB */
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#define DMAR_IOTLB_IVT32 (1U << 31)
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#define DMAR_IOTLB_IIRG_MASK (0x3ULL << 60) /* Invalidation Request
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Granularity */
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#define DMAR_IOTLB_IIRG_GLB (0x1ULL << 60) /* Global */
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#define DMAR_IOTLB_IIRG_DOM (0x2ULL << 60) /* Domain-selective */
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#define DMAR_IOTLB_IIRG_PAGE (0x3ULL << 60) /* Page-selective */
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#define DMAR_IOTLB_IAIG_MASK (0x3ULL << 57) /* Actual Invalidation
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Granularity */
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#define DMAR_IOTLB_IAIG_INVLD 0 /* Hw detected error */
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#define DMAR_IOTLB_IAIG_GLB (0x1ULL << 57) /* Global */
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#define DMAR_IOTLB_IAIG_DOM (0x2ULL << 57) /* Domain-selective */
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#define DMAR_IOTLB_IAIG_PAGE (0x3ULL << 57) /* Page-selective */
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#define DMAR_IOTLB_DR (0x1ULL << 49) /* Drain Reads */
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#define DMAR_IOTLB_DW (0x1ULL << 48) /* Drain Writes */
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#define DMAR_IOTLB_DID(x) (((uint64_t)(x) & 0xffff) << 32) /* Domain Id */
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/* Fault Status register */
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#define DMAR_FSTS_REG 0x34
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#define DMAR_FSTS_FRI(x) (((x) >> 8) & 0xff) /* Fault Record Index */
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#define DMAR_FSTS_ITE (1 << 6) /* Invalidation Time-out */
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#define DMAR_FSTS_ICE (1 << 5) /* Invalidation Completion */
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#define DMAR_FSTS_IQE (1 << 4) /* Invalidation Queue */
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#define DMAR_FSTS_APF (1 << 3) /* Advanced Pending Fault */
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#define DMAR_FSTS_AFO (1 << 2) /* Advanced Fault Overflow */
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#define DMAR_FSTS_PPF (1 << 1) /* Primary Pending Fault */
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#define DMAR_FSTS_PFO 1 /* Fault Overflow */
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/* Fault Event Control register */
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#define DMAR_FECTL_REG 0x38
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#define DMAR_FECTL_IM (1U << 31) /* Interrupt Mask */
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#define DMAR_FECTL_IP (1 << 30) /* Interrupt Pending */
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/* Fault Event Data register */
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#define DMAR_FEDATA_REG 0x3c
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/* Fault Event Address register */
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#define DMAR_FEADDR_REG 0x40
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/* Fault Event Upper Address register */
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#define DMAR_FEUADDR_REG 0x44
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/* Advanced Fault Log register */
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#define DMAR_AFLOG_REG 0x58
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/* Fault Recording Register, also usable for Advanced Fault Log records */
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#define DMAR_FRCD2_F (1ULL << 63) /* Fault */
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#define DMAR_FRCD2_F32 (1U << 31)
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#define DMAR_FRCD2_T(x) ((int)((x >> 62) & 1)) /* Type */
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#define DMAR_FRCD2_T_W 0 /* Write request */
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#define DMAR_FRCD2_T_R 1 /* Read or AtomicOp */
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#define DMAR_FRCD2_AT(x) ((int)((x >> 60) & 0x3)) /* Address Type */
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#define DMAR_FRCD2_FR(x) ((int)((x >> 32) & 0xff)) /* Fault Reason */
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#define DMAR_FRCD2_SID(x) ((int)(x & 0xffff)) /* Source Identifier */
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#define DMAR_FRCS1_FI_MASK 0xffffffffff000 /* Fault Info, Address Mask */
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/* Protected Memory Enable register */
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#define DMAR_PMEN_REG 0x64
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#define DMAR_PMEN_EPM (1U << 31) /* Enable Protected Memory */
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#define DMAR_PMEN_PRS 1 /* Protected Region Status */
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/* Protected Low-Memory Base register */
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#define DMAR_PLMBASE_REG 0x68
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/* Protected Low-Memory Limit register */
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#define DMAR_PLMLIMIT_REG 0x6c
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/* Protected High-Memory Base register */
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#define DMAR_PHMBASE_REG 0x70
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/* Protected High-Memory Limit register */
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#define DMAR_PHMLIMIT_REG 0x78
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/* Queued Invalidation Descriptors */
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#define DMAR_IQ_DESCR_SZ_SHIFT 4 /* Shift for descriptor count
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to ring offset */
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#define DMAR_IQ_DESCR_SZ (1 << DMAR_IQ_DESCR_SZ_SHIFT)
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/* Descriptor size */
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#define DMAR_IQ_DESCR_CTX_INV 0x1 /* Context-cache Invalidate
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Descriptor */
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#define DMAR_IQ_DESCR_CTX_GLOB (0x1 << 4) /* Granularity: Global */
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#define DMAR_IQ_DESCR_CTX_DOM (0x2 << 4) /* Granularity: Domain */
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#define DMAR_IQ_DESCR_CTX_DEV (0x3 << 4) /* Granularity: Device */
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#define DMAR_IQ_DESCR_CTX_DID(x) (((uint32_t)(x)) << 16) /* Domain Id */
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#define DMAR_IQ_DESCR_CTX_SRC(x) (((uint64_t)(x)) << 32) /* Source Id */
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#define DMAR_IQ_DESCR_CTX_FM(x) (((uint64_t)(x)) << 48) /* Function Mask */
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#define DMAR_IQ_DESCR_IOTLB_INV 0x2 /* IOTLB Invalidate Descriptor */
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#define DMAR_IQ_DESCR_IOTLB_GLOB (0x1 << 4) /* Granularity: Global */
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#define DMAR_IQ_DESCR_IOTLB_DOM (0x2 << 4) /* Granularity: Domain */
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#define DMAR_IQ_DESCR_IOTLB_PAGE (0x3 << 4) /* Granularity: Page */
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#define DMAR_IQ_DESCR_IOTLB_DW (1 << 6) /* Drain Writes */
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#define DMAR_IQ_DESCR_IOTLB_DR (1 << 7) /* Drain Reads */
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#define DMAR_IQ_DESCR_IOTLB_DID(x) (((uint32_t)(x)) << 16) /* Domain Id */
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#define DMAR_IQ_DESCR_IEC_INV 0x4 /* Invalidate Interrupt Entry Cache */
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#define DMAR_IQ_DESCR_IEC_IDX (1 << 4) /* Index-Selective Invalidation */
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#define DMAR_IQ_DESCR_IEC_IIDX(x) (((uint64_t)x) << 32) /* Interrupt Index */
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#define DMAR_IQ_DESCR_IEC_IM(x) ((x) << 27) /* Index Mask */
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#define DMAR_IQ_DESCR_WAIT_ID 0x5 /* Invalidation Wait Descriptor */
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#define DMAR_IQ_DESCR_WAIT_IF (1 << 4) /* Interrupt Flag */
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#define DMAR_IQ_DESCR_WAIT_SW (1 << 5) /* Status Write */
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#define DMAR_IQ_DESCR_WAIT_FN (1 << 6) /* Fence */
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#define DMAR_IQ_DESCR_WAIT_SD(x) (((uint64_t)(x)) << 32) /* Status Data */
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/* Invalidation Queue Head register */
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#define DMAR_IQH_REG 0x80
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#define DMAR_IQH_MASK 0x7fff0 /* Next cmd index mask */
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/* Invalidation Queue Tail register */
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#define DMAR_IQT_REG 0x88
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#define DMAR_IQT_MASK 0x7fff0
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/* Invalidation Queue Address register */
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#define DMAR_IQA_REG 0x90
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#define DMAR_IQA_IQA_MASK 0xfffffffffffff000 /* Invalidation Queue
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Base Address mask */
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#define DMAR_IQA_QS_MASK 0x7 /* Queue Size in pages */
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#define DMAR_IQA_QS_MAX 0x7 /* Max Queue size */
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#define DMAR_IQA_QS_DEF 3
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/* Invalidation Completion Status register */
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#define DMAR_ICS_REG 0x9c
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#define DMAR_ICS_IWC 1 /* Invalidation Wait
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Descriptor Complete */
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/* Invalidation Event Control register */
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#define DMAR_IECTL_REG 0xa0
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#define DMAR_IECTL_IM (1U << 31) /* Interrupt Mask */
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#define DMAR_IECTL_IP (1 << 30) /* Interrupt Pending */
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/* Invalidation Event Data register */
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#define DMAR_IEDATA_REG 0xa4
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/* Invalidation Event Address register */
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#define DMAR_IEADDR_REG 0xa8
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/* Invalidation Event Upper Address register */
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#define DMAR_IEUADDR_REG 0xac
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/* Interrupt Remapping Table Address register */
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#define DMAR_IRTA_REG 0xb8
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#define DMAR_IRTA_EIME (1 << 11) /* Extended Interrupt Mode
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Enable */
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#define DMAR_IRTA_S_MASK 0xf /* Size Mask */
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#endif
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