Neel Natu f7bb996d92 Various fixes to get the SWARM config working on a big-endian Sibyte CPU. ... Getting the little-endian PCI bus working on the big-endian CPU proved to be quite challenging. We let the PCI devices be mapped in the "match byte lanes" address window. This is where they are mapped by the CFE and DMA transfers generated to or from addresses within this window are not subject to automatic byte-swapping. However any access by the driver to memory-mapped pci space is redirected via the "match bit lanes" address window. We get the benefit of automatic byte swapping through this address window and drivers don't need to change to deal with CPU big-endianness.		2010-02-17 06:43:37 +00:00
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ata_zbbus.c
files.sibyte	With this commit our friend RMI will now compile. I have	2009-10-30 08:53:11 +00:00
sb_asm.S	Various fixes to get the SWARM config working on a big-endian Sibyte CPU.	2010-02-17 06:43:37 +00:00
sb_bus_space.h	Various fixes to get the SWARM config working on a big-endian Sibyte CPU.	2010-02-17 06:43:37 +00:00
sb_machdep.c	SMP support for the mips port.	2010-02-09 06:24:43 +00:00
sb_scd.c	SMP support for the mips port.	2010-02-09 06:24:43 +00:00
sb_scd.h	SMP support for the mips port.	2010-02-09 06:24:43 +00:00
sb_zbbus.c	SMP support for the mips port.	2010-02-09 06:24:43 +00:00
sb_zbpci.c	Various fixes to get the SWARM config working on a big-endian Sibyte CPU.	2010-02-17 06:43:37 +00:00