179f14534e
This is an import of the reworked LEDE dts files. Besides other things they make it easier for us to reuse. The only diffs left are for the following SoCs: MT7620A (fbsd-mt7620a.dtsi) MT7621 (fbsd-mt7621.dtsi) MT7628 (fbsd-mt7628an.dtsi) RT3883 (fbsd-rt3883.dtsi) So we include the fbsd-*.dtsi files at the end of the original LEDE dtsi files, using '#include "fbsd-xxxx.dtsi"'. For example, for MT7621, the LEDE dtsi file is mt7621.dtsi. At the end of it we add: #include "fbsd-mt7621.dtsi" Approved by: adrian (mentor) Obtained from: LEDE project Sponsored by: Smartcom - Bulgaria AD Differential Revision: https://reviews.freebsd.org/D6394
127 lines
1.9 KiB
Plaintext
127 lines
1.9 KiB
Plaintext
/dts-v1/;
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#include "mt7621.dtsi"
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/ {
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compatible = "mediatek,mt7621-eval-board", "mediatek,mt7621-soc";
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model = "ZBT-WG3526";
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memory@0 {
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device_type = "memory";
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reg = <0x0 0x1c000000>, <0x20000000 0x4000000>;
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};
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chosen {
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bootargs = "console=ttyS0,115200";
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};
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palmbus: palmbus@1E000000 {
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i2c@900 {
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compatible = "ralink,i2c-mt7621";
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reg = <0x900 0x100>;
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&i2c_pins>;
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status = "okay";
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};
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};
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gpio-keys-polled {
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compatible = "gpio-keys-polled";
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#address-cells = <1>;
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#size-cells = <0>;
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poll-interval = <20>;
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reset {
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label = "reset";
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gpios = <&gpio0 18 1>;
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linux,code = <0x198>;
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};
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};
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gpio-leds {
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compatible = "gpio-leds";
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status {
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label = "zbt-wg3526:green:status";
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gpios = <&gpio0 24 1>;
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};
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};
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};
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&sdhci {
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status = "okay";
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};
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&spi0 {
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status = "okay";
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m25p80@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "jedec,spi-nor";
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reg = <0 0>;
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linux,modalias = "m25p80";
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spi-max-frequency = <10000000>;
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partition@0 {
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label = "u-boot";
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reg = <0x0 0x30000>;
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read-only;
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};
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partition@30000 {
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label = "u-boot-env";
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reg = <0x30000 0x10000>;
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read-only;
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};
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factory: partition@40000 {
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label = "factory";
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reg = <0x40000 0x10000>;
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read-only;
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};
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partition@50000 {
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label = "firmware";
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reg = <0x50000 0xfb0000>;
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};
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};
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};
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&pcie {
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status = "okay";
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pcie0 {
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mt76@0,0 {
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reg = <0x0000 0 0 0 0>;
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device_type = "pci";
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mediatek,mtd-eeprom = <&factory 0x0000>;
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mediatek,5ghz = <0>;
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};
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};
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pcie1 {
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mt76@1,0 {
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reg = <0x0000 0 0 0 0>;
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device_type = "pci";
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mediatek,mtd-eeprom = <&factory 0x8000>;
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mediatek,2ghz = <0>;
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};
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};
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};
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ðernet {
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mtd-mac-address = <&factory 0xe000>;
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};
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&pinctrl {
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state_default: pinctrl0 {
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gpio {
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ralink,group = "wdt", "rgmii2", "wdt rst", "jtag", "mdio";
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ralink,function = "gpio";
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};
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};
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};
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