1130b656e5
This will make a number of things easier in the future, as well as (finally!) avoiding the Id-smashing problem which has plagued developers for so long. Boy, I'm glad we're not using sup anymore. This update would have been insane otherwise.
187 lines
4.5 KiB
ArmAsm
187 lines
4.5 KiB
ArmAsm
/*
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* Mach Operating System
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* Copyright (c) 1992, 1991 Carnegie Mellon University
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* All Rights Reserved.
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*
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* Permission to use, copy, modify and distribute this software and its
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* documentation is hereby granted, provided that both the copyright
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* notice and this permission notice appear in all copies of the
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* software, derivative works or modified versions, and any portions
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* thereof, and that both notices appear in supporting documentation.
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*
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* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
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* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
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* ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
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*
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* Carnegie Mellon requests users of this software to return to
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*
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* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
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* School of Computer Science
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* Carnegie Mellon University
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* Pittsburgh PA 15213-3890
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*
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* any improvements or extensions that they make and grant Carnegie Mellon
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* the rights to redistribute these changes.
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*
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* from: Mach, Revision 2.2 92/04/04 11:34:13 rpd
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* $FreeBSD$
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*/
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/*
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Copyright 1988, 1989, 1990, 1991, 1992
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by Intel Corporation, Santa Clara, California.
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All Rights Reserved
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Permission to use, copy, modify, and distribute this software and
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its documentation for any purpose and without fee is hereby
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granted, provided that the above copyright notice appears in all
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copies and that both the copyright notice and this permission notice
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appear in supporting documentation, and that the name of Intel
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not be used in advertising or publicity pertaining to distribution
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of the software without specific, written prior permission.
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INTEL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE
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INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS,
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IN NO EVENT SHALL INTEL BE LIABLE FOR ANY SPECIAL, INDIRECT, OR
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CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
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LOSS OF USE, DATA OR PROFITS, WHETHER IN ACTION OF CONTRACT,
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NEGLIGENCE, OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION
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WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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/*
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* LP (Laptop Package)
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*
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* Copyright (C) 1994 by HOSOKAWA, Tatsumi <hosokawa@mt.cs.keio.ac.jp>
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*
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* This software may be used, modified, copied, and distributed, in
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* both source and binary form provided that the above copyright and
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* these terms are retained. Under no circumstances is the author
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* responsible for the proper functioning of this software, nor does
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* the author assume any responsibility for damages incurred with its
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* use.
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*
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* Sep., 1994 Implemented on FreeBSD 1.1.5.1R (Toshiba AVS001WD)
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*/
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/*
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* Modified for APM BIOS initializer by HOSOKAWA Tatsumi
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*
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* See also locore.s.
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* (This file is based directly on /sys/i386/boot/biosboot/asm.S)
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*/
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.file "real_prot.S"
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#include "real_prot.h"
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#include "apm_segments.h"
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#include "apm_bios.h"
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CR0_PE_ON = 0x1
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CR0_PE_OFF = 0xfffffffe
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.text
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/*
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*
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* real_to_prot()
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* transfer from real mode to protected mode.
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*/
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ENTRY(real_to_prot)
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/* guarantee that interrupt is disabled when in prot mode */
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cli
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/*
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* deleted for APM initializer by HOSOKAWA Tatsumi
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* <hosoakwa@mt.cs.keio.ac.jp>
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*/
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#if 0
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/* load the gdtr */
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addr32
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data32
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lgdt EXT(Gdtr)
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#endif
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/* set the PE bit of CR0 */
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mov %cr0, %eax
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data32
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or $CR0_PE_ON, %eax
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mov %eax, %cr0
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/*
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* make intrasegment jump to flush the processor pipeline and
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* reload CS register
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*/
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data32
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ljmp $(APM_INIT_CS_SEL), $xprot
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xprot:
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/*
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* we are in USE32 mode now
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* set up the protected mode segment registers : DS, SS, ES
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*/
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movw $(APM_INIT_DS_SEL), %ax /* data segment */
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mov %ax, %ds /* gas would waste a prefix byte for movw */
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mov %ax, %ss
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mov %ax, %es
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/* load idtr so that we can enable interrupts */
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lidt EXT(Idtr_prot)
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ret
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/*
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*
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* prot_to_real()
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* transfer from protected mode to real mode
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*
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*/
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ENTRY(prot_to_real)
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/* Prepare %ax while we're still in a mode that gas understands. */
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movw $(APM_INIT_DS16_SEL), %ax
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/* Change to use16 mode. */
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ljmp $(APM_INIT_CS16_SEL), $x16
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x16:
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mov %ax, %ds
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mov %ax, %ss
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mov %ax, %es
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/* clear the PE bit of CR0 */
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mov %cr0, %eax
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data32
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and $CR0_PE_OFF, %eax
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mov %eax, %cr0
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/*
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* make intersegment jmp to flush the processor pipeline
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* and reload CS register
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*/
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data32
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ljmp $(APM_OURADDR>>4), $xreal
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xreal:
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/*
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* we are in real mode now
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* set up the real mode segment registers : DS, SS, ES
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*/
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mov %cs, %ax
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mov %ax, %ds
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mov %ax, %ss
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mov %ax, %es
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/* load idtr so that we can enable interrupts */
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addr32
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data32
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lidt EXT(Idtr_real)
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data32
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ret
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