0dc34160f3
mfi, mps, mpr, mvs, my, oce, pcn, ral, rl. This only labels existing pci device tables, and has no probe / attach code changes. Reviewed by: imp, chuck Submitted by: Lakhan Shiva Kamireddy <lakhanshiva@gmail.com> Sponsored by: Google, Inc. (GSoC 2018) Approved by: re (glen)
529 lines
15 KiB
C
529 lines
15 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2010 Alexander Motin <mav@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer,
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* without modification, immediately at the beginning of the file.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/module.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/bus.h>
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#include <sys/endian.h>
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#include <sys/malloc.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <vm/uma.h>
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#include <machine/stdarg.h>
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#include <machine/resource.h>
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#include <machine/bus.h>
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#include <sys/rman.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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#include "mvs.h"
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/* local prototypes */
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static int mvs_setup_interrupt(device_t dev);
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static void mvs_intr(void *data);
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static int mvs_suspend(device_t dev);
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static int mvs_resume(device_t dev);
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static int mvs_ctlr_setup(device_t dev);
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static struct {
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uint32_t id;
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uint8_t rev;
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const char *name;
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int ports;
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int quirks;
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} mvs_ids[] = {
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{0x504011ab, 0x00, "Marvell 88SX5040", 4, MVS_Q_GENI},
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{0x504111ab, 0x00, "Marvell 88SX5041", 4, MVS_Q_GENI},
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{0x508011ab, 0x00, "Marvell 88SX5080", 8, MVS_Q_GENI},
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{0x508111ab, 0x00, "Marvell 88SX5081", 8, MVS_Q_GENI},
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{0x604011ab, 0x00, "Marvell 88SX6040", 4, MVS_Q_GENII},
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{0x604111ab, 0x00, "Marvell 88SX6041", 4, MVS_Q_GENII},
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{0x604211ab, 0x00, "Marvell 88SX6042", 4, MVS_Q_GENIIE},
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{0x608011ab, 0x00, "Marvell 88SX6080", 8, MVS_Q_GENII},
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{0x608111ab, 0x00, "Marvell 88SX6081", 8, MVS_Q_GENII},
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{0x704211ab, 0x00, "Marvell 88SX7042", 4, MVS_Q_GENIIE|MVS_Q_CT},
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{0x02419005, 0x00, "Adaptec 1420SA", 4, MVS_Q_GENII},
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{0x02439005, 0x00, "Adaptec 1430SA", 4, MVS_Q_GENIIE|MVS_Q_CT},
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{0x00000000, 0x00, NULL, 0, 0}
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};
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static int
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mvs_probe(device_t dev)
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{
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char buf[64];
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int i;
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uint32_t devid = pci_get_devid(dev);
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uint8_t revid = pci_get_revid(dev);
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for (i = 0; mvs_ids[i].id != 0; i++) {
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if (mvs_ids[i].id == devid &&
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mvs_ids[i].rev <= revid) {
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snprintf(buf, sizeof(buf), "%s SATA controller",
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mvs_ids[i].name);
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device_set_desc_copy(dev, buf);
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return (BUS_PROBE_DEFAULT);
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}
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}
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return (ENXIO);
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}
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static int
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mvs_attach(device_t dev)
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{
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struct mvs_controller *ctlr = device_get_softc(dev);
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device_t child;
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int error, unit, i;
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uint32_t devid = pci_get_devid(dev);
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uint8_t revid = pci_get_revid(dev);
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ctlr->dev = dev;
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i = 0;
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while (mvs_ids[i].id != 0 &&
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(mvs_ids[i].id != devid ||
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mvs_ids[i].rev > revid))
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i++;
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ctlr->channels = mvs_ids[i].ports;
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ctlr->quirks = mvs_ids[i].quirks;
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ctlr->ccc = 0;
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resource_int_value(device_get_name(dev),
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device_get_unit(dev), "ccc", &ctlr->ccc);
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ctlr->cccc = 8;
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resource_int_value(device_get_name(dev),
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device_get_unit(dev), "cccc", &ctlr->cccc);
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if (ctlr->ccc == 0 || ctlr->cccc == 0) {
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ctlr->ccc = 0;
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ctlr->cccc = 0;
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}
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if (ctlr->ccc > 100000)
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ctlr->ccc = 100000;
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device_printf(dev,
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"Gen-%s, %d %sGbps ports, Port Multiplier %s%s\n",
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((ctlr->quirks & MVS_Q_GENI) ? "I" :
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((ctlr->quirks & MVS_Q_GENII) ? "II" : "IIe")),
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ctlr->channels,
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((ctlr->quirks & MVS_Q_GENI) ? "1.5" : "3"),
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((ctlr->quirks & MVS_Q_GENI) ?
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"not supported" : "supported"),
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((ctlr->quirks & MVS_Q_GENIIE) ?
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" with FBS" : ""));
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mtx_init(&ctlr->mtx, "MVS controller lock", NULL, MTX_DEF);
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/* We should have a memory BAR(0). */
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ctlr->r_rid = PCIR_BAR(0);
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if (!(ctlr->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
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&ctlr->r_rid, RF_ACTIVE)))
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return ENXIO;
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/* Setup our own memory management for channels. */
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ctlr->sc_iomem.rm_start = rman_get_start(ctlr->r_mem);
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ctlr->sc_iomem.rm_end = rman_get_end(ctlr->r_mem);
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ctlr->sc_iomem.rm_type = RMAN_ARRAY;
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ctlr->sc_iomem.rm_descr = "I/O memory addresses";
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if ((error = rman_init(&ctlr->sc_iomem)) != 0) {
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bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem);
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return (error);
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}
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if ((error = rman_manage_region(&ctlr->sc_iomem,
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rman_get_start(ctlr->r_mem), rman_get_end(ctlr->r_mem))) != 0) {
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bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem);
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rman_fini(&ctlr->sc_iomem);
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return (error);
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}
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pci_enable_busmaster(dev);
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mvs_ctlr_setup(dev);
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/* Setup interrupts. */
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if (mvs_setup_interrupt(dev)) {
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bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem);
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rman_fini(&ctlr->sc_iomem);
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return ENXIO;
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}
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/* Attach all channels on this controller */
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for (unit = 0; unit < ctlr->channels; unit++) {
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child = device_add_child(dev, "mvsch", -1);
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if (child == NULL)
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device_printf(dev, "failed to add channel device\n");
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else
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device_set_ivars(child, (void *)(intptr_t)unit);
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}
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bus_generic_attach(dev);
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return 0;
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}
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static int
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mvs_detach(device_t dev)
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{
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struct mvs_controller *ctlr = device_get_softc(dev);
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/* Detach & delete all children */
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device_delete_children(dev);
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/* Free interrupt. */
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if (ctlr->irq.r_irq) {
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bus_teardown_intr(dev, ctlr->irq.r_irq,
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ctlr->irq.handle);
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bus_release_resource(dev, SYS_RES_IRQ,
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ctlr->irq.r_irq_rid, ctlr->irq.r_irq);
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}
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pci_release_msi(dev);
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/* Free memory. */
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rman_fini(&ctlr->sc_iomem);
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if (ctlr->r_mem)
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bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem);
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mtx_destroy(&ctlr->mtx);
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return (0);
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}
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static int
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mvs_ctlr_setup(device_t dev)
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{
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struct mvs_controller *ctlr = device_get_softc(dev);
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int i, ccc = ctlr->ccc, cccc = ctlr->cccc, ccim = 0;
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/* Mask chip interrupts */
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ATA_OUTL(ctlr->r_mem, CHIP_MIM, 0x00000000);
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/* Mask PCI interrupts */
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ATA_OUTL(ctlr->r_mem, CHIP_PCIIM, 0x00000000);
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/* Clear PCI interrupts */
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ATA_OUTL(ctlr->r_mem, CHIP_PCIIC, 0x00000000);
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if (ccc && bootverbose) {
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device_printf(dev,
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"CCC with %dus/%dcmd enabled\n",
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ctlr->ccc, ctlr->cccc);
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}
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ccc *= 150;
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/* Configure chip-global CCC */
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if (ctlr->channels > 4 && (ctlr->quirks & MVS_Q_GENI) == 0) {
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ATA_OUTL(ctlr->r_mem, CHIP_ICT, cccc);
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ATA_OUTL(ctlr->r_mem, CHIP_ITT, ccc);
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ATA_OUTL(ctlr->r_mem, CHIP_ICC, ~CHIP_ICC_ALL_PORTS);
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if (ccc)
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ccim |= IC_ALL_PORTS_COAL_DONE;
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ccc = 0;
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cccc = 0;
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}
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for (i = 0; i < ctlr->channels / 4; i++) {
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/* Configure per-HC CCC */
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ATA_OUTL(ctlr->r_mem, HC_BASE(i) + HC_ICT, cccc);
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ATA_OUTL(ctlr->r_mem, HC_BASE(i) + HC_ITT, ccc);
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if (ccc)
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ccim |= (IC_HC0_COAL_DONE << (i * IC_HC_SHIFT));
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/* Clear HC interrupts */
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ATA_OUTL(ctlr->r_mem, HC_BASE(i) + HC_IC, 0x00000000);
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}
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/* Enable chip interrupts */
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ctlr->gmim = (ccim ? ccim : (IC_DONE_HC0 | IC_DONE_HC1)) |
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IC_ERR_HC0 | IC_ERR_HC1;
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ctlr->mim = ctlr->gmim | ctlr->pmim;
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ATA_OUTL(ctlr->r_mem, CHIP_MIM, ctlr->mim);
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/* Enable PCI interrupts */
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ATA_OUTL(ctlr->r_mem, CHIP_PCIIM, 0x007fffff);
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return (0);
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}
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static void
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mvs_edma(device_t dev, device_t child, int mode)
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{
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struct mvs_controller *ctlr = device_get_softc(dev);
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int unit = ((struct mvs_channel *)device_get_softc(child))->unit;
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int bit = IC_DONE_IRQ << (unit * 2 + unit / 4) ;
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if (ctlr->ccc == 0)
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return;
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/* CCC is not working for non-EDMA mode. Unmask device interrupts. */
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mtx_lock(&ctlr->mtx);
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if (mode == MVS_EDMA_OFF)
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ctlr->pmim |= bit;
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else
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ctlr->pmim &= ~bit;
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ctlr->mim = ctlr->gmim | ctlr->pmim;
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if (!ctlr->msia)
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ATA_OUTL(ctlr->r_mem, CHIP_MIM, ctlr->mim);
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mtx_unlock(&ctlr->mtx);
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}
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static int
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mvs_suspend(device_t dev)
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{
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struct mvs_controller *ctlr = device_get_softc(dev);
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bus_generic_suspend(dev);
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/* Mask chip interrupts */
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ATA_OUTL(ctlr->r_mem, CHIP_MIM, 0x00000000);
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/* Mask PCI interrupts */
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ATA_OUTL(ctlr->r_mem, CHIP_PCIIM, 0x00000000);
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return 0;
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}
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static int
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mvs_resume(device_t dev)
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{
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mvs_ctlr_setup(dev);
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return (bus_generic_resume(dev));
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}
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static int
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mvs_setup_interrupt(device_t dev)
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{
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struct mvs_controller *ctlr = device_get_softc(dev);
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int msi = 0;
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/* Process hints. */
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resource_int_value(device_get_name(dev),
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device_get_unit(dev), "msi", &msi);
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if (msi < 0)
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msi = 0;
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else if (msi > 0)
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msi = min(1, pci_msi_count(dev));
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/* Allocate MSI if needed/present. */
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if (msi && pci_alloc_msi(dev, &msi) != 0)
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msi = 0;
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ctlr->msi = msi;
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/* Allocate all IRQs. */
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ctlr->irq.r_irq_rid = msi ? 1 : 0;
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if (!(ctlr->irq.r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
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&ctlr->irq.r_irq_rid, RF_SHAREABLE | RF_ACTIVE))) {
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device_printf(dev, "unable to map interrupt\n");
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return (ENXIO);
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}
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if ((bus_setup_intr(dev, ctlr->irq.r_irq, ATA_INTR_FLAGS, NULL,
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mvs_intr, ctlr, &ctlr->irq.handle))) {
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device_printf(dev, "unable to setup interrupt\n");
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bus_release_resource(dev, SYS_RES_IRQ,
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ctlr->irq.r_irq_rid, ctlr->irq.r_irq);
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ctlr->irq.r_irq = NULL;
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return (ENXIO);
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}
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return (0);
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}
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/*
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* Common case interrupt handler.
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*/
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static void
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mvs_intr(void *data)
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{
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struct mvs_controller *ctlr = data;
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struct mvs_intr_arg arg;
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void (*function)(void *);
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int p;
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u_int32_t ic, aic;
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ic = ATA_INL(ctlr->r_mem, CHIP_MIC);
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if (ctlr->msi) {
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/* We have to mask MSI during processing. */
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mtx_lock(&ctlr->mtx);
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ATA_OUTL(ctlr->r_mem, CHIP_MIM, 0);
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ctlr->msia = 1; /* Deny MIM update during processing. */
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mtx_unlock(&ctlr->mtx);
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} else if (ic == 0)
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return;
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/* Acknowledge all-ports CCC interrupt. */
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if (ic & IC_ALL_PORTS_COAL_DONE)
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ATA_OUTL(ctlr->r_mem, CHIP_ICC, ~CHIP_ICC_ALL_PORTS);
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for (p = 0; p < ctlr->channels; p++) {
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if ((p & 3) == 0) {
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if (p != 0)
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ic >>= 1;
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if ((ic & IC_HC0) == 0) {
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p += 3;
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ic >>= 8;
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continue;
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}
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/* Acknowledge interrupts of this HC. */
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aic = 0;
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if (ic & (IC_DONE_IRQ << 0))
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aic |= HC_IC_DONE(0) | HC_IC_DEV(0);
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if (ic & (IC_DONE_IRQ << 2))
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aic |= HC_IC_DONE(1) | HC_IC_DEV(1);
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if (ic & (IC_DONE_IRQ << 4))
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aic |= HC_IC_DONE(2) | HC_IC_DEV(2);
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if (ic & (IC_DONE_IRQ << 6))
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aic |= HC_IC_DONE(3) | HC_IC_DEV(3);
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if (ic & IC_HC0_COAL_DONE)
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aic |= HC_IC_COAL;
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ATA_OUTL(ctlr->r_mem, HC_BASE(p == 4) + HC_IC, ~aic);
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}
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/* Call per-port interrupt handler. */
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arg.cause = ic & (IC_ERR_IRQ|IC_DONE_IRQ);
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if ((arg.cause != 0) &&
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(function = ctlr->interrupt[p].function)) {
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arg.arg = ctlr->interrupt[p].argument;
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function(&arg);
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}
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ic >>= 2;
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}
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if (ctlr->msi) {
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/* Unmasking MSI triggers next interrupt, if needed. */
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mtx_lock(&ctlr->mtx);
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ctlr->msia = 0; /* Allow MIM update. */
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ATA_OUTL(ctlr->r_mem, CHIP_MIM, ctlr->mim);
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mtx_unlock(&ctlr->mtx);
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}
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}
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static struct resource *
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mvs_alloc_resource(device_t dev, device_t child, int type, int *rid,
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rman_res_t start, rman_res_t end, rman_res_t count,
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u_int flags)
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{
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struct mvs_controller *ctlr = device_get_softc(dev);
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int unit = ((struct mvs_channel *)device_get_softc(child))->unit;
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struct resource *res = NULL;
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int offset = HC_BASE(unit >> 2) + PORT_BASE(unit & 0x03);
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rman_res_t st;
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switch (type) {
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case SYS_RES_MEMORY:
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st = rman_get_start(ctlr->r_mem);
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res = rman_reserve_resource(&ctlr->sc_iomem, st + offset,
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st + offset + PORT_SIZE - 1, PORT_SIZE, RF_ACTIVE, child);
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if (res) {
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bus_space_handle_t bsh;
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bus_space_tag_t bst;
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bsh = rman_get_bushandle(ctlr->r_mem);
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bst = rman_get_bustag(ctlr->r_mem);
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bus_space_subregion(bst, bsh, offset, PORT_SIZE, &bsh);
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rman_set_bushandle(res, bsh);
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rman_set_bustag(res, bst);
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}
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break;
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case SYS_RES_IRQ:
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if (*rid == ATA_IRQ_RID)
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res = ctlr->irq.r_irq;
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break;
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}
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return (res);
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}
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static int
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mvs_release_resource(device_t dev, device_t child, int type, int rid,
|
|
struct resource *r)
|
|
{
|
|
|
|
switch (type) {
|
|
case SYS_RES_MEMORY:
|
|
rman_release_resource(r);
|
|
return (0);
|
|
case SYS_RES_IRQ:
|
|
if (rid != ATA_IRQ_RID)
|
|
return ENOENT;
|
|
return (0);
|
|
}
|
|
return (EINVAL);
|
|
}
|
|
|
|
static int
|
|
mvs_setup_intr(device_t dev, device_t child, struct resource *irq,
|
|
int flags, driver_filter_t *filter, driver_intr_t *function,
|
|
void *argument, void **cookiep)
|
|
{
|
|
struct mvs_controller *ctlr = device_get_softc(dev);
|
|
int unit = (intptr_t)device_get_ivars(child);
|
|
|
|
if (filter != NULL) {
|
|
printf("mvs.c: we cannot use a filter here\n");
|
|
return (EINVAL);
|
|
}
|
|
ctlr->interrupt[unit].function = function;
|
|
ctlr->interrupt[unit].argument = argument;
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
mvs_teardown_intr(device_t dev, device_t child, struct resource *irq,
|
|
void *cookie)
|
|
{
|
|
struct mvs_controller *ctlr = device_get_softc(dev);
|
|
int unit = (intptr_t)device_get_ivars(child);
|
|
|
|
ctlr->interrupt[unit].function = NULL;
|
|
ctlr->interrupt[unit].argument = NULL;
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
mvs_print_child(device_t dev, device_t child)
|
|
{
|
|
int retval;
|
|
|
|
retval = bus_print_child_header(dev, child);
|
|
retval += printf(" at channel %d",
|
|
(int)(intptr_t)device_get_ivars(child));
|
|
retval += bus_print_child_footer(dev, child);
|
|
|
|
return (retval);
|
|
}
|
|
|
|
static int
|
|
mvs_child_location_str(device_t dev, device_t child, char *buf,
|
|
size_t buflen)
|
|
{
|
|
|
|
snprintf(buf, buflen, "channel=%d",
|
|
(int)(intptr_t)device_get_ivars(child));
|
|
return (0);
|
|
}
|
|
|
|
static bus_dma_tag_t
|
|
mvs_get_dma_tag(device_t bus, device_t child)
|
|
{
|
|
|
|
return (bus_get_dma_tag(bus));
|
|
}
|
|
|
|
static device_method_t mvs_methods[] = {
|
|
DEVMETHOD(device_probe, mvs_probe),
|
|
DEVMETHOD(device_attach, mvs_attach),
|
|
DEVMETHOD(device_detach, mvs_detach),
|
|
DEVMETHOD(device_suspend, mvs_suspend),
|
|
DEVMETHOD(device_resume, mvs_resume),
|
|
DEVMETHOD(bus_print_child, mvs_print_child),
|
|
DEVMETHOD(bus_alloc_resource, mvs_alloc_resource),
|
|
DEVMETHOD(bus_release_resource, mvs_release_resource),
|
|
DEVMETHOD(bus_setup_intr, mvs_setup_intr),
|
|
DEVMETHOD(bus_teardown_intr,mvs_teardown_intr),
|
|
DEVMETHOD(bus_child_location_str, mvs_child_location_str),
|
|
DEVMETHOD(bus_get_dma_tag, mvs_get_dma_tag),
|
|
DEVMETHOD(mvs_edma, mvs_edma),
|
|
{ 0, 0 }
|
|
};
|
|
static driver_t mvs_driver = {
|
|
"mvs",
|
|
mvs_methods,
|
|
sizeof(struct mvs_controller)
|
|
};
|
|
DRIVER_MODULE(mvs, pci, mvs_driver, mvs_devclass, 0, 0);
|
|
MODULE_PNP_INFO("W32:vendor/device", pci, mvs, mvs_ids,
|
|
nitems(mvs_ids) - 1);
|
|
MODULE_VERSION(mvs, 1);
|
|
MODULE_DEPEND(mvs, cam, 1, 1, 1);
|
|
|