718cf2ccb9
Mainly focus on files that use BSD 2-Clause license, however the tool I was using misidentified many licenses so this was mostly a manual - error prone - task. The Software Package Data Exchange (SPDX) group provides a specification to make it easier for automated tools to detect and summarize well known opensource licenses. We are gradually adopting the specification, noting that the tags are considered only advisory and do not, in any way, superceed or replace the license texts.
621 lines
16 KiB
C
621 lines
16 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2012 The FreeBSD Foundation
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* All rights reserved.
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*
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* This software was developed by Oleksandr Rybalko under sponsorship
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* from the FreeBSD Foundation.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include "opt_ddb.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/conf.h>
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#include <sys/kdb.h>
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#include <machine/bus.h>
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#include <machine/fdt.h>
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#include <dev/uart/uart.h>
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#include <dev/uart/uart_cpu.h>
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#include <dev/uart/uart_cpu_fdt.h>
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#include <dev/uart/uart_bus.h>
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#include <dev/uart/uart_dev_imx.h>
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#include "uart_if.h"
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#include <arm/freescale/imx/imx_ccmvar.h>
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/*
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* The hardare FIFOs are 32 bytes. We want an interrupt when there are 24 bytes
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* available to read or space for 24 more bytes to write. While 8 bytes of
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* slack before over/underrun might seem excessive, the hardware can run at
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* 5mbps, which means 2uS per char, so at full speed 8 bytes provides only 16uS
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* to get into the interrupt handler and service the fifo.
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*/
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#define IMX_FIFOSZ 32
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#define IMX_RXFIFO_LEVEL 24
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#define IMX_TXFIFO_LEVEL 24
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/*
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* Low-level UART interface.
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*/
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static int imx_uart_probe(struct uart_bas *bas);
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static void imx_uart_init(struct uart_bas *bas, int, int, int, int);
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static void imx_uart_term(struct uart_bas *bas);
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static void imx_uart_putc(struct uart_bas *bas, int);
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static int imx_uart_rxready(struct uart_bas *bas);
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static int imx_uart_getc(struct uart_bas *bas, struct mtx *);
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static struct uart_ops uart_imx_uart_ops = {
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.probe = imx_uart_probe,
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.init = imx_uart_init,
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.term = imx_uart_term,
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.putc = imx_uart_putc,
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.rxready = imx_uart_rxready,
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.getc = imx_uart_getc,
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};
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#if 0 /* Handy when debugging. */
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static void
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dumpregs(struct uart_bas *bas, const char * msg)
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{
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if (!bootverbose)
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return;
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printf("%s bsh 0x%08lx UCR1 0x%08x UCR2 0x%08x "
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"UCR3 0x%08x UCR4 0x%08x USR1 0x%08x USR2 0x%08x\n",
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msg, bas->bsh,
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GETREG(bas, REG(UCR1)), GETREG(bas, REG(UCR2)),
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GETREG(bas, REG(UCR3)), GETREG(bas, REG(UCR4)),
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GETREG(bas, REG(USR1)), GETREG(bas, REG(USR2)));
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}
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#endif
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static int
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imx_uart_probe(struct uart_bas *bas)
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{
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return (0);
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}
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static u_int
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imx_uart_getbaud(struct uart_bas *bas)
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{
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uint32_t rate, ubir, ubmr;
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u_int baud, blo, bhi, i;
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static const u_int predivs[] = {6, 5, 4, 3, 2, 1, 7, 1};
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static const u_int std_rates[] = {
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9600, 14400, 19200, 38400, 57600, 115200, 230400, 460800, 921600
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};
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/*
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* Get the baud rate the hardware is programmed for, then search the
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* table of standard baud rates for a number that's within 3% of the
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* actual rate the hardware is programmed for. It's more comforting to
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* see that your console is running at 115200 than 114942. Note that
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* here we cannot make a simplifying assumption that the predivider and
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* numerator are 1 (like we do when setting the baud rate), because we
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* don't know what u-boot might have set up.
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*/
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i = (GETREG(bas, REG(UFCR)) & IMXUART_UFCR_RFDIV_MASK) >>
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IMXUART_UFCR_RFDIV_SHIFT;
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rate = imx_ccm_uart_hz() / predivs[i];
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ubir = GETREG(bas, REG(UBIR)) + 1;
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ubmr = GETREG(bas, REG(UBMR)) + 1;
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baud = ((rate / 16 ) * ubir) / ubmr;
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blo = (baud * 100) / 103;
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bhi = (baud * 100) / 97;
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for (i = 0; i < nitems(std_rates); i++) {
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rate = std_rates[i];
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if (rate >= blo && rate <= bhi) {
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baud = rate;
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break;
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}
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}
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return (baud);
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}
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static void
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imx_uart_init(struct uart_bas *bas, int baudrate, int databits,
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int stopbits, int parity)
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{
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uint32_t baseclk, reg;
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/* Enable the device and the RX/TX channels. */
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SET(bas, REG(UCR1), FLD(UCR1, UARTEN));
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SET(bas, REG(UCR2), FLD(UCR2, RXEN) | FLD(UCR2, TXEN));
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if (databits == 7)
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DIS(bas, UCR2, WS);
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else
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ENA(bas, UCR2, WS);
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if (stopbits == 2)
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ENA(bas, UCR2, STPB);
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else
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DIS(bas, UCR2, STPB);
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switch (parity) {
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case UART_PARITY_ODD:
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DIS(bas, UCR2, PROE);
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ENA(bas, UCR2, PREN);
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break;
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case UART_PARITY_EVEN:
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ENA(bas, UCR2, PROE);
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ENA(bas, UCR2, PREN);
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break;
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case UART_PARITY_MARK:
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case UART_PARITY_SPACE:
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/* FALLTHROUGH: Hardware doesn't support mark/space. */
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case UART_PARITY_NONE:
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default:
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DIS(bas, UCR2, PREN);
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break;
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}
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/*
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* The hardware has an extremely flexible baud clock: it allows setting
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* both the numerator and denominator of the divider, as well as a
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* separate pre-divider. We simplify the problem of coming up with a
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* workable pair of numbers by assuming a pre-divider and numerator of
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* one because our base clock is so fast we can reach virtually any
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* reasonable speed with a simple divisor. The numerator value actually
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* includes the 16x over-sampling (so a value of 16 means divide by 1);
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* the register value is the numerator-1, so we have a hard-coded 15.
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* Note that a quirk of the hardware requires that both UBIR and UBMR be
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* set back to back in order for the change to take effect.
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*/
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if (baudrate > 0) {
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baseclk = imx_ccm_uart_hz();
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reg = GETREG(bas, REG(UFCR));
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reg = (reg & ~IMXUART_UFCR_RFDIV_MASK) | IMXUART_UFCR_RFDIV_DIV1;
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SETREG(bas, REG(UFCR), reg);
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SETREG(bas, REG(UBIR), 15);
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SETREG(bas, REG(UBMR), (baseclk / baudrate) - 1);
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}
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/*
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* Program the tx lowater and rx hiwater levels at which fifo-service
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* interrupts are signaled. The tx value is interpetted as "when there
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* are only this many bytes remaining" (not "this many free").
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*/
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reg = GETREG(bas, REG(UFCR));
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reg &= ~(IMXUART_UFCR_TXTL_MASK | IMXUART_UFCR_RXTL_MASK);
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reg |= (IMX_FIFOSZ - IMX_TXFIFO_LEVEL) << IMXUART_UFCR_TXTL_SHIFT;
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reg |= IMX_RXFIFO_LEVEL << IMXUART_UFCR_RXTL_SHIFT;
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SETREG(bas, REG(UFCR), reg);
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}
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static void
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imx_uart_term(struct uart_bas *bas)
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{
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}
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static void
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imx_uart_putc(struct uart_bas *bas, int c)
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{
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while (!(IS(bas, USR1, TRDY)))
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;
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SETREG(bas, REG(UTXD), c);
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}
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static int
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imx_uart_rxready(struct uart_bas *bas)
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{
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return ((IS(bas, USR2, RDR)) ? 1 : 0);
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}
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static int
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imx_uart_getc(struct uart_bas *bas, struct mtx *hwmtx)
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{
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int c;
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uart_lock(hwmtx);
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while (!(IS(bas, USR2, RDR)))
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;
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c = GETREG(bas, REG(URXD));
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uart_unlock(hwmtx);
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#if defined(KDB)
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if (c & FLD(URXD, BRK)) {
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if (kdb_break())
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return (0);
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}
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#endif
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return (c & 0xff);
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}
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/*
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* High-level UART interface.
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*/
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struct imx_uart_softc {
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struct uart_softc base;
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};
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static int imx_uart_bus_attach(struct uart_softc *);
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static int imx_uart_bus_detach(struct uart_softc *);
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static int imx_uart_bus_flush(struct uart_softc *, int);
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static int imx_uart_bus_getsig(struct uart_softc *);
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static int imx_uart_bus_ioctl(struct uart_softc *, int, intptr_t);
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static int imx_uart_bus_ipend(struct uart_softc *);
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static int imx_uart_bus_param(struct uart_softc *, int, int, int, int);
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static int imx_uart_bus_probe(struct uart_softc *);
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static int imx_uart_bus_receive(struct uart_softc *);
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static int imx_uart_bus_setsig(struct uart_softc *, int);
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static int imx_uart_bus_transmit(struct uart_softc *);
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static void imx_uart_bus_grab(struct uart_softc *);
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static void imx_uart_bus_ungrab(struct uart_softc *);
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static kobj_method_t imx_uart_methods[] = {
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KOBJMETHOD(uart_attach, imx_uart_bus_attach),
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KOBJMETHOD(uart_detach, imx_uart_bus_detach),
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KOBJMETHOD(uart_flush, imx_uart_bus_flush),
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KOBJMETHOD(uart_getsig, imx_uart_bus_getsig),
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KOBJMETHOD(uart_ioctl, imx_uart_bus_ioctl),
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KOBJMETHOD(uart_ipend, imx_uart_bus_ipend),
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KOBJMETHOD(uart_param, imx_uart_bus_param),
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KOBJMETHOD(uart_probe, imx_uart_bus_probe),
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KOBJMETHOD(uart_receive, imx_uart_bus_receive),
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KOBJMETHOD(uart_setsig, imx_uart_bus_setsig),
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KOBJMETHOD(uart_transmit, imx_uart_bus_transmit),
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KOBJMETHOD(uart_grab, imx_uart_bus_grab),
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KOBJMETHOD(uart_ungrab, imx_uart_bus_ungrab),
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{ 0, 0 }
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};
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static struct uart_class uart_imx_class = {
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"imx",
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imx_uart_methods,
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sizeof(struct imx_uart_softc),
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.uc_ops = &uart_imx_uart_ops,
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.uc_range = 0x100,
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.uc_rclk = 24000000, /* TODO: get value from CCM */
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.uc_rshift = 0
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};
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static struct ofw_compat_data compat_data[] = {
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{"fsl,imx6q-uart", (uintptr_t)&uart_imx_class},
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{"fsl,imx53-uart", (uintptr_t)&uart_imx_class},
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{"fsl,imx51-uart", (uintptr_t)&uart_imx_class},
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{"fsl,imx31-uart", (uintptr_t)&uart_imx_class},
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{"fsl,imx27-uart", (uintptr_t)&uart_imx_class},
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{"fsl,imx25-uart", (uintptr_t)&uart_imx_class},
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{"fsl,imx21-uart", (uintptr_t)&uart_imx_class},
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{NULL, (uintptr_t)NULL},
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};
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UART_FDT_CLASS_AND_DEVICE(compat_data);
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#define SIGCHG(c, i, s, d) \
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if (c) { \
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i |= (i & s) ? s : s | d; \
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} else { \
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i = (i & s) ? (i & ~s) | d : i; \
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}
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static int
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imx_uart_bus_attach(struct uart_softc *sc)
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{
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struct uart_bas *bas;
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struct uart_devinfo *di;
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bas = &sc->sc_bas;
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if (sc->sc_sysdev != NULL) {
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di = sc->sc_sysdev;
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imx_uart_init(bas, di->baudrate, di->databits, di->stopbits,
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di->parity);
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} else {
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imx_uart_init(bas, 115200, 8, 1, 0);
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}
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(void)imx_uart_bus_getsig(sc);
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/* Clear all pending interrupts. */
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SETREG(bas, REG(USR1), 0xffff);
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SETREG(bas, REG(USR2), 0xffff);
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DIS(bas, UCR4, DREN);
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ENA(bas, UCR1, RRDYEN);
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DIS(bas, UCR1, IDEN);
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DIS(bas, UCR3, RXDSEN);
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ENA(bas, UCR2, ATEN);
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DIS(bas, UCR1, TXMPTYEN);
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DIS(bas, UCR1, TRDYEN);
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DIS(bas, UCR4, TCEN);
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DIS(bas, UCR4, OREN);
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ENA(bas, UCR4, BKEN);
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DIS(bas, UCR4, WKEN);
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DIS(bas, UCR1, ADEN);
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DIS(bas, UCR3, ACIEN);
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DIS(bas, UCR2, ESCI);
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DIS(bas, UCR4, ENIRI);
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DIS(bas, UCR3, AIRINTEN);
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DIS(bas, UCR3, AWAKEN);
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DIS(bas, UCR3, FRAERREN);
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DIS(bas, UCR3, PARERREN);
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DIS(bas, UCR1, RTSDEN);
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DIS(bas, UCR2, RTSEN);
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DIS(bas, UCR3, DTREN);
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DIS(bas, UCR3, RI);
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DIS(bas, UCR3, DCD);
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DIS(bas, UCR3, DTRDEN);
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ENA(bas, UCR2, IRTS);
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ENA(bas, UCR3, RXDMUXSEL);
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return (0);
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}
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static int
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imx_uart_bus_detach(struct uart_softc *sc)
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{
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SETREG(&sc->sc_bas, REG(UCR4), 0);
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return (0);
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}
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static int
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imx_uart_bus_flush(struct uart_softc *sc, int what)
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{
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/* TODO */
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return (0);
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}
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static int
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imx_uart_bus_getsig(struct uart_softc *sc)
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{
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uint32_t new, old, sig;
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uint8_t bes;
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do {
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old = sc->sc_hwsig;
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sig = old;
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uart_lock(sc->sc_hwmtx);
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bes = GETREG(&sc->sc_bas, REG(USR2));
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uart_unlock(sc->sc_hwmtx);
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/* XXX: chip can show delta */
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SIGCHG(bes & FLD(USR2, DCDIN), sig, SER_DCD, SER_DDCD);
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new = sig & ~SER_MASK_DELTA;
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} while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
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return (sig);
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}
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static int
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imx_uart_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
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{
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struct uart_bas *bas;
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int error;
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bas = &sc->sc_bas;
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error = 0;
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uart_lock(sc->sc_hwmtx);
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switch (request) {
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case UART_IOCTL_BREAK:
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/* TODO */
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break;
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case UART_IOCTL_BAUD:
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*(u_int*)data = imx_uart_getbaud(bas);
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break;
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default:
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error = EINVAL;
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break;
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}
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uart_unlock(sc->sc_hwmtx);
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return (error);
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}
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static int
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imx_uart_bus_ipend(struct uart_softc *sc)
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{
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struct uart_bas *bas;
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int ipend;
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uint32_t usr1, usr2;
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uint32_t ucr1, ucr2, ucr4;
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bas = &sc->sc_bas;
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ipend = 0;
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uart_lock(sc->sc_hwmtx);
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/* Read pending interrupts */
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usr1 = GETREG(bas, REG(USR1));
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usr2 = GETREG(bas, REG(USR2));
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/* ACK interrupts */
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SETREG(bas, REG(USR1), usr1);
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SETREG(bas, REG(USR2), usr2);
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ucr1 = GETREG(bas, REG(UCR1));
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ucr2 = GETREG(bas, REG(UCR2));
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ucr4 = GETREG(bas, REG(UCR4));
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/* If we have reached tx low-water, we can tx some more now. */
|
|
if ((usr1 & FLD(USR1, TRDY)) && (ucr1 & FLD(UCR1, TRDYEN))) {
|
|
DIS(bas, UCR1, TRDYEN);
|
|
ipend |= SER_INT_TXIDLE;
|
|
}
|
|
|
|
/*
|
|
* If we have reached the rx high-water, or if there are bytes in the rx
|
|
* fifo and no new data has arrived for 8 character periods (aging
|
|
* timer), we have input data to process.
|
|
*/
|
|
if (((usr1 & FLD(USR1, RRDY)) && (ucr1 & FLD(UCR1, RRDYEN))) ||
|
|
((usr1 & FLD(USR1, AGTIM)) && (ucr2 & FLD(UCR2, ATEN)))) {
|
|
DIS(bas, UCR1, RRDYEN);
|
|
DIS(bas, UCR2, ATEN);
|
|
ipend |= SER_INT_RXREADY;
|
|
}
|
|
|
|
/* A break can come in at any time, it never gets disabled. */
|
|
if ((usr2 & FLD(USR2, BRCD)) && (ucr4 & FLD(UCR4, BKEN)))
|
|
ipend |= SER_INT_BREAK;
|
|
|
|
uart_unlock(sc->sc_hwmtx);
|
|
|
|
return (ipend);
|
|
}
|
|
|
|
static int
|
|
imx_uart_bus_param(struct uart_softc *sc, int baudrate, int databits,
|
|
int stopbits, int parity)
|
|
{
|
|
|
|
uart_lock(sc->sc_hwmtx);
|
|
imx_uart_init(&sc->sc_bas, baudrate, databits, stopbits, parity);
|
|
uart_unlock(sc->sc_hwmtx);
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
imx_uart_bus_probe(struct uart_softc *sc)
|
|
{
|
|
int error;
|
|
|
|
error = imx_uart_probe(&sc->sc_bas);
|
|
if (error)
|
|
return (error);
|
|
|
|
/*
|
|
* On input we can read up to the full fifo size at once. On output, we
|
|
* want to write only as much as the programmed tx low water level,
|
|
* because that's all we can be certain we have room for in the fifo
|
|
* when we get a tx-ready interrupt.
|
|
*/
|
|
sc->sc_rxfifosz = IMX_FIFOSZ;
|
|
sc->sc_txfifosz = IMX_TXFIFO_LEVEL;
|
|
|
|
device_set_desc(sc->sc_dev, "Freescale i.MX UART");
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
imx_uart_bus_receive(struct uart_softc *sc)
|
|
{
|
|
struct uart_bas *bas;
|
|
int xc, out;
|
|
|
|
bas = &sc->sc_bas;
|
|
uart_lock(sc->sc_hwmtx);
|
|
|
|
/*
|
|
* Empty the rx fifo. We get the RRDY interrupt when IMX_RXFIFO_LEVEL
|
|
* (the rx high-water level) is reached, but we set sc_rxfifosz to the
|
|
* full hardware fifo size, so we can safely process however much is
|
|
* there, not just the highwater size.
|
|
*/
|
|
while (IS(bas, USR2, RDR)) {
|
|
if (uart_rx_full(sc)) {
|
|
/* No space left in input buffer */
|
|
sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
|
|
break;
|
|
}
|
|
xc = GETREG(bas, REG(URXD));
|
|
out = xc & 0x000000ff;
|
|
if (xc & FLD(URXD, FRMERR))
|
|
out |= UART_STAT_FRAMERR;
|
|
if (xc & FLD(URXD, PRERR))
|
|
out |= UART_STAT_PARERR;
|
|
if (xc & FLD(URXD, OVRRUN))
|
|
out |= UART_STAT_OVERRUN;
|
|
if (xc & FLD(URXD, BRK))
|
|
out |= UART_STAT_BREAK;
|
|
|
|
uart_rx_put(sc, out);
|
|
}
|
|
ENA(bas, UCR1, RRDYEN);
|
|
ENA(bas, UCR2, ATEN);
|
|
|
|
uart_unlock(sc->sc_hwmtx);
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
imx_uart_bus_setsig(struct uart_softc *sc, int sig)
|
|
{
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
imx_uart_bus_transmit(struct uart_softc *sc)
|
|
{
|
|
struct uart_bas *bas = &sc->sc_bas;
|
|
int i;
|
|
|
|
bas = &sc->sc_bas;
|
|
uart_lock(sc->sc_hwmtx);
|
|
|
|
/*
|
|
* Fill the tx fifo. The uart core puts at most IMX_TXFIFO_LEVEL bytes
|
|
* into the txbuf (because that's what sc_txfifosz is set to), and
|
|
* because we got the TRDY (low-water reached) interrupt we know at
|
|
* least that much space is available in the fifo.
|
|
*/
|
|
for (i = 0; i < sc->sc_txdatasz; i++) {
|
|
SETREG(bas, REG(UTXD), sc->sc_txbuf[i] & 0xff);
|
|
}
|
|
sc->sc_txbusy = 1;
|
|
ENA(bas, UCR1, TRDYEN);
|
|
|
|
uart_unlock(sc->sc_hwmtx);
|
|
|
|
return (0);
|
|
}
|
|
|
|
static void
|
|
imx_uart_bus_grab(struct uart_softc *sc)
|
|
{
|
|
struct uart_bas *bas = &sc->sc_bas;
|
|
|
|
bas = &sc->sc_bas;
|
|
uart_lock(sc->sc_hwmtx);
|
|
DIS(bas, UCR1, RRDYEN);
|
|
DIS(bas, UCR2, ATEN);
|
|
uart_unlock(sc->sc_hwmtx);
|
|
}
|
|
|
|
static void
|
|
imx_uart_bus_ungrab(struct uart_softc *sc)
|
|
{
|
|
struct uart_bas *bas = &sc->sc_bas;
|
|
|
|
bas = &sc->sc_bas;
|
|
uart_lock(sc->sc_hwmtx);
|
|
ENA(bas, UCR1, RRDYEN);
|
|
ENA(bas, UCR2, ATEN);
|
|
uart_unlock(sc->sc_hwmtx);
|
|
}
|