80a7c0f53b
DMA boundary constraint applied in bhndb_dma_tag_create(). Sponsored by: The FreeBSD Foundation
680 lines
18 KiB
C
680 lines
18 KiB
C
/*-
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* Copyright (c) 2015 Landon Fuller <landon@landonf.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer,
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* without modification.
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* 2. Redistributions in binary form must reproduce at minimum a disclaimer
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* similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
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* redistribution must be conditioned upon including a substantially
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* similar Disclaimer requirement for further binary redistribution.
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*
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* NO WARRANTY
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
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* AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
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* OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
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* IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGES.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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/*
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* Resource specifications and register maps for Broadcom PCI/PCIe cores
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* configured as PCI-BHND bridges.
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*/
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#include <sys/param.h>
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#include <sys/bus.h>
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#include <machine/bus.h>
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#include <sys/rman.h>
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#include <machine/resource.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcivar.h>
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#include <dev/bhnd/cores/pci/bhnd_pcireg.h>
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#include <dev/bhnd/cores/pcie2/bhnd_pcie2_reg.h>
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#include "bhndbvar.h"
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#include "bhndb_pcireg.h"
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static const struct bhndb_hwcfg bhndb_pci_hwcfg_v0;
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static const struct bhndb_hwcfg bhndb_pci_hwcfg_v1_pci;
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static const struct bhndb_hwcfg bhndb_pci_hwcfg_v1_pcie;
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static const struct bhndb_hwcfg bhndb_pci_hwcfg_v2;
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static const struct bhndb_hwcfg bhndb_pci_hwcfg_v3;
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/**
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* Define a bhndb_hw match entry.
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*
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* @param _name The entry name.
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* @param _vers The configuration version associated with this entry.
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*/
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#define BHNDB_HW_MATCH(_name, _vers, ...) { \
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.name = _name, \
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.hw_reqs = _BHNDB_HW_REQ_ARRAY(__VA_ARGS__), \
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.num_hw_reqs = (sizeof(_BHNDB_HW_REQ_ARRAY(__VA_ARGS__)) / \
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sizeof(_BHNDB_HW_REQ_ARRAY(__VA_ARGS__)[0])), \
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.cfg = &bhndb_pci_hwcfg_ ## _vers \
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}
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#define _BHNDB_HW_REQ_ARRAY(...) (struct bhnd_core_match[]) { __VA_ARGS__ }
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/**
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* Generic PCI-SIBA bridge configuration usable with all known siba(4)-based
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* PCI devices; this configuration is adequate for enumerating a bridged
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* siba(4) bus to determine the full hardware configuration.
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*
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* @par Compatibility
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* - Compatible with PCI_V0, PCI_V1, PCI_V2, and PCI_V3 devices.
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* - Compatible with siba(4) bus enumeration.
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* - Compatible with bcma(4) bus enumeration if the ChipCommon core is mapped
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* at the default enumeration address (0x18000000).
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*/
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const struct bhndb_hwcfg bhndb_pci_siba_generic_hwcfg = {
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.resource_specs = (const struct resource_spec[]) {
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{ SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE },
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{ -1, 0, 0 }
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},
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.register_windows = (const struct bhndb_regwin[]) {
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/* bar0+0x0000: configurable backplane window */
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{
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.win_type = BHNDB_REGWIN_T_DYN,
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.win_offset = BHNDB_PCI_V1_BAR0_WIN0_OFFSET,
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.win_size = BHNDB_PCI_V1_BAR0_WIN0_SIZE,
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.d.dyn = {
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.cfg_offset = BHNDB_PCI_V1_BAR0_WIN0_CONTROL
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},
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.res = { SYS_RES_MEMORY, PCIR_BAR(0) }
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},
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BHNDB_REGWIN_TABLE_END
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},
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/* DMA unsupported under generic configuration */
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.dma_translations = NULL,
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};
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/**
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* Generic PCI-BCMA bridge configuration usable with all known bcma(4)-based
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* PCI devices; this configuration is adequate for enumerating a bridged
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* bcma(4) bus to determine the full hardware configuration.
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*
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* @par Compatibility
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* - Compatible with PCI_V1, PCI_V2, and PCI_V3 devices.
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* - Compatible with both siba(4) and bcma(4) bus enumeration.
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*/
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const struct bhndb_hwcfg bhndb_pci_bcma_generic_hwcfg = {
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.resource_specs = (const struct resource_spec[]) {
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{ SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE },
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{ -1, 0, 0 }
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},
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.register_windows = (const struct bhndb_regwin[]) {
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/* bar0+0x0000: configurable backplane window */
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{
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.win_type = BHNDB_REGWIN_T_DYN,
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.win_offset = BHNDB_PCI_V1_BAR0_WIN0_OFFSET,
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.win_size = BHNDB_PCI_V1_BAR0_WIN0_SIZE,
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.d.dyn = {
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.cfg_offset = BHNDB_PCI_V1_BAR0_WIN0_CONTROL,
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},
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.res = { SYS_RES_MEMORY, PCIR_BAR(0) }
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},
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/* bar0+0x3000: chipc core registers */
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{
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.win_type = BHNDB_REGWIN_T_CORE,
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.win_offset = BHNDB_PCI_V1_BAR0_CCREGS_OFFSET,
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.win_size = BHNDB_PCI_V1_BAR0_CCREGS_SIZE,
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.d.core = {
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.class = BHND_DEVCLASS_CC,
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.unit = 0,
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.port = 0,
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.region = 0,
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.port_type = BHND_PORT_DEVICE
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},
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.res = { SYS_RES_MEMORY, PCIR_BAR(0) }
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},
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BHNDB_REGWIN_TABLE_END
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},
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/* DMA unsupported under generic configuration */
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.dma_translations = NULL,
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};
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/**
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* Hardware configuration tables for Broadcom HND PCI NICs.
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*/
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const struct bhndb_hw bhndb_pci_generic_hw_table[] = {
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/* PCI/V0 WLAN */
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BHNDB_HW_MATCH("PCI/v0 WLAN", v0,
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/* PCI Core */
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{
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BHND_MATCH_CORE_VENDOR (BHND_MFGID_BCM),
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BHND_MATCH_CORE_ID (BHND_COREID_PCI),
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BHND_MATCH_CORE_REV(
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HWREV_LTE (BHNDB_PCI_V0_MAX_PCI_HWREV)),
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BHND_MATCH_CORE_CLASS (BHND_DEVCLASS_PCI),
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BHND_MATCH_CORE_UNIT (0)
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},
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/* 802.11 Core */
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{
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BHND_MATCH_CORE_VENDOR (BHND_MFGID_BCM),
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BHND_MATCH_CORE_CLASS (BHND_DEVCLASS_WLAN),
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BHND_MATCH_CORE_UNIT (0)
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}
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),
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/* PCI/V1 WLAN */
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BHNDB_HW_MATCH("PCI/v1 WLAN", v1_pci,
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/* PCI Core */
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{
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BHND_MATCH_CORE_VENDOR (BHND_MFGID_BCM),
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BHND_MATCH_CORE_ID (BHND_COREID_PCI),
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BHND_MATCH_CORE_REV(
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HWREV_GTE (BHNDB_PCI_V1_MIN_PCI_HWREV)),
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BHND_MATCH_CORE_CLASS (BHND_DEVCLASS_PCI),
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BHND_MATCH_CORE_UNIT (0)
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},
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/* 802.11 Core */
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{
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BHND_MATCH_CORE_VENDOR (BHND_MFGID_BCM),
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BHND_MATCH_CORE_CLASS (BHND_DEVCLASS_WLAN),
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BHND_MATCH_CORE_UNIT (0)
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}
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),
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/* PCIE/V1 WLAN */
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BHNDB_HW_MATCH("PCIe/v1 WLAN", v1_pcie,
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/* PCIe Core */
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{
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BHND_MATCH_CORE_VENDOR (BHND_MFGID_BCM),
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BHND_MATCH_CORE_ID (BHND_COREID_PCIE),
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BHND_MATCH_CORE_CLASS (BHND_DEVCLASS_PCIE),
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BHND_MATCH_CORE_UNIT (0)
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},
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/* ChipCommon (revision <= 31) */
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{
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BHND_MATCH_CORE_VENDOR (BHND_MFGID_BCM),
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BHND_MATCH_CORE_ID (BHND_COREID_CC),
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BHND_MATCH_CORE_REV(
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HWREV_LTE (BHNDB_PCI_V1_MAX_CHIPC_HWREV)),
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BHND_MATCH_CORE_CLASS (BHND_DEVCLASS_CC),
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BHND_MATCH_CORE_UNIT (0)
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},
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/* 802.11 Core */
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{
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BHND_MATCH_CORE_VENDOR (BHND_MFGID_BCM),
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BHND_MATCH_CORE_CLASS (BHND_DEVCLASS_WLAN),
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BHND_MATCH_CORE_UNIT (0)
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}
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),
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/* PCIE/V2 WLAN */
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BHNDB_HW_MATCH("PCIe/v2 WLAN", v2,
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/* PCIe Core */
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{
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BHND_MATCH_CORE_VENDOR (BHND_MFGID_BCM),
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BHND_MATCH_CORE_ID (BHND_COREID_PCIE),
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BHND_MATCH_CORE_CLASS (BHND_DEVCLASS_PCIE),
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BHND_MATCH_CORE_UNIT (0)
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},
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/* ChipCommon (revision >= 32) */
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{
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BHND_MATCH_CORE_VENDOR (BHND_MFGID_BCM),
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BHND_MATCH_CORE_ID (BHND_COREID_CC),
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BHND_MATCH_CORE_REV(
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HWREV_GTE (BHNDB_PCI_V2_MIN_CHIPC_HWREV)),
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BHND_MATCH_CORE_CLASS (BHND_DEVCLASS_CC),
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BHND_MATCH_CORE_UNIT (0)
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},
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/* 802.11 Core */
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{
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BHND_MATCH_CORE_VENDOR (BHND_MFGID_BCM),
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BHND_MATCH_CORE_CLASS (BHND_DEVCLASS_WLAN),
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BHND_MATCH_CORE_UNIT (0)
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}
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),
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/* PCIE/V3 WLAN */
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BHNDB_HW_MATCH("PCIe-Gen2/v3 WLAN", v3,
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/* PCIe Gen2 Core */
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{
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BHND_MATCH_CORE_VENDOR (BHND_MFGID_BCM),
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BHND_MATCH_CORE_ID (BHND_COREID_PCIE2),
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BHND_MATCH_CORE_CLASS (BHND_DEVCLASS_PCIE),
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BHND_MATCH_CORE_UNIT (0)
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},
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/* 802.11 Core */
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{
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BHND_MATCH_CORE_VENDOR (BHND_MFGID_BCM),
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BHND_MATCH_CORE_CLASS (BHND_DEVCLASS_WLAN),
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BHND_MATCH_CORE_UNIT (0)
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}
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),
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{ NULL, NULL, 0, NULL }
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};
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/**
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* PCI_V0 hardware configuration.
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*
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* Applies to:
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* - PCI (cid=0x804, revision <= 12)
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*/
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static const struct bhndb_hwcfg bhndb_pci_hwcfg_v0 = {
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.resource_specs = (const struct resource_spec[]) {
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{ SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE },
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{ -1, 0, 0 }
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},
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.register_windows = (const struct bhndb_regwin[]) {
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/* bar0+0x0000: configurable backplane window */
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{
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.win_type = BHNDB_REGWIN_T_DYN,
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.win_offset = BHNDB_PCI_V0_BAR0_WIN0_OFFSET,
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.win_size = BHNDB_PCI_V0_BAR0_WIN0_SIZE,
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.d.dyn = {
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.cfg_offset = BHNDB_PCI_V0_BAR0_WIN0_CONTROL
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},
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.res = { SYS_RES_MEMORY, PCIR_BAR(0) }
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},
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/* bar0+0x1000: sprom shadow */
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{
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.win_type = BHNDB_REGWIN_T_SPROM,
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.win_offset = BHNDB_PCI_V0_BAR0_SPROM_OFFSET,
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.win_size = BHNDB_PCI_V0_BAR0_SPROM_SIZE,
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.res = { SYS_RES_MEMORY, PCIR_BAR(0) }
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},
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/*
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* bar0+0x1800: pci core registers.
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*
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* Does not include the SSB CFG registers found at the end of
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* the 4K core register block; these are mapped non-contigiously
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* by the next entry.
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*/
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{
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.win_type = BHNDB_REGWIN_T_CORE,
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.win_offset = BHNDB_PCI_V0_BAR0_PCIREG_OFFSET,
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.win_size = BHNDB_PCI_V0_BAR0_PCIREG_SIZE,
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.d.core = {
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.class = BHND_DEVCLASS_PCI,
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.unit = 0,
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.port = 0,
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.region = 0,
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.port_type = BHND_PORT_DEVICE,
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},
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.res = { SYS_RES_MEMORY, PCIR_BAR(0) }
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},
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/* bar0+0x1E00: pci core (SSB CFG registers) */
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{
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.win_type = BHNDB_REGWIN_T_CORE,
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.win_offset = BHNDB_PCI_V0_BAR0_PCISB_OFFSET ,
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.win_size = BHNDB_PCI_V0_BAR0_PCISB_SIZE,
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.d.core = {
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.class = BHND_DEVCLASS_PCI,
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.unit = 0,
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.port = 0,
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.region = 0,
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.offset = BHNDB_PCI_V0_BAR0_PCISB_COREOFF,
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.port_type = BHND_PORT_DEVICE
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},
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.res = { SYS_RES_MEMORY, PCIR_BAR(0) }
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},
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BHNDB_REGWIN_TABLE_END
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},
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.dma_translations = (const struct bhnd_dma_translation[]) {
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{
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.base_addr = BHND_PCI_DMA32_TRANSLATION,
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.addr_mask = ~BHND_PCI_DMA32_MASK,
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.addrext_mask = BHND_PCI_DMA32_MASK
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},
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BHND_DMA_TRANSLATION_TABLE_END
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}
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};
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/**
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* PCI_V1 (PCI-only) hardware configuration (PCI version)
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*
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* Applies to:
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* - PCI (cid=0x804, revision >= 13)
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*/
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static const struct bhndb_hwcfg bhndb_pci_hwcfg_v1_pci = {
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.resource_specs = (const struct resource_spec[]) {
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{ SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE },
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{ -1, 0, 0 }
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},
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.register_windows = (const struct bhndb_regwin[]) {
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/* bar0+0x0000: configurable backplane window */
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{
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.win_type = BHNDB_REGWIN_T_DYN,
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.win_offset = BHNDB_PCI_V1_BAR0_WIN0_OFFSET,
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.win_size = BHNDB_PCI_V1_BAR0_WIN0_SIZE,
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.d.dyn = {
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.cfg_offset = BHNDB_PCI_V1_BAR0_WIN0_CONTROL
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},
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.res = { SYS_RES_MEMORY, PCIR_BAR(0) }
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},
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/* bar0+0x1000: sprom shadow */
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{
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.win_type = BHNDB_REGWIN_T_SPROM,
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.win_offset = BHNDB_PCI_V1_BAR0_SPROM_OFFSET,
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.win_size = BHNDB_PCI_V1_BAR0_SPROM_SIZE,
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.res = { SYS_RES_MEMORY, PCIR_BAR(0) }
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},
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/* bar0+0x2000: pci core registers */
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{
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.win_type = BHNDB_REGWIN_T_CORE,
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.win_offset = BHNDB_PCI_V1_BAR0_PCIREG_OFFSET,
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.win_size = BHNDB_PCI_V1_BAR0_PCIREG_SIZE,
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.d.core = {
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.class = BHND_DEVCLASS_PCI,
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.unit = 0,
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.port = 0,
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.region = 0,
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.port_type = BHND_PORT_DEVICE
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},
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.res = { SYS_RES_MEMORY, PCIR_BAR(0) }
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},
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/* bar0+0x3000: chipc core registers */
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{
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.win_type = BHNDB_REGWIN_T_CORE,
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.win_offset = BHNDB_PCI_V1_BAR0_CCREGS_OFFSET,
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.win_size = BHNDB_PCI_V1_BAR0_CCREGS_SIZE,
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.d.core = {
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.class = BHND_DEVCLASS_CC,
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.unit = 0,
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.port = 0,
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.region = 0,
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.port_type = BHND_PORT_DEVICE
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},
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.res = { SYS_RES_MEMORY, PCIR_BAR(0) }
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},
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BHNDB_REGWIN_TABLE_END
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},
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.dma_translations = (const struct bhnd_dma_translation[]) {
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{
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.base_addr = BHND_PCI_DMA32_TRANSLATION,
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.addr_mask = ~BHND_PCI_DMA32_MASK,
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.addrext_mask = BHND_PCI_DMA32_MASK
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},
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BHND_DMA_TRANSLATION_TABLE_END
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}
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};
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/**
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* PCI_V1 hardware configuration (PCIE version).
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*
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* Applies to:
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* - PCIE (cid=0x820) with ChipCommon (revision <= 31)
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*/
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static const struct bhndb_hwcfg bhndb_pci_hwcfg_v1_pcie = {
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.resource_specs = (const struct resource_spec[]) {
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{ SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE },
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{ -1, 0, 0 }
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},
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.register_windows = (const struct bhndb_regwin[]) {
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/* bar0+0x0000: configurable backplane window */
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{
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.win_type = BHNDB_REGWIN_T_DYN,
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.win_offset = BHNDB_PCI_V1_BAR0_WIN0_OFFSET,
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.win_size = BHNDB_PCI_V1_BAR0_WIN0_SIZE,
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.d.dyn = {
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.cfg_offset = BHNDB_PCI_V1_BAR0_WIN0_CONTROL
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},
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.res = { SYS_RES_MEMORY, PCIR_BAR(0) }
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|
},
|
|
|
|
/* bar0+0x1000: sprom shadow */
|
|
{
|
|
.win_type = BHNDB_REGWIN_T_SPROM,
|
|
.win_offset = BHNDB_PCI_V1_BAR0_SPROM_OFFSET,
|
|
.win_size = BHNDB_PCI_V1_BAR0_SPROM_SIZE,
|
|
.res = { SYS_RES_MEMORY, PCIR_BAR(0) }
|
|
},
|
|
|
|
/* bar0+0x2000: pci core registers */
|
|
{
|
|
.win_type = BHNDB_REGWIN_T_CORE,
|
|
.win_offset = BHNDB_PCI_V1_BAR0_PCIREG_OFFSET,
|
|
.win_size = BHNDB_PCI_V1_BAR0_PCIREG_SIZE,
|
|
.d.core = {
|
|
.class = BHND_DEVCLASS_PCIE,
|
|
.unit = 0,
|
|
.port = 0,
|
|
.region = 0,
|
|
.port_type = BHND_PORT_DEVICE
|
|
},
|
|
.res = { SYS_RES_MEMORY, PCIR_BAR(0) }
|
|
},
|
|
|
|
/* bar0+0x3000: chipc core registers */
|
|
{
|
|
.win_type = BHNDB_REGWIN_T_CORE,
|
|
.win_offset = BHNDB_PCI_V1_BAR0_CCREGS_OFFSET,
|
|
.win_size = BHNDB_PCI_V1_BAR0_CCREGS_SIZE,
|
|
.d.core = {
|
|
.class = BHND_DEVCLASS_CC,
|
|
.unit = 0,
|
|
.port = 0,
|
|
.region = 0,
|
|
.port_type = BHND_PORT_DEVICE
|
|
},
|
|
.res = { SYS_RES_MEMORY, PCIR_BAR(0) }
|
|
},
|
|
|
|
BHNDB_REGWIN_TABLE_END
|
|
},
|
|
|
|
.dma_translations = (const struct bhnd_dma_translation[]) {
|
|
{
|
|
.base_addr = BHND_PCIE_DMA32_TRANSLATION,
|
|
.addr_mask = ~BHND_PCIE_DMA32_MASK,
|
|
.addrext_mask = BHND_PCIE_DMA32_MASK
|
|
},
|
|
{
|
|
.base_addr = BHND_PCIE_DMA64_TRANSLATION,
|
|
.addr_mask = ~BHND_PCIE_DMA64_MASK,
|
|
.addrext_mask = BHND_PCIE_DMA64_MASK
|
|
},
|
|
BHND_DMA_TRANSLATION_TABLE_END
|
|
}
|
|
};
|
|
|
|
/**
|
|
* PCI_V2 hardware configuration.
|
|
*
|
|
* Applies to:
|
|
* - PCIE (cid=0x820) with ChipCommon (revision >= 32)
|
|
*/
|
|
static const struct bhndb_hwcfg bhndb_pci_hwcfg_v2 = {
|
|
.resource_specs = (const struct resource_spec[]) {
|
|
{ SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE },
|
|
{ -1, 0, 0 }
|
|
},
|
|
|
|
.register_windows = (const struct bhndb_regwin[]) {
|
|
/* bar0+0x0000: configurable backplane window */
|
|
{
|
|
.win_type = BHNDB_REGWIN_T_DYN,
|
|
.win_offset = BHNDB_PCI_V2_BAR0_WIN0_OFFSET,
|
|
.win_size = BHNDB_PCI_V2_BAR0_WIN0_SIZE,
|
|
.d.dyn = {
|
|
.cfg_offset = BHNDB_PCI_V2_BAR0_WIN0_CONTROL,
|
|
},
|
|
.res = { SYS_RES_MEMORY, PCIR_BAR(0) }
|
|
},
|
|
|
|
/* bar0+0x1000: configurable backplane window */
|
|
{
|
|
.win_type = BHNDB_REGWIN_T_DYN,
|
|
.win_offset = BHNDB_PCI_V2_BAR0_WIN1_OFFSET,
|
|
.win_size = BHNDB_PCI_V2_BAR0_WIN1_SIZE,
|
|
.d.dyn = {
|
|
.cfg_offset = BHNDB_PCI_V2_BAR0_WIN1_CONTROL,
|
|
},
|
|
.res = { SYS_RES_MEMORY, PCIR_BAR(0) }
|
|
},
|
|
|
|
/* bar0+0x2000: pcie core registers */
|
|
{
|
|
.win_type = BHNDB_REGWIN_T_CORE,
|
|
.win_offset = BHNDB_PCI_V2_BAR0_PCIREG_OFFSET,
|
|
.win_size = BHNDB_PCI_V2_BAR0_PCIREG_SIZE,
|
|
.d.core = {
|
|
.class = BHND_DEVCLASS_PCIE,
|
|
.unit = 0,
|
|
.port = 0,
|
|
.region = 0,
|
|
.port_type = BHND_PORT_DEVICE
|
|
},
|
|
.res = { SYS_RES_MEMORY, PCIR_BAR(0) }
|
|
},
|
|
|
|
/* bar0+0x3000: chipc core registers */
|
|
{
|
|
.win_type = BHNDB_REGWIN_T_CORE,
|
|
.win_offset = BHNDB_PCI_V2_BAR0_CCREGS_OFFSET,
|
|
.win_size = BHNDB_PCI_V2_BAR0_CCREGS_SIZE,
|
|
.d.core = {
|
|
.class = BHND_DEVCLASS_CC,
|
|
.unit = 0,
|
|
.port = 0,
|
|
.region = 0,
|
|
.port_type = BHND_PORT_DEVICE
|
|
},
|
|
.res = { SYS_RES_MEMORY, PCIR_BAR(0) }
|
|
},
|
|
|
|
BHNDB_REGWIN_TABLE_END
|
|
},
|
|
|
|
.dma_translations = (const struct bhnd_dma_translation[]) {
|
|
{
|
|
.base_addr = BHND_PCIE_DMA32_TRANSLATION,
|
|
.addr_mask = ~BHND_PCIE_DMA32_MASK,
|
|
.addrext_mask = BHND_PCIE_DMA32_MASK
|
|
},
|
|
{
|
|
.base_addr = BHND_PCIE_DMA64_TRANSLATION,
|
|
.addr_mask = ~BHND_PCIE_DMA64_MASK,
|
|
.addrext_mask = BHND_PCIE_DMA64_MASK
|
|
},
|
|
BHND_DMA_TRANSLATION_TABLE_END
|
|
}
|
|
};
|
|
|
|
/**
|
|
* PCI_V3 hardware configuration.
|
|
*
|
|
* Applies to:
|
|
* - PCIE2 (cid=0x83c)
|
|
*/
|
|
static const struct bhndb_hwcfg bhndb_pci_hwcfg_v3 = {
|
|
.resource_specs = (const struct resource_spec[]) {
|
|
{ SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE },
|
|
{ -1, 0, 0 }
|
|
},
|
|
|
|
.register_windows = (const struct bhndb_regwin[]) {
|
|
/* bar0+0x0000: configurable backplane window */
|
|
{
|
|
.win_type = BHNDB_REGWIN_T_DYN,
|
|
.win_offset = BHNDB_PCI_V3_BAR0_WIN0_OFFSET,
|
|
.win_size = BHNDB_PCI_V3_BAR0_WIN0_SIZE,
|
|
.d.dyn = {
|
|
.cfg_offset = BHNDB_PCI_V3_BAR0_WIN0_CONTROL,
|
|
},
|
|
.res = { SYS_RES_MEMORY, PCIR_BAR(0) }
|
|
},
|
|
|
|
/* bar0+0x1000: configurable backplane window */
|
|
{
|
|
.win_type = BHNDB_REGWIN_T_DYN,
|
|
.win_offset = BHNDB_PCI_V3_BAR0_WIN1_OFFSET,
|
|
.win_size = BHNDB_PCI_V3_BAR0_WIN1_SIZE,
|
|
.d.dyn = {
|
|
.cfg_offset = BHNDB_PCI_V3_BAR0_WIN1_CONTROL,
|
|
},
|
|
.res = { SYS_RES_MEMORY, PCIR_BAR(0) }
|
|
},
|
|
|
|
/* bar0+0x2000: pcie core registers */
|
|
{
|
|
.win_type = BHNDB_REGWIN_T_CORE,
|
|
.win_offset = BHNDB_PCI_V3_BAR0_PCIREG_OFFSET,
|
|
.win_size = BHNDB_PCI_V3_BAR0_PCIREG_SIZE,
|
|
.d.core = {
|
|
.class = BHND_DEVCLASS_PCIE,
|
|
.unit = 0,
|
|
.port = 0,
|
|
.region = 0,
|
|
.port_type = BHND_PORT_DEVICE
|
|
},
|
|
.res = { SYS_RES_MEMORY, PCIR_BAR(0) }
|
|
},
|
|
|
|
/* bar0+0x3000: chipc core registers */
|
|
{
|
|
.win_type = BHNDB_REGWIN_T_CORE,
|
|
.win_offset = BHNDB_PCI_V3_BAR0_CCREGS_OFFSET,
|
|
.win_size = BHNDB_PCI_V3_BAR0_CCREGS_SIZE,
|
|
.d.core = {
|
|
.class = BHND_DEVCLASS_CC,
|
|
.unit = 0,
|
|
.port = 0,
|
|
.region = 0,
|
|
.port_type = BHND_PORT_DEVICE
|
|
},
|
|
.res = { SYS_RES_MEMORY, PCIR_BAR(0) }
|
|
},
|
|
|
|
BHNDB_REGWIN_TABLE_END
|
|
},
|
|
|
|
.dma_translations = (const struct bhnd_dma_translation[]) {
|
|
{
|
|
.base_addr = BHND_PCIE2_DMA64_TRANSLATION,
|
|
.addr_mask = ~BHND_PCIE2_DMA64_MASK,
|
|
.addrext_mask = BHND_PCIE_DMA64_MASK
|
|
},
|
|
BHND_DMA_TRANSLATION_TABLE_END
|
|
}
|
|
};
|