eaa5fb4b80
Very early (PCI_V0) Broadcom PCI Wi-Fi chipsets have a few quirks when compared to later PCI(e) core revisions: - The standard static BAR0 mapping of the PCI core registers is discontiguous, with siba's cfg0 register block mapped distinctly from the other core registers. - No dedicated ChipCommon register mapping is provided; instead, the single configurable register window must be used to access both ChipCommon and D11 core registers. The D11 core's operational semantics guarantee the safety of -- after disabling interrupts -- borrowing the single dynamic register window to perform the few ChipCommon operations required by a driver. To support these early PCI devices: - Allow defining multiple discontiguous BHNDB_REGWIN_T_CORE register windows that map a single port/region, and producing bridged resource allocations backed by those discontiguous windows. - Support stealing existing register window allocations to fulfill indirect bhnd(4) bus I/O requests within address ranges tagged with BHNDB_ALLOC_FULFILL_ON_OVERCOMMIT. - Fix an inverted test of bhndb_is_pcie_attached() that disabled PCI-only clock bring-up required by these devices. Approved by: adrian (mentor, implicit) Sponsored by: The FreeBSD Foundation
193 lines
6.6 KiB
C
193 lines
6.6 KiB
C
/*-
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* Copyright (c) 2015-2016 Landon Fuller <landon@landonf.org>
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* Copyright (c) 2017 The FreeBSD Foundation
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* All rights reserved.
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*
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* Portions of this software were developed by Landon Fuller
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* under sponsorship from the FreeBSD Foundation.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer,
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* without modification.
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* 2. Redistributions in binary form must reproduce at minimum a disclaimer
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* similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
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* redistribution must be conditioned upon including a substantially
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* similar Disclaimer requirement for further binary redistribution.
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*
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* NO WARRANTY
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
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* AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
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* OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
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* IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGES.
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*
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* $FreeBSD$
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*/
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#ifndef _BHND_BHNDBVAR_H_
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#define _BHND_BHNDBVAR_H_
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#include <sys/param.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/lock.h>
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#include <sys/malloc.h>
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#include <sys/mutex.h>
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#include <sys/rman.h>
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#include <dev/bhnd/bhndvar.h>
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#include "bhndb.h"
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#include "bhndb_if.h"
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/*
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* Definitions shared by bhndb(4) driver implementations.
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*/
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DECLARE_CLASS(bhndb_driver);
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/* forward declarations */
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struct bhndb_intr_isrc;
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struct bhndb_resources;
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struct bhndb_host_resources;
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int bhndb_attach(device_t dev,
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struct bhnd_chipid *cid,
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struct bhnd_core_info *cores, u_int ncores,
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struct bhnd_core_info *bridge_core,
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bhnd_erom_class_t *erom_class);
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int bhndb_generic_probe(device_t dev);
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int bhndb_generic_detach(device_t dev);
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int bhndb_generic_suspend(device_t dev);
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int bhndb_generic_resume(device_t dev);
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int bhndb_generic_init_full_config(device_t dev,
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device_t child,
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const struct bhndb_hw_priority *hw_prio_table);
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int bhnd_generic_br_suspend_child(device_t dev,
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device_t child);
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int bhnd_generic_br_resume_child(device_t dev,
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device_t child);
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int bhndb_find_hostb_core(
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struct bhnd_core_info *cores, u_int ncores,
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bhnd_devclass_t bridge_devclass,
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struct bhnd_core_info *core);
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struct bhndb_intr_isrc *bhndb_alloc_intr_isrc(device_t owner, int rid,
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rman_res_t start, rman_res_t end,
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rman_res_t count, u_int flags);
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void bhndb_free_intr_isrc(
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struct bhndb_intr_isrc *isrc);
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int bhndb_alloc_host_resources(
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struct bhndb_host_resources **resources,
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device_t dev, device_t parent_dev,
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const struct bhndb_hwcfg *hwcfg);
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void bhndb_release_host_resources(
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struct bhndb_host_resources *resources);
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struct resource *bhndb_host_resource_for_range(
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struct bhndb_host_resources *resources,
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int type, rman_res_t start,
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rman_res_t count);
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struct resource *bhndb_host_resource_for_regwin(
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struct bhndb_host_resources *resources,
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const struct bhndb_regwin *win);
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size_t bhndb_regwin_count(
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const struct bhndb_regwin *table,
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bhndb_regwin_type_t type);
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const struct bhndb_regwin *bhndb_regwin_find_type(
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const struct bhndb_regwin *table,
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bhndb_regwin_type_t type,
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bus_size_t min_size);
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const struct bhndb_regwin *bhndb_regwin_find_core(
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const struct bhndb_regwin *table,
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bhnd_devclass_t class, int unit,
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bhnd_port_type port_type, u_int port,
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u_int region, bus_size_t offset,
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bus_size_t min_size);
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const struct bhndb_regwin *bhndb_regwin_find_best(
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const struct bhndb_regwin *table,
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bhnd_devclass_t class, int unit,
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bhnd_port_type port_type, u_int port,
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u_int region, bus_size_t offset,
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bus_size_t min_size);
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bool bhndb_regwin_match_core(
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const struct bhndb_regwin *regw,
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struct bhnd_core_info *core);
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/**
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* bhndb child address space. Children either operate in the bridged
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* SoC address space, or within the address space mapped to the host
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* device (e.g. the PCI BAR(s)).
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*/
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typedef enum {
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BHNDB_ADDRSPACE_BRIDGED, /**< bridged (SoC) address space */
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BHNDB_ADDRSPACE_NATIVE /**< host address space */
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} bhndb_addrspace;
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/** bhndb child instance state */
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struct bhndb_devinfo {
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bhndb_addrspace addrspace; /**< child address space. */
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struct resource_list resources; /**< child resources. */
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};
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/**
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* Host interrupt source to which bridged interrupts may be routed.
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*/
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struct bhndb_intr_isrc {
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device_t is_owner; /**< host device (e.g. the pci device). */
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struct resource *is_res; /**< irq resource */
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int is_rid; /**< irq resource ID */
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};
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/**
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* Host resources allocated for a bridge hardware configuration.
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*/
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struct bhndb_host_resources {
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device_t owner; /**< device owning the allocated resources */
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const struct bhndb_hwcfg *cfg; /**< bridge hardware configuration */
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struct resource_spec *resource_specs; /**< resource specification table */
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struct resource **resources; /**< allocated resource table */
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bus_dma_tag_t *dma_tags; /**< DMA tags for all hwcfg DMA translations, or NULL
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if DMA is not supported */
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size_t num_dma_tags; /**< DMA tag count */
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};
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/**
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* bhndb driver instance state. Must be first member of all subclass
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* softc structures.
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*/
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struct bhndb_softc {
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device_t dev; /**< bridge device */
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struct bhnd_chipid chipid; /**< chip identification */
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struct bhnd_core_info bridge_core; /**< bridge core info */
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device_t parent_dev; /**< parent device */
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device_t bus_dev; /**< child bhnd(4) bus */
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struct bhnd_service_registry services; /**< local service registry */
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struct mtx sc_mtx; /**< resource lock. */
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struct bhndb_resources *bus_res; /**< bus resource state */
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STAILQ_HEAD(,bhndb_intr_handler) bus_intrs; /**< attached child interrupt handlers */
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};
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#endif /* _BHND_BHNDBVAR_H_ */
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