718cf2ccb9
Mainly focus on files that use BSD 2-Clause license, however the tool I was using misidentified many licenses so this was mostly a manual - error prone - task. The Software Package Data Exchange (SPDX) group provides a specification to make it easier for automated tools to detect and summarize well known opensource licenses. We are gradually adopting the specification, noting that the tags are considered only advisory and do not, in any way, superceed or replace the license texts.
1013 lines
30 KiB
C
1013 lines
30 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2002-2007 Neterion, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef XGE_HAL_DEVICE_H
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#define XGE_HAL_DEVICE_H
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#include <dev/nxge/include/xge-os-pal.h>
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#include <dev/nxge/include/xge-queue.h>
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#include <dev/nxge/include/xgehal-event.h>
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#include <dev/nxge/include/xgehal-config.h>
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#include <dev/nxge/include/xgehal-regs.h>
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#include <dev/nxge/include/xgehal-channel.h>
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#include <dev/nxge/include/xgehal-stats.h>
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#include <dev/nxge/include/xgehal-ring.h>
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__EXTERN_BEGIN_DECLS
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#define XGE_HAL_VPD_LENGTH 80
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#define XGE_HAL_CARD_XENA_VPD_ADDR 0x50
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#define XGE_HAL_CARD_HERC_VPD_ADDR 0x80
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#define XGE_HAL_VPD_READ_COMPLETE 0x80
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#define XGE_HAL_VPD_BUFFER_SIZE 128
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#define XGE_HAL_DEVICE_XMSI_WAIT_MAX_MILLIS 500
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#define XGE_HAL_DEVICE_CMDMEM_WAIT_MAX_MILLIS 500
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#define XGE_HAL_DEVICE_QUIESCENT_WAIT_MAX_MILLIS 500
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#define XGE_HAL_DEVICE_FAULT_WAIT_MAX_MILLIS 50
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#define XGE_HAL_DEVICE_RESET_WAIT_MAX_MILLIS 250
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#define XGE_HAL_DEVICE_SPDM_READY_WAIT_MAX_MILLIS 250 /* TODO */
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#define XGE_HAL_MAGIC 0x12345678
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#define XGE_HAL_DEAD 0xDEADDEAD
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#define XGE_HAL_DUMP_BUF_SIZE 0x4000
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#define XGE_HAL_LRO_MAX_BUCKETS 32
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/**
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* enum xge_hal_card_e - Xframe adapter type.
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* @XGE_HAL_CARD_UNKNOWN: Unknown device.
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* @XGE_HAL_CARD_XENA: Xframe I device.
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* @XGE_HAL_CARD_HERC: Xframe II (PCI-266Mhz) device.
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* @XGE_HAL_CARD_TITAN: Xframe ER (PCI-266Mhz) device.
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*
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* Enumerates Xframe adapter types. The corresponding PCI device
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* IDs are listed in the file xgehal-defs.h.
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* (See XGE_PCI_DEVICE_ID_XENA_1, etc.)
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*
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* See also: xge_hal_device_check_id().
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*/
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typedef enum xge_hal_card_e {
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XGE_HAL_CARD_UNKNOWN = 0,
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XGE_HAL_CARD_XENA = 1,
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XGE_HAL_CARD_HERC = 2,
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XGE_HAL_CARD_TITAN = 3,
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} xge_hal_card_e;
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/**
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* struct xge_hal_device_attr_t - Device memory spaces.
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* @regh0: BAR0 mapped memory handle (Solaris), or simply PCI device @pdev
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* (Linux and the rest.)
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* @regh1: BAR1 mapped memory handle. Same comment as above.
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* @bar0: BAR0 virtual address.
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* @bar1: BAR1 virtual address.
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* @irqh: IRQ handle (Solaris).
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* @cfgh: Configuration space handle (Solaris), or PCI device @pdev (Linux).
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* @pdev: PCI device object.
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*
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* Device memory spaces. Includes configuration, BAR0, BAR1, etc. per device
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* mapped memories. Also, includes a pointer to OS-specific PCI device object.
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*/
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typedef struct xge_hal_device_attr_t {
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pci_reg_h regh0;
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pci_reg_h regh1;
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pci_reg_h regh2;
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char *bar0;
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char *bar1;
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char *bar2;
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pci_irq_h irqh;
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pci_cfg_h cfgh;
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pci_dev_h pdev;
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} xge_hal_device_attr_t;
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/**
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* enum xge_hal_device_link_state_e - Link state enumeration.
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* @XGE_HAL_LINK_NONE: Invalid link state.
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* @XGE_HAL_LINK_DOWN: Link is down.
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* @XGE_HAL_LINK_UP: Link is up.
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*
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*/
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typedef enum xge_hal_device_link_state_e {
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XGE_HAL_LINK_NONE,
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XGE_HAL_LINK_DOWN,
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XGE_HAL_LINK_UP
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} xge_hal_device_link_state_e;
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/**
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* enum xge_hal_pci_mode_e - PIC bus speed and mode specific enumeration.
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* @XGE_HAL_PCI_33MHZ_MODE: 33 MHZ pci mode.
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* @XGE_HAL_PCI_66MHZ_MODE: 66 MHZ pci mode.
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* @XGE_HAL_PCIX_M1_66MHZ_MODE: PCIX M1 66MHZ mode.
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* @XGE_HAL_PCIX_M1_100MHZ_MODE: PCIX M1 100MHZ mode.
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* @XGE_HAL_PCIX_M1_133MHZ_MODE: PCIX M1 133MHZ mode.
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* @XGE_HAL_PCIX_M2_66MHZ_MODE: PCIX M2 66MHZ mode.
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* @XGE_HAL_PCIX_M2_100MHZ_MODE: PCIX M2 100MHZ mode.
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* @XGE_HAL_PCIX_M2_133MHZ_MODE: PCIX M3 133MHZ mode.
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* @XGE_HAL_PCIX_M1_RESERVED: PCIX M1 reserved mode.
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* @XGE_HAL_PCIX_M1_66MHZ_NS: PCIX M1 66MHZ mode not supported.
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* @XGE_HAL_PCIX_M1_100MHZ_NS: PCIX M1 100MHZ mode not supported.
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* @XGE_HAL_PCIX_M1_133MHZ_NS: PCIX M1 133MHZ not supported.
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* @XGE_HAL_PCIX_M2_RESERVED: PCIX M2 reserved.
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* @XGE_HAL_PCIX_533_RESERVED: PCIX 533 reserved.
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* @XGE_HAL_PCI_BASIC_MODE: PCI basic mode, XENA specific value.
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* @XGE_HAL_PCIX_BASIC_MODE: PCIX basic mode, XENA specific value.
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* @XGE_HAL_PCI_INVALID_MODE: Invalid PCI or PCIX mode.
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*
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*/
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typedef enum xge_hal_pci_mode_e {
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XGE_HAL_PCI_33MHZ_MODE = 0x0,
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XGE_HAL_PCI_66MHZ_MODE = 0x1,
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XGE_HAL_PCIX_M1_66MHZ_MODE = 0x2,
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XGE_HAL_PCIX_M1_100MHZ_MODE = 0x3,
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XGE_HAL_PCIX_M1_133MHZ_MODE = 0x4,
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XGE_HAL_PCIX_M2_66MHZ_MODE = 0x5,
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XGE_HAL_PCIX_M2_100MHZ_MODE = 0x6,
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XGE_HAL_PCIX_M2_133MHZ_MODE = 0x7,
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XGE_HAL_PCIX_M1_RESERVED = 0x8,
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XGE_HAL_PCIX_M1_66MHZ_NS = 0xA,
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XGE_HAL_PCIX_M1_100MHZ_NS = 0xB,
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XGE_HAL_PCIX_M1_133MHZ_NS = 0xC,
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XGE_HAL_PCIX_M2_RESERVED = 0xD,
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XGE_HAL_PCIX_533_RESERVED = 0xE,
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XGE_HAL_PCI_BASIC_MODE = 0x10,
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XGE_HAL_PCIX_BASIC_MODE = 0x11,
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XGE_HAL_PCI_INVALID_MODE = 0x12,
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} xge_hal_pci_mode_e;
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/**
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* enum xge_hal_pci_bus_frequency_e - PCI bus frequency enumeration.
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* @XGE_HAL_PCI_BUS_FREQUENCY_33MHZ: PCI bus frequency 33MHZ
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* @XGE_HAL_PCI_BUS_FREQUENCY_66MHZ: PCI bus frequency 66MHZ
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* @XGE_HAL_PCI_BUS_FREQUENCY_100MHZ: PCI bus frequency 100MHZ
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* @XGE_HAL_PCI_BUS_FREQUENCY_133MHZ: PCI bus frequency 133MHZ
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* @XGE_HAL_PCI_BUS_FREQUENCY_200MHZ: PCI bus frequency 200MHZ
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* @XGE_HAL_PCI_BUS_FREQUENCY_250MHZ: PCI bus frequency 250MHZ
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* @XGE_HAL_PCI_BUS_FREQUENCY_266MHZ: PCI bus frequency 266MHZ
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* @XGE_HAL_PCI_BUS_FREQUENCY_UNKNOWN: Unrecognized PCI bus frequency value.
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*
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*/
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typedef enum xge_hal_pci_bus_frequency_e {
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XGE_HAL_PCI_BUS_FREQUENCY_33MHZ = 33,
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XGE_HAL_PCI_BUS_FREQUENCY_66MHZ = 66,
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XGE_HAL_PCI_BUS_FREQUENCY_100MHZ = 100,
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XGE_HAL_PCI_BUS_FREQUENCY_133MHZ = 133,
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XGE_HAL_PCI_BUS_FREQUENCY_200MHZ = 200,
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XGE_HAL_PCI_BUS_FREQUENCY_250MHZ = 250,
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XGE_HAL_PCI_BUS_FREQUENCY_266MHZ = 266,
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XGE_HAL_PCI_BUS_FREQUENCY_UNKNOWN = 0
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} xge_hal_pci_bus_frequency_e;
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/**
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* enum xge_hal_pci_bus_width_e - PCI bus width enumeration.
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* @XGE_HAL_PCI_BUS_WIDTH_64BIT: 64 bit bus width.
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* @XGE_HAL_PCI_BUS_WIDTH_32BIT: 32 bit bus width.
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* @XGE_HAL_PCI_BUS_WIDTH_UNKNOWN: unknown bus width.
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*
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*/
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typedef enum xge_hal_pci_bus_width_e {
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XGE_HAL_PCI_BUS_WIDTH_64BIT = 0,
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XGE_HAL_PCI_BUS_WIDTH_32BIT = 1,
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XGE_HAL_PCI_BUS_WIDTH_UNKNOWN = 2,
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} xge_hal_pci_bus_width_e;
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#if defined (XGE_HAL_CONFIG_LRO)
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#define IP_TOTAL_LENGTH_OFFSET 2
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#define IP_FAST_PATH_HDR_MASK 0x45
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#define TCP_FAST_PATH_HDR_MASK1 0x50
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#define TCP_FAST_PATH_HDR_MASK2 0x10
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#define TCP_FAST_PATH_HDR_MASK3 0x18
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#define IP_SOURCE_ADDRESS_OFFSET 12
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#define IP_DESTINATION_ADDRESS_OFFSET 16
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#define TCP_DESTINATION_PORT_OFFSET 2
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#define TCP_SOURCE_PORT_OFFSET 0
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#define TCP_DATA_OFFSET_OFFSET 12
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#define TCP_WINDOW_OFFSET 14
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#define TCP_SEQUENCE_NUMBER_OFFSET 4
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#define TCP_ACKNOWLEDGEMENT_NUMBER_OFFSET 8
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typedef struct tcplro {
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u16 source;
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u16 dest;
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u32 seq;
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u32 ack_seq;
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u8 doff_res;
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u8 ctrl;
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u16 window;
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u16 check;
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u16 urg_ptr;
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} tcplro_t;
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typedef struct iplro {
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u8 version_ihl;
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u8 tos;
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u16 tot_len;
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u16 id;
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u16 frag_off;
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u8 ttl;
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u8 protocol;
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u16 check;
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u32 saddr;
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u32 daddr;
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/*The options start here. */
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} iplro_t;
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/*
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* LRO object, one per each LRO session.
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*/
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typedef struct lro {
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/* non-linear: contains scatter-gather list of
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xframe-mapped received buffers */
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OS_NETSTACK_BUF os_buf;
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OS_NETSTACK_BUF os_buf_end;
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/* link layer header of the first frame;
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remains intack throughout the processing */
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u8 *ll_hdr;
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/* IP header - gets _collapsed_ */
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iplro_t *ip_hdr;
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/* transport header - gets _collapsed_ */
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tcplro_t *tcp_hdr;
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/* Next tcp sequence number */
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u32 tcp_next_seq_num;
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/* Current tcp seq & ack */
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u32 tcp_seq_num;
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u32 tcp_ack_num;
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/* total number of accumulated (so far) frames */
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int sg_num;
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/* total data length */
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int total_length;
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/* receive side hash value, available from Hercules */
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u32 rth_value;
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/* In use */
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u8 in_use;
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/* Total length of the fragments clubbed with the inital frame */
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u32 frags_len;
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/* LRO frame contains time stamp, if (ts_off != -1) */
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int ts_off;
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} lro_t;
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#endif
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/*
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* xge_hal_spdm_entry_t
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*
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* Represents a single spdm entry in the SPDM table.
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*/
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typedef struct xge_hal_spdm_entry_t {
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xge_hal_ipaddr_t src_ip;
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xge_hal_ipaddr_t dst_ip;
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u32 jhash_value;
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u16 l4_sp;
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u16 l4_dp;
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u16 spdm_entry;
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u8 in_use;
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u8 is_tcp;
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u8 is_ipv4;
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u8 tgt_queue;
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} xge_hal_spdm_entry_t;
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#if defined(XGE_HAL_CONFIG_LRO)
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typedef struct {
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lro_t lro_pool[XGE_HAL_LRO_MAX_BUCKETS];
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int lro_next_idx;
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lro_t *lro_recent;
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} xge_hal_lro_desc_t;
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#endif
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/*
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* xge_hal_vpd_data_t
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*
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* Represents vpd capabilty structure
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*/
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typedef struct xge_hal_vpd_data_t {
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u8 product_name[XGE_HAL_VPD_LENGTH];
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u8 serial_num[XGE_HAL_VPD_LENGTH];
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} xge_hal_vpd_data_t;
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/*
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* xge_hal_device_t
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*
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* HAL device object. Represents Xframe.
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*/
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typedef struct {
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unsigned int magic;
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pci_reg_h regh0;
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pci_reg_h regh1;
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pci_reg_h regh2;
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char *bar0;
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char *isrbar0;
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char *bar1;
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char *bar2;
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pci_irq_h irqh;
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pci_cfg_h cfgh;
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pci_dev_h pdev;
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xge_hal_pci_config_t pci_config_space;
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xge_hal_pci_config_t pci_config_space_bios;
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xge_hal_device_config_t config;
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xge_list_t free_channels;
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xge_list_t fifo_channels;
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xge_list_t ring_channels;
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volatile int is_initialized;
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volatile int terminating;
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xge_hal_stats_t stats;
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macaddr_t macaddr[1];
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xge_queue_h queueh;
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volatile int mcast_refcnt;
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int is_promisc;
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volatile xge_hal_device_link_state_e link_state;
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void *upper_layer_info;
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xge_hal_device_attr_t orig_attr;
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u16 device_id;
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u8 revision;
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int msi_enabled;
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int hw_is_initialized;
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u64 inject_serr;
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u64 inject_ecc;
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u8 inject_bad_tcode;
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int inject_bad_tcode_for_chan_type;
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int reset_needed_after_close;
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int tti_enabled;
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xge_hal_tti_config_t bimodal_tti[XGE_HAL_MAX_RING_NUM];
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int bimodal_timer_val_us;
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int bimodal_urange_a_en;
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int bimodal_intr_cnt;
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char *spdm_mem_base;
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u16 spdm_max_entries;
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xge_hal_spdm_entry_t **spdm_table;
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spinlock_t spdm_lock;
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#if defined(XGE_HAL_CONFIG_LRO)
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xge_hal_lro_desc_t lro_desc[XGE_HAL_MAX_RING_NUM];
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#endif
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spinlock_t xena_post_lock;
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/* bimodal workload stats */
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int irq_workload_rxd[XGE_HAL_MAX_RING_NUM];
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int irq_workload_rxcnt[XGE_HAL_MAX_RING_NUM];
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int irq_workload_rxlen[XGE_HAL_MAX_RING_NUM];
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int irq_workload_txd[XGE_HAL_MAX_FIFO_NUM];
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int irq_workload_txcnt[XGE_HAL_MAX_FIFO_NUM];
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int irq_workload_txlen[XGE_HAL_MAX_FIFO_NUM];
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int mtu_first_time_set;
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u64 rxufca_lbolt;
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u64 rxufca_lbolt_time;
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u64 rxufca_intr_thres;
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char* dump_buf;
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xge_hal_pci_mode_e pci_mode;
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xge_hal_pci_bus_frequency_e bus_frequency;
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xge_hal_pci_bus_width_e bus_width;
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xge_hal_vpd_data_t vpd_data;
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volatile int in_poll;
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u64 msix_vector_table[XGE_HAL_MAX_MSIX_MESSAGES_WITH_ADDR];
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} xge_hal_device_t;
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/* ========================== PRIVATE API ================================= */
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void
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__hal_device_event_queued(void *data, int event_type);
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xge_hal_status_e
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__hal_device_set_swapper(xge_hal_device_t *hldev);
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xge_hal_status_e
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__hal_device_rth_it_configure(xge_hal_device_t *hldev);
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xge_hal_status_e
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__hal_device_rth_spdm_configure(xge_hal_device_t *hldev);
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xge_hal_status_e
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__hal_verify_pcc_idle(xge_hal_device_t *hldev, u64 adp_status);
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xge_hal_status_e
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__hal_device_handle_pic(xge_hal_device_t *hldev, u64 reason);
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xge_hal_status_e
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__hal_read_spdm_entry_line(xge_hal_device_t *hldev, u8 spdm_line,
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u16 spdm_entry, u64 *spdm_line_val);
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void __hal_pio_mem_write32_upper(pci_dev_h pdev, pci_reg_h regh, u32 val,
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void *addr);
|
|
|
|
void __hal_pio_mem_write32_lower(pci_dev_h pdev, pci_reg_h regh, u32 val,
|
|
void *addr);
|
|
void __hal_device_get_vpd_data(xge_hal_device_t *hldev);
|
|
|
|
xge_hal_status_e
|
|
__hal_device_handle_txpic(xge_hal_device_t *hldev, u64 reason);
|
|
|
|
xge_hal_status_e
|
|
__hal_device_handle_txdma(xge_hal_device_t *hldev, u64 reason);
|
|
|
|
xge_hal_status_e
|
|
__hal_device_handle_txmac(xge_hal_device_t *hldev, u64 reason);
|
|
|
|
xge_hal_status_e
|
|
__hal_device_handle_txxgxs(xge_hal_device_t *hldev, u64 reason);
|
|
|
|
xge_hal_status_e
|
|
__hal_device_handle_rxpic(xge_hal_device_t *hldev, u64 reason);
|
|
|
|
xge_hal_status_e
|
|
__hal_device_handle_rxdma(xge_hal_device_t *hldev, u64 reason);
|
|
|
|
xge_hal_status_e
|
|
__hal_device_handle_rxmac(xge_hal_device_t *hldev, u64 reason);
|
|
|
|
xge_hal_status_e
|
|
__hal_device_handle_rxxgxs(xge_hal_device_t *hldev, u64 reason);
|
|
|
|
xge_hal_status_e
|
|
__hal_device_handle_mc(xge_hal_device_t *hldev, u64 reason);
|
|
|
|
xge_hal_status_e
|
|
__hal_device_register_poll(xge_hal_device_t *hldev, u64 *reg, int op, u64 mask,
|
|
int max_millis);
|
|
xge_hal_status_e
|
|
__hal_device_rts_mac_configure(xge_hal_device_t *hldev);
|
|
|
|
xge_hal_status_e
|
|
__hal_device_rts_qos_configure(xge_hal_device_t *hldev);
|
|
|
|
xge_hal_status_e
|
|
__hal_device_rts_port_configure(xge_hal_device_t *hldev);
|
|
|
|
xge_hal_status_e
|
|
__hal_device_rti_configure(xge_hal_device_t *hldev, int runtime);
|
|
|
|
void
|
|
__hal_device_msi_intr_endis(xge_hal_device_t *hldev, int flag);
|
|
|
|
void
|
|
__hal_device_msix_intr_endis(xge_hal_device_t *hldev,
|
|
xge_hal_channel_t *channel, int flag);
|
|
|
|
/* =========================== PUBLIC API ================================= */
|
|
|
|
unsigned int
|
|
__hal_fix_time_ival_herc(xge_hal_device_t *hldev,
|
|
unsigned int time_ival);
|
|
xge_hal_status_e
|
|
xge_hal_rts_rth_itable_set(xge_hal_device_t *hldev, u8 *itable,
|
|
u32 itable_size);
|
|
|
|
void
|
|
xge_hal_rts_rth_set(xge_hal_device_t *hldev, u8 def_q, u64 hash_type,
|
|
u16 bucket_size);
|
|
|
|
void
|
|
xge_hal_rts_rth_init(xge_hal_device_t *hldev);
|
|
|
|
void
|
|
xge_hal_rts_rth_clr(xge_hal_device_t *hldev);
|
|
|
|
void
|
|
xge_hal_rts_rth_start(xge_hal_device_t *hldev);
|
|
|
|
void
|
|
xge_hal_rts_rth_stop(xge_hal_device_t *hldev);
|
|
|
|
void
|
|
xge_hal_device_rts_rth_key_set(xge_hal_device_t *hldev, u8 KeySize, u8 *Key);
|
|
|
|
xge_hal_status_e
|
|
xge_hal_device_rts_mac_enable(xge_hal_device_h devh, int index, macaddr_t macaddr);
|
|
|
|
xge_hal_status_e
|
|
xge_hal_device_rts_mac_disable(xge_hal_device_h devh, int index);
|
|
|
|
int xge_hal_reinitialize_hw(xge_hal_device_t * hldev);
|
|
|
|
xge_hal_status_e xge_hal_fix_rldram_ecc_error(xge_hal_device_t * hldev);
|
|
/**
|
|
* xge_hal_device_rti_reconfigure
|
|
* @hldev: Hal Device
|
|
*/
|
|
static inline xge_hal_status_e
|
|
xge_hal_device_rti_reconfigure(xge_hal_device_t *hldev)
|
|
{
|
|
return __hal_device_rti_configure(hldev, 1);
|
|
}
|
|
|
|
/**
|
|
* xge_hal_device_rts_port_reconfigure
|
|
* @hldev: Hal Device
|
|
*/
|
|
static inline xge_hal_status_e
|
|
xge_hal_device_rts_port_reconfigure(xge_hal_device_t *hldev)
|
|
{
|
|
return __hal_device_rts_port_configure(hldev);
|
|
}
|
|
|
|
/**
|
|
* xge_hal_device_is_initialized - Returns 0 if device is not
|
|
* initialized, non-zero otherwise.
|
|
* @devh: HAL device handle.
|
|
*
|
|
* Returns 0 if device is not initialized, non-zero otherwise.
|
|
*/
|
|
static inline int
|
|
xge_hal_device_is_initialized(xge_hal_device_h devh)
|
|
{
|
|
return ((xge_hal_device_t*)devh)->is_initialized;
|
|
}
|
|
|
|
|
|
/**
|
|
* xge_hal_device_in_poll - non-zero, if xge_hal_device_poll() is executing.
|
|
* @devh: HAL device handle.
|
|
*
|
|
* Returns non-zero if xge_hal_device_poll() is executing, and 0 - otherwise.
|
|
*/
|
|
static inline int
|
|
xge_hal_device_in_poll(xge_hal_device_h devh)
|
|
{
|
|
return ((xge_hal_device_t*)devh)->in_poll;
|
|
}
|
|
|
|
|
|
/**
|
|
* xge_hal_device_inject_ecc - Inject ECC error.
|
|
* @devh: HAL device, pointer to xge_hal_device_t structure.
|
|
* @err_reg: Contains the error register.
|
|
*
|
|
* This function is used to inject ECC error into the driver flow.
|
|
* This facility can be used to test the driver flow in the
|
|
* case of ECC error is reported by the firmware.
|
|
*
|
|
* Returns: void
|
|
* See also: xge_hal_device_inject_serr(),
|
|
* xge_hal_device_inject_bad_tcode()
|
|
*/
|
|
static inline void
|
|
xge_hal_device_inject_ecc(xge_hal_device_h devh, u64 err_reg)
|
|
{
|
|
((xge_hal_device_t*)devh)->inject_ecc = err_reg;
|
|
}
|
|
|
|
|
|
/**
|
|
* xge_hal_device_inject_serr - Inject SERR error.
|
|
* @devh: HAL device, pointer to xge_hal_device_t structure.
|
|
* @err_reg: Contains the error register.
|
|
*
|
|
* This function is used to inject SERR error into the driver flow.
|
|
* This facility can be used to test the driver flow in the
|
|
* case of SERR error is reported by firmware.
|
|
*
|
|
* Returns: void
|
|
* See also: xge_hal_device_inject_ecc(),
|
|
* xge_hal_device_inject_bad_tcode()
|
|
*/
|
|
static inline void
|
|
xge_hal_device_inject_serr(xge_hal_device_h devh, u64 err_reg)
|
|
{
|
|
((xge_hal_device_t*)devh)->inject_serr = err_reg;
|
|
}
|
|
|
|
|
|
/**
|
|
* xge_hal_device_inject_bad_tcode - Inject Bad transfer code.
|
|
* @devh: HAL device, pointer to xge_hal_device_t structure.
|
|
* @chan_type: Channel type (fifo/ring).
|
|
* @t_code: Transfer code.
|
|
*
|
|
* This function is used to inject bad (Tx/Rx Data)transfer code
|
|
* into the driver flow.
|
|
*
|
|
* This facility can be used to test the driver flow in the
|
|
* case of bad transfer code reported by firmware for a Tx/Rx data
|
|
* transfer.
|
|
*
|
|
* Returns: void
|
|
* See also: xge_hal_device_inject_ecc(), xge_hal_device_inject_serr()
|
|
*/
|
|
static inline void
|
|
xge_hal_device_inject_bad_tcode(xge_hal_device_h devh, int chan_type, u8 t_code)
|
|
{
|
|
((xge_hal_device_t*)devh)->inject_bad_tcode_for_chan_type = chan_type;
|
|
((xge_hal_device_t*)devh)->inject_bad_tcode = t_code;
|
|
}
|
|
|
|
void xge_hal_device_msi_enable(xge_hal_device_h devh);
|
|
|
|
/*
|
|
* xge_hal_device_msi_mode - Is MSI enabled?
|
|
* @devh: HAL device handle.
|
|
*
|
|
* Returns 0 if MSI is enabled for the specified device,
|
|
* non-zero otherwise.
|
|
*/
|
|
static inline int
|
|
xge_hal_device_msi_mode(xge_hal_device_h devh)
|
|
{
|
|
return ((xge_hal_device_t*)devh)->msi_enabled;
|
|
}
|
|
|
|
/**
|
|
* xge_hal_device_queue - Get per-device event queue.
|
|
* @devh: HAL device handle.
|
|
*
|
|
* Returns: event queue associated with the specified HAL device.
|
|
*/
|
|
static inline xge_queue_h
|
|
xge_hal_device_queue (xge_hal_device_h devh)
|
|
{
|
|
return ((xge_hal_device_t*)devh)->queueh;
|
|
}
|
|
|
|
/**
|
|
* xge_hal_device_attr - Get original (user-specified) device
|
|
* attributes.
|
|
* @devh: HAL device handle.
|
|
*
|
|
* Returns: original (user-specified) device attributes.
|
|
*/
|
|
static inline xge_hal_device_attr_t*
|
|
xge_hal_device_attr(xge_hal_device_h devh)
|
|
{
|
|
return &((xge_hal_device_t*)devh)->orig_attr;
|
|
}
|
|
|
|
/**
|
|
* xge_hal_device_private_set - Set ULD context.
|
|
* @devh: HAL device handle.
|
|
* @data: pointer to ULD context
|
|
*
|
|
* Use HAL device to set upper-layer driver (ULD) context.
|
|
*
|
|
* See also: xge_hal_device_from_private(), xge_hal_device_private()
|
|
*/
|
|
static inline void
|
|
xge_hal_device_private_set(xge_hal_device_h devh, void *data)
|
|
{
|
|
((xge_hal_device_t*)devh)->upper_layer_info = data;
|
|
}
|
|
|
|
/**
|
|
* xge_hal_device_private - Get ULD context.
|
|
* @devh: HAL device handle.
|
|
*
|
|
* Use HAL device to get upper-layer driver (ULD) context.
|
|
*
|
|
* Returns: ULD context.
|
|
*
|
|
* See also: xge_hal_device_from_private(), xge_hal_device_private_set()
|
|
*/
|
|
static inline void*
|
|
xge_hal_device_private(xge_hal_device_h devh)
|
|
{
|
|
return ((xge_hal_device_t*)devh)->upper_layer_info;
|
|
}
|
|
|
|
/**
|
|
* xge_hal_device_from_private - Get HAL device object from private.
|
|
* @info_ptr: ULD context.
|
|
*
|
|
* Use ULD context to get HAL device.
|
|
*
|
|
* Returns: Device handle.
|
|
*
|
|
* See also: xge_hal_device_private(), xge_hal_device_private_set()
|
|
*/
|
|
static inline xge_hal_device_h
|
|
xge_hal_device_from_private(void *info_ptr)
|
|
{
|
|
return xge_container_of((void ** ) info_ptr, xge_hal_device_t,
|
|
upper_layer_info);
|
|
}
|
|
|
|
/**
|
|
* xge_hal_device_mtu_check - check MTU value for ranges
|
|
* @hldev: the device
|
|
* @new_mtu: new MTU value to check
|
|
*
|
|
* Will do sanity check for new MTU value.
|
|
*
|
|
* Returns: XGE_HAL_OK - success.
|
|
* XGE_HAL_ERR_INVALID_MTU_SIZE - MTU is invalid.
|
|
*
|
|
* See also: xge_hal_device_mtu_set()
|
|
*/
|
|
static inline xge_hal_status_e
|
|
xge_hal_device_mtu_check(xge_hal_device_t *hldev, int new_mtu)
|
|
{
|
|
if ((new_mtu < XGE_HAL_MIN_MTU) || (new_mtu > XGE_HAL_MAX_MTU)) {
|
|
return XGE_HAL_ERR_INVALID_MTU_SIZE;
|
|
}
|
|
|
|
return XGE_HAL_OK;
|
|
}
|
|
|
|
void xge_hal_device_bcast_enable(xge_hal_device_h devh);
|
|
|
|
void xge_hal_device_bcast_disable(xge_hal_device_h devh);
|
|
|
|
void xge_hal_device_terminating(xge_hal_device_h devh);
|
|
|
|
xge_hal_status_e xge_hal_device_initialize(xge_hal_device_t *hldev,
|
|
xge_hal_device_attr_t *attr, xge_hal_device_config_t *config);
|
|
|
|
void xge_hal_device_terminate(xge_hal_device_t *hldev);
|
|
|
|
xge_hal_status_e xge_hal_device_reset(xge_hal_device_t *hldev);
|
|
|
|
xge_hal_status_e xge_hal_device_macaddr_get(xge_hal_device_t *hldev,
|
|
int index, macaddr_t *macaddr);
|
|
|
|
xge_hal_status_e xge_hal_device_macaddr_set(xge_hal_device_t *hldev,
|
|
int index, macaddr_t macaddr);
|
|
|
|
xge_hal_status_e xge_hal_device_macaddr_clear(xge_hal_device_t *hldev,
|
|
int index);
|
|
|
|
int xge_hal_device_macaddr_find(xge_hal_device_t *hldev, macaddr_t wanted);
|
|
|
|
xge_hal_status_e xge_hal_device_mtu_set(xge_hal_device_t *hldev, int new_mtu);
|
|
|
|
xge_hal_status_e xge_hal_device_status(xge_hal_device_t *hldev, u64 *hw_status);
|
|
|
|
void xge_hal_device_intr_enable(xge_hal_device_t *hldev);
|
|
|
|
void xge_hal_device_intr_disable(xge_hal_device_t *hldev);
|
|
|
|
xge_hal_status_e xge_hal_device_mcast_enable(xge_hal_device_t *hldev);
|
|
|
|
xge_hal_status_e xge_hal_device_mcast_disable(xge_hal_device_t *hldev);
|
|
|
|
void xge_hal_device_promisc_enable(xge_hal_device_t *hldev);
|
|
|
|
void xge_hal_device_promisc_disable(xge_hal_device_t *hldev);
|
|
|
|
xge_hal_status_e xge_hal_device_disable(xge_hal_device_t *hldev);
|
|
|
|
xge_hal_status_e xge_hal_device_enable(xge_hal_device_t *hldev);
|
|
|
|
xge_hal_status_e xge_hal_device_handle_tcode(xge_hal_channel_h channelh,
|
|
xge_hal_dtr_h dtrh,
|
|
u8 t_code);
|
|
|
|
xge_hal_status_e xge_hal_device_link_state(xge_hal_device_h devh,
|
|
xge_hal_device_link_state_e *ls);
|
|
|
|
void xge_hal_device_sched_timer(xge_hal_device_h devh, int interval_us,
|
|
int one_shot);
|
|
|
|
void xge_hal_device_poll(xge_hal_device_h devh);
|
|
|
|
xge_hal_card_e xge_hal_device_check_id(xge_hal_device_h devh);
|
|
|
|
int xge_hal_device_is_slot_freeze(xge_hal_device_h devh);
|
|
|
|
xge_hal_status_e
|
|
xge_hal_device_pci_info_get(xge_hal_device_h devh, xge_hal_pci_mode_e *pci_mode,
|
|
xge_hal_pci_bus_frequency_e *bus_frequency,
|
|
xge_hal_pci_bus_width_e *bus_width);
|
|
|
|
xge_hal_status_e
|
|
xge_hal_spdm_entry_add(xge_hal_device_h devh, xge_hal_ipaddr_t *src_ip,
|
|
xge_hal_ipaddr_t *dst_ip, u16 l4_sp, u16 l4_dp,
|
|
u8 is_tcp, u8 is_ipv4, u8 tgt_queue);
|
|
|
|
xge_hal_status_e
|
|
xge_hal_spdm_entry_remove(xge_hal_device_h devh, xge_hal_ipaddr_t *src_ip,
|
|
xge_hal_ipaddr_t *dst_ip, u16 l4_sp, u16 l4_dp,
|
|
u8 is_tcp, u8 is_ipv4);
|
|
|
|
xge_hal_status_e
|
|
xge_hal_device_rts_section_enable(xge_hal_device_h devh, int index);
|
|
|
|
int
|
|
xge_hal_device_is_closed (xge_hal_device_h devh);
|
|
|
|
/* private functions, don't use them in ULD */
|
|
|
|
void __hal_serial_mem_write64(xge_hal_device_t *hldev, u64 value, u64 *reg);
|
|
|
|
u64 __hal_serial_mem_read64(xge_hal_device_t *hldev, u64 *reg);
|
|
|
|
|
|
/* Some function protoypes for MSI implementation. */
|
|
xge_hal_status_e
|
|
xge_hal_channel_msi_set (xge_hal_channel_h channelh, int msi,
|
|
u32 msg_val);
|
|
void
|
|
xge_hal_mask_msi(xge_hal_device_t *hldev);
|
|
|
|
void
|
|
xge_hal_unmask_msi(xge_hal_channel_h channelh);
|
|
|
|
xge_hal_status_e
|
|
xge_hal_channel_msix_set(xge_hal_channel_h channelh, int msix_idx);
|
|
|
|
xge_hal_status_e
|
|
xge_hal_mask_msix(xge_hal_device_h devh, int msi_id);
|
|
|
|
xge_hal_status_e
|
|
xge_hal_unmask_msix(xge_hal_device_h devh, int msi_id);
|
|
|
|
#if defined(XGE_HAL_CONFIG_LRO)
|
|
xge_hal_status_e
|
|
xge_hal_lro_init(u32 lro_scale, xge_hal_device_t *hldev);
|
|
|
|
void
|
|
xge_hal_lro_terminate(u32 lro_scale, xge_hal_device_t *hldev);
|
|
#endif
|
|
|
|
#if defined(XGE_DEBUG_FP) && (XGE_DEBUG_FP & XGE_DEBUG_FP_DEVICE)
|
|
#define __HAL_STATIC_DEVICE
|
|
#define __HAL_INLINE_DEVICE
|
|
|
|
__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE int
|
|
xge_hal_device_rev(xge_hal_device_t *hldev);
|
|
|
|
__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE xge_hal_status_e
|
|
xge_hal_device_begin_irq(xge_hal_device_t *hldev, u64 *reason);
|
|
|
|
__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void
|
|
xge_hal_device_clear_rx(xge_hal_device_t *hldev);
|
|
|
|
__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void
|
|
xge_hal_device_clear_tx(xge_hal_device_t *hldev);
|
|
|
|
__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE xge_hal_status_e
|
|
xge_hal_device_continue_irq(xge_hal_device_t *hldev);
|
|
|
|
__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE xge_hal_status_e
|
|
xge_hal_device_handle_irq(xge_hal_device_t *hldev);
|
|
|
|
__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE char *
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xge_hal_device_bar0(xge_hal_device_t *hldev);
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__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE char *
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xge_hal_device_isrbar0(xge_hal_device_t *hldev);
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__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE char *
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xge_hal_device_bar1(xge_hal_device_t *hldev);
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__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void
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xge_hal_device_bar0_set(xge_hal_device_t *hldev, char *bar0);
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__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void
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xge_hal_device_isrbar0_set(xge_hal_device_t *hldev, char *isrbar0);
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__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void
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xge_hal_device_bar1_set(xge_hal_device_t *hldev, xge_hal_channel_h channelh,
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char *bar1);
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__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void
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xge_hal_device_mask_tx(xge_hal_device_t *hldev);
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__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void
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xge_hal_device_mask_rx(xge_hal_device_t *hldev);
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__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void
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xge_hal_device_mask_all(xge_hal_device_t *hldev);
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__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void
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xge_hal_device_unmask_tx(xge_hal_device_t *hldev);
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__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void
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xge_hal_device_unmask_rx(xge_hal_device_t *hldev);
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__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void
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xge_hal_device_unmask_all(xge_hal_device_t *hldev);
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__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE xge_hal_status_e
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xge_hal_device_poll_tx_channels(xge_hal_device_t *hldev, int *got_tx);
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__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE xge_hal_status_e
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xge_hal_device_poll_rx_channels(xge_hal_device_t *hldev, int *got_rx);
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__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE xge_hal_status_e
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xge_hal_device_poll_rx_channel(xge_hal_channel_t *channel, int *got_rx);
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__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE xge_hal_status_e
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xge_hal_device_poll_tx_channel(xge_hal_channel_t *channel, int *got_tx);
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#if defined (XGE_HAL_CONFIG_LRO)
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__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL u8
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__hal_header_parse_token_u8(u8 *string,u16 offset);
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__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL u16
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__hal_header_parse_token_u16(u8 *string,u16 offset);
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__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL u32
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__hal_header_parse_token_u32(u8 *string,u16 offset);
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__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL void
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__hal_header_update_u8(u8 *string, u16 offset, u8 val);
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__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL void
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__hal_header_update_u16(u8 *string, u16 offset, u16 val);
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__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL void
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__hal_header_update_u32(u8 *string, u16 offset, u32 val);
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__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL u16
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__hal_tcp_seg_len(iplro_t *ip, tcplro_t *tcp);
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__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e
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__hal_ip_lro_capable(iplro_t *ip, xge_hal_dtr_info_t *ext_info);
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__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e
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__hal_tcp_lro_capable(iplro_t *ip, tcplro_t *tcp, lro_t *lro, int *ts_off);
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__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e
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__hal_lro_capable(u8 *buffer, iplro_t **ip, tcplro_t **tcp,
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xge_hal_dtr_info_t *ext_info);
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__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e
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__hal_get_lro_session(u8 *eth_hdr, iplro_t *ip, tcplro_t *tcp, lro_t **lro,
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xge_hal_dtr_info_t *ext_info, xge_hal_device_t *hldev,
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xge_hal_lro_desc_t *ring_lro, lro_t **lro_end3);
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__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e
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__hal_lro_under_optimal_thresh(iplro_t *ip, tcplro_t *tcp, lro_t *lro,
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xge_hal_device_t *hldev);
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__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e
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__hal_collapse_ip_hdr(iplro_t *ip, tcplro_t *tcp, lro_t *lro,
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xge_hal_device_t *hldev);
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__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e
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__hal_collapse_tcp_hdr(iplro_t *ip, tcplro_t *tcp, lro_t *lro,
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xge_hal_device_t *hldev);
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__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e
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__hal_append_lro(iplro_t *ip, tcplro_t **tcp, u32 *seg_len, lro_t *lro,
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xge_hal_device_t *hldev);
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__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e
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xge_hal_lro_process_rx(int ring, u8 *eth_hdr, u8 *ip_hdr, tcplro_t **tcp,
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u32 *seglen, lro_t **p_lro,
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|
xge_hal_dtr_info_t *ext_info, xge_hal_device_t *hldev,
|
|
lro_t **lro_end3);
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|
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__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e
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xge_hal_accumulate_large_rx(u8 *buffer, tcplro_t **tcp, u32 *seglen,
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|
lro_t **lro, xge_hal_dtr_info_t *ext_info,
|
|
xge_hal_device_t *hldev, lro_t **lro_end3);
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|
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__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL lro_t *
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xge_hal_lro_next_session (xge_hal_device_t *hldev, int ring);
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__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL lro_t *
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xge_hal_lro_get_next_session(xge_hal_device_t *hldev);
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__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL void
|
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__hal_open_lro_session (u8 *buffer, iplro_t *ip, tcplro_t *tcp, lro_t **lro,
|
|
xge_hal_device_t *hldev, xge_hal_lro_desc_t *ring_lro,
|
|
int slot, u32 tcp_seg_len, int ts_off);
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|
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__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL int
|
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__hal_lro_get_free_slot (xge_hal_lro_desc_t *ring_lro);
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#endif
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#else /* XGE_FASTPATH_EXTERN */
|
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#define __HAL_STATIC_DEVICE static
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#define __HAL_INLINE_DEVICE inline
|
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#include <dev/nxge/xgehal/xgehal-device-fp.c>
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#endif /* XGE_FASTPATH_INLINE */
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__EXTERN_END_DECLS
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#endif /* XGE_HAL_DEVICE_H */
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