freebsd-dev/sys/mips
Oleksandr Tymoshenko 1453f4e112 - Fix busdma sync: dcache invalidation operates on cache line aligned
addresses and could modify areas of memory that share the same cache
  line at the beginning and at the ending of the buffer. In order to
  prevent a data loss we save these chunks in temporary buffer before
  invalidation and restore them afer it.

Idea suggested by: cognet
2009-10-28 03:34:05 +00:00
..
adm5120 Does 4 things: 2009-10-15 21:03:32 +00:00
alchemy Does 4 things: 2009-10-15 21:03:32 +00:00
atheros Does 4 things: 2009-10-15 21:03:32 +00:00
compile
conf Update options.mips to support config options required to build the SWARM 2009-10-21 00:56:13 +00:00
idt Does 4 things: 2009-10-15 21:03:32 +00:00
include - Remove bunch of declared but not defined cach-related variables 2009-10-28 00:01:20 +00:00
malta Does 4 things: 2009-10-15 21:03:32 +00:00
mips - Fix busdma sync: dcache invalidation operates on cache line aligned 2009-10-28 03:34:05 +00:00
octeon1 Does 4 things: 2009-10-15 21:03:32 +00:00
rmi White space changes. 2009-10-26 11:00:37 +00:00
sentry5 Does 4 things: 2009-10-15 21:03:32 +00:00
sibyte Does 4 things: 2009-10-15 21:03:32 +00:00