ae09ab8f63
possible, and double faults within an SLB trap handler are not. The result is that it possible to take an SLB fault at any time, on any address, for any reason, at any point in the kernel. This lets us do two important things. First, it removes the (soft) 16 GB RAM ceiling on PPC64 as well as any architectural limitations on KVA space. Second, it lets the kernel tolerate poorly designed hypervisors that have a tendency to fail to restore the SLB properly after a hypervisor context switch. MFC after: 6 weeks
170 lines
5.1 KiB
C
170 lines
5.1 KiB
C
/*-
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* Copyright (c) 1999 Luoqi Chen <luoqi@freebsd.org>
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* Copyright (c) Peter Wemm <peter@netplex.com.au>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _MACHINE_PCPU_H_
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#define _MACHINE_PCPU_H_
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#include <machine/cpufunc.h>
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#include <machine/slb.h>
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#include <machine/tlb.h>
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struct pmap;
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#define CPUSAVE_LEN 9
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#define PCPU_MD_COMMON_FIELDS \
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int pc_inside_intr; \
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struct pmap *pc_curpmap; /* current pmap */ \
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struct thread *pc_fputhread; /* current fpu user */ \
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struct thread *pc_vecthread; /* current vec user */ \
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uintptr_t pc_hwref; \
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uint32_t pc_pir; \
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int pc_bsp; \
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volatile int pc_awake; \
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uint32_t pc_ipimask; \
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register_t pc_tempsave[CPUSAVE_LEN]; \
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register_t pc_disisave[CPUSAVE_LEN]; \
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register_t pc_dbsave[CPUSAVE_LEN];
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#define PCPU_MD_AIM32_FIELDS
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#define PCPU_MD_AIM64_FIELDS \
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struct slb pc_slb[64]; \
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struct slb **pc_userslb; \
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register_t pc_slbsave[18]; \
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uint8_t pc_slbstack[1024];
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#ifdef __powerpc64__
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#define PCPU_MD_AIM_FIELDS PCPU_MD_AIM64_FIELDS
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#else
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#define PCPU_MD_AIM_FIELDS PCPU_MD_AIM32_FIELDS
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#endif
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#define BOOKE_CRITSAVE_LEN (CPUSAVE_LEN + 2)
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#define BOOKE_TLB_MAXNEST 3
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#define BOOKE_TLB_SAVELEN 16
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#define BOOKE_TLBSAVE_LEN (BOOKE_TLB_SAVELEN * BOOKE_TLB_MAXNEST)
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#define PCPU_MD_BOOKE_FIELDS \
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register_t pc_booke_critsave[BOOKE_CRITSAVE_LEN]; \
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register_t pc_booke_mchksave[CPUSAVE_LEN]; \
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register_t pc_booke_tlbsave[BOOKE_TLBSAVE_LEN]; \
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register_t pc_booke_tlb_level; \
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uint32_t *pc_booke_tlb_lock; \
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int pc_tid_next;
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/* Definitions for register offsets within the exception tmp save areas */
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#define CPUSAVE_R27 0 /* where r27 gets saved */
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#define CPUSAVE_R28 1 /* where r28 gets saved */
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#define CPUSAVE_R29 2 /* where r29 gets saved */
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#define CPUSAVE_R30 3 /* where r30 gets saved */
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#define CPUSAVE_R31 4 /* where r31 gets saved */
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#define CPUSAVE_AIM_DAR 5 /* where SPR_DAR gets saved */
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#define CPUSAVE_AIM_DSISR 6 /* where SPR_DSISR gets saved */
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#define CPUSAVE_BOOKE_DEAR 5 /* where SPR_DEAR gets saved */
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#define CPUSAVE_BOOKE_ESR 6 /* where SPR_ESR gets saved */
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#define CPUSAVE_SRR0 7 /* where SRR0 gets saved */
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#define CPUSAVE_SRR1 8 /* where SRR1 gets saved */
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/* Book-E TLBSAVE is more elaborate */
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#define TLBSAVE_BOOKE_LR 0
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#define TLBSAVE_BOOKE_CR 1
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#define TLBSAVE_BOOKE_SRR0 2
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#define TLBSAVE_BOOKE_SRR1 3
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#define TLBSAVE_BOOKE_R20 4
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#define TLBSAVE_BOOKE_R21 5
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#define TLBSAVE_BOOKE_R22 6
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#define TLBSAVE_BOOKE_R23 7
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#define TLBSAVE_BOOKE_R24 8
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#define TLBSAVE_BOOKE_R25 9
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#define TLBSAVE_BOOKE_R26 10
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#define TLBSAVE_BOOKE_R27 11
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#define TLBSAVE_BOOKE_R28 12
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#define TLBSAVE_BOOKE_R29 13
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#define TLBSAVE_BOOKE_R30 14
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#define TLBSAVE_BOOKE_R31 15
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#ifndef COMPILING_LINT
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#ifdef AIM
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#define PCPU_MD_FIELDS \
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PCPU_MD_COMMON_FIELDS \
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PCPU_MD_AIM_FIELDS
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#endif
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#ifdef E500
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#define PCPU_MD_FIELDS \
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PCPU_MD_COMMON_FIELDS \
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PCPU_MD_BOOKE_FIELDS
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#endif
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#else
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#define PCPU_MD_FIELDS \
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PCPU_MD_COMMON_FIELDS \
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PCPU_MD_AIM_FIELDS \
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PCPU_MD_BOOKE_FIELDS
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#endif
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/*
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* Catch-all for ports (e.g. lsof, used by gtop)
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*/
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#ifndef PCPU_MD_FIELDS
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#define PCPU_MD_FIELDS \
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int pc_md_placeholder
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#endif
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#ifdef _KERNEL
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#define pcpup ((struct pcpu *) powerpc_get_pcpup())
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#ifdef AIM /* Book-E not yet adapted */
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static __inline __pure2 struct thread *
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__curthread(void)
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{
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struct thread *td;
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#ifdef __powerpc64__
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__asm __volatile("mr %0,13" : "=r"(td));
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#else
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__asm __volatile("mr %0,2" : "=r"(td));
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#endif
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return (td);
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}
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#define curthread (__curthread())
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#endif
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#define PCPU_GET(member) (pcpup->pc_ ## member)
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/*
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* XXX The implementation of this operation should be made atomic
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* with respect to preemption.
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*/
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#define PCPU_ADD(member, value) (pcpup->pc_ ## member += (value))
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#define PCPU_INC(member) PCPU_ADD(member, 1)
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#define PCPU_PTR(member) (&pcpup->pc_ ## member)
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#define PCPU_SET(member,value) (pcpup->pc_ ## member = (value))
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#endif /* _KERNEL */
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#endif /* !_MACHINE_PCPU_H_ */
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