66ef8af5b0
this introduces a new buffering mechanism which results in dramatic simplification of the channel manager. as several structures have changed, we take the opportunity to move their definitions into the source files where they are used, make them private and de-typedef them. the sound drivers are updated to use snd_setup_intr instead of bus_setup_intr, and to comply with the de-typedefed structures. the ac97, mixer and channel layers have been updated with finegrained locking, as have some drivers- not all though. the rest will follow soon.
689 lines
17 KiB
C
689 lines
17 KiB
C
/*
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* Copyright (c) 1999 Cameron Grant <gandalf@vilnya.demon.co.uk>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#include <dev/sound/pcm/sound.h>
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#include <dev/sound/pcm/ac97.h>
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#include <dev/sound/pci/aureal.h>
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#include <pci/pcireg.h>
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#include <pci/pcivar.h>
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/* PCI IDs of supported chips */
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#define AU8820_PCI_ID 0x000112eb
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/* channel interface */
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static u_int32_t au_playfmt[] = {
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AFMT_U8,
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AFMT_STEREO | AFMT_U8,
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AFMT_S16_LE,
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AFMT_STEREO | AFMT_S16_LE,
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0
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};
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static struct pcmchan_caps au_playcaps = {4000, 48000, au_playfmt, 0};
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static u_int32_t au_recfmt[] = {
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AFMT_U8,
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AFMT_STEREO | AFMT_U8,
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AFMT_S16_LE,
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AFMT_STEREO | AFMT_S16_LE,
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0
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};
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static struct pcmchan_caps au_reccaps = {4000, 48000, au_recfmt, 0};
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/* -------------------------------------------------------------------- */
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struct au_info;
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struct au_chinfo {
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struct au_info *parent;
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struct pcm_channel *channel;
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struct snd_dbuf *buffer;
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int dir;
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};
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struct au_info {
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int unit;
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bus_space_tag_t st[3];
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bus_space_handle_t sh[3];
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bus_dma_tag_t parent_dmat;
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void *lock;
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u_int32_t x[32], y[128];
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char z[128];
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u_int32_t routes[4], interrupts;
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struct au_chinfo pch;
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};
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static int au_init(device_t dev, struct au_info *au);
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static void au_intr(void *);
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/* -------------------------------------------------------------------- */
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static u_int32_t
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au_rd(struct au_info *au, int mapno, int regno, int size)
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{
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switch(size) {
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case 1:
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return bus_space_read_1(au->st[mapno], au->sh[mapno], regno);
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case 2:
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return bus_space_read_2(au->st[mapno], au->sh[mapno], regno);
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case 4:
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return bus_space_read_4(au->st[mapno], au->sh[mapno], regno);
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default:
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return 0xffffffff;
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}
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}
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static void
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au_wr(struct au_info *au, int mapno, int regno, u_int32_t data, int size)
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{
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switch(size) {
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case 1:
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bus_space_write_1(au->st[mapno], au->sh[mapno], regno, data);
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break;
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case 2:
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bus_space_write_2(au->st[mapno], au->sh[mapno], regno, data);
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break;
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case 4:
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bus_space_write_4(au->st[mapno], au->sh[mapno], regno, data);
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break;
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}
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}
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/* -------------------------------------------------------------------- */
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static int
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au_rdcd(kobj_t obj, void *arg, int regno)
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{
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struct au_info *au = (struct au_info *)arg;
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int i=0, j=0;
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regno<<=16;
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au_wr(au, 0, AU_REG_CODECIO, regno, 4);
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while (j<50) {
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i=au_rd(au, 0, AU_REG_CODECIO, 4);
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if ((i & 0x00ff0000) == (regno | 0x00800000)) break;
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DELAY(j * 200 + 2000);
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j++;
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}
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if (j==50) printf("pcm%d: codec timeout reading register %x (%x)\n",
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au->unit, (regno & AU_CDC_REGMASK)>>16, i);
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return i & AU_CDC_DATAMASK;
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}
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static int
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au_wrcd(kobj_t obj, void *arg, int regno, u_int32_t data)
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{
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struct au_info *au = (struct au_info *)arg;
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int i, j, tries;
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i=j=tries=0;
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do {
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while (j<50 && (i & AU_CDC_WROK) == 0) {
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i=au_rd(au, 0, AU_REG_CODECST, 4);
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DELAY(2000);
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j++;
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}
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if (j==50) printf("codec timeout during write of register %x, data %x\n",
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regno, data);
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au_wr(au, 0, AU_REG_CODECIO, (regno<<16) | AU_CDC_REGSET | data, 4);
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/* DELAY(20000);
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i=au_rdcd(au, regno);
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*/ tries++;
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} while (0); /* (i != data && tries < 3); */
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/*
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if (tries == 3) printf("giving up writing 0x%4x to codec reg %2x\n", data, regno);
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*/
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return 0;
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}
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static kobj_method_t au_ac97_methods[] = {
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KOBJMETHOD(ac97_read, au_rdcd),
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KOBJMETHOD(ac97_write, au_wrcd),
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{ 0, 0 }
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};
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AC97_DECLARE(au_ac97);
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/* -------------------------------------------------------------------- */
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static void
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au_setbit(u_int32_t *p, char bit, u_int32_t value)
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{
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p += bit >> 5;
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bit &= 0x1f;
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*p &= ~ (1 << bit);
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*p |= (value << bit);
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}
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static void
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au_addroute(struct au_info *au, int a, int b, int route)
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{
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int j = 0x1099c+(a<<2);
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if (au->x[a] != a+0x67) j = AU_REG_RTBASE+(au->x[a]<<2);
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au_wr(au, 0, AU_REG_RTBASE+(route<<2), 0xffffffff, 4);
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au_wr(au, 0, j, route | (b<<7), 4);
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au->y[route]=au->x[a];
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au->x[a]=route;
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au->z[route]=a & 0x000000ff;
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au_setbit(au->routes, route, 1);
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}
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static void
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au_delroute(struct au_info *au, int route)
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{
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int i;
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int j=au->z[route];
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au_setbit(au->routes, route, 0);
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au->z[route]=0x1f;
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i=au_rd(au, 0, AU_REG_RTBASE+(route<<2), 4);
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au_wr(au, 0, AU_REG_RTBASE+(au->y[route]<<2), i, 4);
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au->y[i & 0x7f]=au->y[route];
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au_wr(au, 0, AU_REG_RTBASE+(route<<2), 0xfffffffe, 4);
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if (au->x[j] == route) au->x[j]=au->y[route];
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au->y[route]=0x7f;
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}
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static void
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au_encodec(struct au_info *au, char channel)
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{
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au_wr(au, 0, AU_REG_CODECEN,
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au_rd(au, 0, AU_REG_CODECEN, 4) | (1 << (channel + 8)), 4);
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}
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static void
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au_clrfifo(struct au_info *au, u_int32_t c)
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{
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u_int32_t i;
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for (i=0; i<32; i++) au_wr(au, 0, AU_REG_FIFOBASE+(c<<7)+(i<<2), 0, 4);
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}
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static void
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au_setadb(struct au_info *au, u_int32_t c, u_int32_t enable)
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{
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int x;
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x = au_rd(au, 0, AU_REG_ADB, 4);
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x &= ~(1 << c);
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x |= (enable << c);
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au_wr(au, 0, AU_REG_ADB, x, 4);
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}
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static void
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au_prepareoutput(struct au_chinfo *ch, u_int32_t format)
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{
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struct au_info *au = ch->parent;
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int i, stereo = (format & AFMT_STEREO)? 1 : 0;
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u_int32_t baseaddr = vtophys(sndbuf_getbuf(ch->buffer));
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au_wr(au, 0, 0x1061c, 0, 4);
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au_wr(au, 0, 0x10620, 0, 4);
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au_wr(au, 0, 0x10624, 0, 4);
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switch(format & ~AFMT_STEREO) {
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case 1:
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i=0xb000;
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break;
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case 2:
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i=0xf000;
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break;
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case 8:
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i=0x7000;
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break;
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case 16:
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i=0x23000;
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break;
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default:
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i=0x3000;
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}
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au_wr(au, 0, 0x10200, baseaddr, 4);
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au_wr(au, 0, 0x10204, baseaddr+0x1000, 4);
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au_wr(au, 0, 0x10208, baseaddr+0x2000, 4);
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au_wr(au, 0, 0x1020c, baseaddr+0x3000, 4);
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au_wr(au, 0, 0x10400, 0xdeffffff, 4);
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au_wr(au, 0, 0x10404, 0xfcffffff, 4);
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au_wr(au, 0, 0x10580, i, 4);
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au_wr(au, 0, 0x10210, baseaddr, 4);
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au_wr(au, 0, 0x10214, baseaddr+0x1000, 4);
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au_wr(au, 0, 0x10218, baseaddr+0x2000, 4);
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au_wr(au, 0, 0x1021c, baseaddr+0x3000, 4);
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au_wr(au, 0, 0x10408, 0x00fff000 | 0x56000000 | 0x00000fff, 4);
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au_wr(au, 0, 0x1040c, 0x00fff000 | 0x74000000 | 0x00000fff, 4);
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au_wr(au, 0, 0x10584, i, 4);
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au_wr(au, 0, 0x0f800, stereo? 0x00030032 : 0x00030030, 4);
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au_wr(au, 0, 0x0f804, stereo? 0x00030032 : 0x00030030, 4);
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au_addroute(au, 0x11, 0, 0x58);
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au_addroute(au, 0x11, stereo? 0 : 1, 0x59);
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}
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/* -------------------------------------------------------------------- */
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/* channel interface */
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static void *
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auchan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir)
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{
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struct au_info *au = devinfo;
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struct au_chinfo *ch = (dir == PCMDIR_PLAY)? &au->pch : NULL;
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ch->parent = au;
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ch->channel = c;
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ch->buffer = b;
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ch->dir = dir;
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if (sndbuf_alloc(ch->buffer, au->parent_dmat, AU_BUFFSIZE) == -1) return NULL;
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return ch;
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}
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static int
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auchan_setformat(kobj_t obj, void *data, u_int32_t format)
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{
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struct au_chinfo *ch = data;
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if (ch->dir == PCMDIR_PLAY) au_prepareoutput(ch, format);
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return 0;
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}
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static int
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auchan_setspeed(kobj_t obj, void *data, u_int32_t speed)
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{
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struct au_chinfo *ch = data;
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if (ch->dir == PCMDIR_PLAY) {
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} else {
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}
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return speed;
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}
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static int
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auchan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize)
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{
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return blocksize;
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}
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static int
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auchan_trigger(kobj_t obj, void *data, int go)
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{
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struct au_chinfo *ch = data;
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struct au_info *au = ch->parent;
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if (go == PCMTRIG_EMLDMAWR || go == PCMTRIG_EMLDMARD)
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return 0;
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if (ch->dir == PCMDIR_PLAY) {
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au_setadb(au, 0x11, (go)? 1 : 0);
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if (!go) {
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au_wr(au, 0, 0xf800, 0, 4);
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au_wr(au, 0, 0xf804, 0, 4);
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au_delroute(au, 0x58);
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au_delroute(au, 0x59);
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}
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} else {
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}
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return 0;
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}
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static int
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auchan_getptr(kobj_t obj, void *data)
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{
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struct au_chinfo *ch = data;
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struct au_info *au = ch->parent;
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if (ch->dir == PCMDIR_PLAY) {
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return au_rd(au, 0, AU_REG_UNK2, 4) & (AU_BUFFSIZE-1);
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} else {
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return 0;
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}
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}
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static struct pcmchan_caps *
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auchan_getcaps(kobj_t obj, void *data)
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{
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struct au_chinfo *ch = data;
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return (ch->dir == PCMDIR_PLAY)? &au_playcaps : &au_reccaps;
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}
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static kobj_method_t auchan_methods[] = {
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KOBJMETHOD(channel_init, auchan_init),
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KOBJMETHOD(channel_setformat, auchan_setformat),
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KOBJMETHOD(channel_setspeed, auchan_setspeed),
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KOBJMETHOD(channel_setblocksize, auchan_setblocksize),
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KOBJMETHOD(channel_trigger, auchan_trigger),
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KOBJMETHOD(channel_getptr, auchan_getptr),
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KOBJMETHOD(channel_getcaps, auchan_getcaps),
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{ 0, 0 }
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};
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CHANNEL_DECLARE(auchan);
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/* -------------------------------------------------------------------- */
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/* The interrupt handler */
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static void
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au_intr (void *p)
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{
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struct au_info *au = p;
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u_int32_t intsrc, i;
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au->interrupts++;
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intsrc=au_rd(au, 0, AU_REG_IRQSRC, 4);
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printf("pcm%d: interrupt with src %x\n", au->unit, intsrc);
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if (intsrc & AU_IRQ_FATAL) printf("pcm%d: fatal error irq\n", au->unit);
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if (intsrc & AU_IRQ_PARITY) printf("pcm%d: parity error irq\n", au->unit);
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if (intsrc & AU_IRQ_UNKNOWN) {
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(void)au_rd(au, 0, AU_REG_UNK1, 4);
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au_wr(au, 0, AU_REG_UNK1, 0, 4);
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au_wr(au, 0, AU_REG_UNK1, 0x10000, 4);
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}
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if (intsrc & AU_IRQ_PCMOUT) {
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i=au_rd(au, 0, AU_REG_UNK2, 4) & (AU_BUFFSIZE-1);
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chn_intr(au->pch.channel);
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(void)au_rd(au, 0, AU_REG_UNK3, 4);
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(void)au_rd(au, 0, AU_REG_UNK4, 4);
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(void)au_rd(au, 0, AU_REG_UNK5, 4);
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}
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/* don't support midi
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if (intsrc & AU_IRQ_MIDI) {
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i=au_rd(au, 0, 0x11004, 4);
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j=10;
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while (i & 0xff) {
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if (j-- <= 0) break;
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i=au_rd(au, 0, 0x11000, 4);
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if ((au->midi_stat & 1) && (au->midi_out))
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au->midi_out(au->midi_devno, i);
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i=au_rd(au, 0, 0x11004);
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}
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}
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*/
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au_wr(au, 0, AU_REG_IRQSRC, intsrc & 0x7ff, 4);
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au_rd(au, 0, AU_REG_IRQSRC, 4);
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}
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/* -------------------------------------------------------------------- */
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/* Probe and attach the card */
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static int
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au_init(device_t dev, struct au_info *au)
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{
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u_int32_t i, j;
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au_wr(au, 0, AU_REG_IRQGLOB, 0xffffffff, 4);
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DELAY(100000);
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/* init codec */
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/* cold reset */
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for (i=0; i<32; i++) {
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au_wr(au, 0, AU_REG_CODECCHN+(i<<2), 0, 4);
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DELAY(10000);
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}
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if (1) {
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au_wr(au, 0, AU_REG_CODECST, 0x8068, 4);
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DELAY(10000);
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au_wr(au, 0, AU_REG_CODECST, 0x00e8, 4);
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DELAY(10000);
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} else {
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au_wr(au, 0, AU_REG_CODECST, 0x00a8, 4);
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DELAY(100000);
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au_wr(au, 0, AU_REG_CODECST, 0x80a8, 4);
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DELAY(100000);
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au_wr(au, 0, AU_REG_CODECST, 0x80e8, 4);
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DELAY(100000);
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au_wr(au, 0, AU_REG_CODECST, 0x80a8, 4);
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DELAY(100000);
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au_wr(au, 0, AU_REG_CODECST, 0x00a8, 4);
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DELAY(100000);
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au_wr(au, 0, AU_REG_CODECST, 0x00e8, 4);
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DELAY(100000);
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}
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/* init */
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for (i=0; i<32; i++) {
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au_wr(au, 0, AU_REG_CODECCHN+(i<<2), 0, 4);
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DELAY(10000);
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}
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|
au_wr(au, 0, AU_REG_CODECST, 0xe8, 4);
|
|
DELAY(10000);
|
|
au_wr(au, 0, AU_REG_CODECEN, 0, 4);
|
|
|
|
/* setup codec */
|
|
i=j=0;
|
|
while (j<100 && (i & AU_CDC_READY)==0) {
|
|
i=au_rd(au, 0, AU_REG_CODECST, 4);
|
|
DELAY(1000);
|
|
j++;
|
|
}
|
|
if (j==100) device_printf(dev, "codec not ready, status 0x%x\n", i);
|
|
|
|
/* init adb */
|
|
/*au->x5c=0;*/
|
|
for (i=0; i<32; i++) au->x[i]=i+0x67;
|
|
for (i=0; i<128; i++) au->y[i]=0x7f;
|
|
for (i=0; i<128; i++) au->z[i]=0x1f;
|
|
au_wr(au, 0, AU_REG_ADB, 0, 4);
|
|
for (i=0; i<124; i++) au_wr(au, 0, AU_REG_RTBASE+(i<<2), 0xffffffff, 4);
|
|
|
|
/* test */
|
|
i=au_rd(au, 0, 0x107c0, 4);
|
|
if (i!=0xdeadbeef) device_printf(dev, "dma check failed: 0x%x\n", i);
|
|
|
|
/* install mixer */
|
|
au_wr(au, 0, AU_REG_IRQGLOB,
|
|
au_rd(au, 0, AU_REG_IRQGLOB, 4) | AU_IRQ_ENABLE, 4);
|
|
/* braindead but it's what the oss/linux driver does
|
|
* for (i=0; i<0x80000000; i++) au_wr(au, 0, i<<2, 0, 4);
|
|
*/
|
|
au->routes[0]=au->routes[1]=au->routes[2]=au->routes[3]=0;
|
|
/*au->x1e4=0;*/
|
|
|
|
/* attach channel */
|
|
au_addroute(au, 0x11, 0x48, 0x02);
|
|
au_addroute(au, 0x11, 0x49, 0x03);
|
|
au_encodec(au, 0);
|
|
au_encodec(au, 1);
|
|
|
|
for (i=0; i<48; i++) au_wr(au, 0, 0xf800+(i<<2), 0x20, 4);
|
|
for (i=2; i<6; i++) au_wr(au, 0, 0xf800+(i<<2), 0, 4);
|
|
au_wr(au, 0, 0xf8c0, 0x0843, 4);
|
|
for (i=0; i<4; i++) au_clrfifo(au, i);
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
au_testirq(struct au_info *au)
|
|
{
|
|
au_wr(au, 0, AU_REG_UNK1, 0x80001000, 4);
|
|
au_wr(au, 0, AU_REG_IRQEN, 0x00001030, 4);
|
|
au_wr(au, 0, AU_REG_IRQSRC, 0x000007ff, 4);
|
|
DELAY(1000000);
|
|
if (au->interrupts==0) printf("pcm%d: irq test failed\n", au->unit);
|
|
/* this apparently generates an irq */
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
au_pci_probe(device_t dev)
|
|
{
|
|
if (pci_get_devid(dev) == AU8820_PCI_ID) {
|
|
device_set_desc(dev, "Aureal Vortex 8820");
|
|
return 0;
|
|
}
|
|
|
|
return ENXIO;
|
|
}
|
|
|
|
static int
|
|
au_pci_attach(device_t dev)
|
|
{
|
|
u_int32_t data;
|
|
struct au_info *au;
|
|
int type[10];
|
|
int regid[10];
|
|
struct resource *reg[10];
|
|
int i, j, mapped = 0;
|
|
int irqid;
|
|
struct resource *irq = 0;
|
|
void *ih = 0;
|
|
struct ac97_info *codec;
|
|
char status[SND_STATUSLEN];
|
|
|
|
if ((au = malloc(sizeof(*au), M_DEVBUF, M_NOWAIT)) == NULL) {
|
|
device_printf(dev, "cannot allocate softc\n");
|
|
return ENXIO;
|
|
}
|
|
|
|
bzero(au, sizeof(*au));
|
|
au->unit = device_get_unit(dev);
|
|
|
|
data = pci_read_config(dev, PCIR_COMMAND, 2);
|
|
data |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
|
|
pci_write_config(dev, PCIR_COMMAND, data, 2);
|
|
data = pci_read_config(dev, PCIR_COMMAND, 2);
|
|
|
|
j=0;
|
|
/* XXX dfr: is this strictly necessary? */
|
|
for (i=0; i<PCI_MAXMAPS_0; i++) {
|
|
#if 0
|
|
/* Slapped wrist: config_id and map are private structures */
|
|
if (bootverbose) {
|
|
printf("pcm%d: map %d - allocating ", unit, i+1);
|
|
printf("0x%x bytes of ", 1<<config_id->map[i].ln2size);
|
|
printf("%s space ", (config_id->map[i].type & PCI_MAPPORT)?
|
|
"io" : "memory");
|
|
printf("at 0x%x...", config_id->map[i].base);
|
|
}
|
|
#endif
|
|
regid[j] = PCIR_MAPS + i*4;
|
|
type[j] = SYS_RES_MEMORY;
|
|
reg[j] = bus_alloc_resource(dev, type[j], ®id[j],
|
|
0, ~0, 1, RF_ACTIVE);
|
|
if (!reg[j]) {
|
|
type[j] = SYS_RES_IOPORT;
|
|
reg[j] = bus_alloc_resource(dev, type[j], ®id[j],
|
|
0, ~0, 1, RF_ACTIVE);
|
|
}
|
|
if (reg[j]) {
|
|
au->st[i] = rman_get_bustag(reg[j]);
|
|
au->sh[i] = rman_get_bushandle(reg[j]);
|
|
mapped++;
|
|
}
|
|
#if 0
|
|
if (bootverbose) printf("%s\n", mapped? "ok" : "failed");
|
|
#endif
|
|
if (mapped) j++;
|
|
if (j == 10) {
|
|
/* XXX */
|
|
device_printf(dev, "too many resources");
|
|
goto bad;
|
|
}
|
|
}
|
|
|
|
#if 0
|
|
if (j < config_id->nummaps) {
|
|
printf("pcm%d: unable to map a required resource\n", unit);
|
|
free(au, M_DEVBUF);
|
|
return;
|
|
}
|
|
#endif
|
|
|
|
au_wr(au, 0, AU_REG_IRQEN, 0, 4);
|
|
|
|
irqid = 0;
|
|
irq = bus_alloc_resource(dev, SYS_RES_IRQ, &irqid,
|
|
0, ~0, 1, RF_ACTIVE | RF_SHAREABLE);
|
|
if (!irq || snd_setup_intr(dev, irq, 0, au_intr, au, &ih)) {
|
|
device_printf(dev, "unable to map interrupt\n");
|
|
goto bad;
|
|
}
|
|
|
|
if (au_testirq(au)) device_printf(dev, "irq test failed\n");
|
|
|
|
if (au_init(dev, au) == -1) {
|
|
device_printf(dev, "unable to initialize the card\n");
|
|
goto bad;
|
|
}
|
|
|
|
codec = AC97_CREATE(dev, au, au_ac97);
|
|
if (codec == NULL) goto bad;
|
|
if (mixer_init(dev, ac97_getmixerclass(), codec) == -1) goto bad;
|
|
|
|
if (bus_dma_tag_create(/*parent*/NULL, /*alignment*/2, /*boundary*/0,
|
|
/*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
|
|
/*highaddr*/BUS_SPACE_MAXADDR,
|
|
/*filter*/NULL, /*filterarg*/NULL,
|
|
/*maxsize*/AU_BUFFSIZE, /*nsegments*/1, /*maxsegz*/0x3ffff,
|
|
/*flags*/0, &au->parent_dmat) != 0) {
|
|
device_printf(dev, "unable to create dma tag\n");
|
|
goto bad;
|
|
}
|
|
|
|
snprintf(status, SND_STATUSLEN, "at %s 0x%lx irq %ld",
|
|
(type[0] == SYS_RES_IOPORT)? "io" : "memory",
|
|
rman_get_start(reg[0]), rman_get_start(irq));
|
|
|
|
if (pcm_register(dev, au, 1, 1)) goto bad;
|
|
/* pcm_addchan(dev, PCMDIR_REC, &au_chantemplate, au); */
|
|
pcm_addchan(dev, PCMDIR_PLAY, &auchan_class, au);
|
|
pcm_setstatus(dev, status);
|
|
|
|
return 0;
|
|
|
|
bad:
|
|
if (au) free(au, M_DEVBUF);
|
|
for (i = 0; i < j; i++)
|
|
bus_release_resource(dev, type[i], regid[i], reg[i]);
|
|
if (ih) bus_teardown_intr(dev, irq, ih);
|
|
if (irq) bus_release_resource(dev, SYS_RES_IRQ, irqid, irq);
|
|
return ENXIO;
|
|
}
|
|
|
|
static device_method_t au_methods[] = {
|
|
/* Device interface */
|
|
DEVMETHOD(device_probe, au_pci_probe),
|
|
DEVMETHOD(device_attach, au_pci_attach),
|
|
|
|
{ 0, 0 }
|
|
};
|
|
|
|
static driver_t au_driver = {
|
|
"pcm",
|
|
au_methods,
|
|
sizeof(struct snddev_info),
|
|
};
|
|
|
|
static devclass_t pcm_devclass;
|
|
|
|
DRIVER_MODULE(snd_aureal, pci, au_driver, pcm_devclass, 0, 0);
|
|
MODULE_DEPEND(snd_aureal, snd_pcm, PCM_MINVER, PCM_PREFVER, PCM_MAXVER);
|
|
MODULE_VERSION(snd_aureal, 1);
|