8e5d93dbb4
the NIC drivers as well as the PHY drivers to take advantage of the
mii_attach() introduced in r213878 to get rid of certain hacks. For
the most part these were:
- Artificially limiting miibus_{read,write}reg methods to certain PHY
addresses; we now let mii_attach() only probe the PHY at the desired
address(es) instead.
- PHY drivers setting MIIF_* flags based on the NIC driver they hang
off from, partly even based on grabbing and using the softc of the
parent; we now pass these flags down from the NIC to the PHY drivers
via mii_attach(). This got us rid of all such hacks except those of
brgphy() in combination with bce(4) and bge(4), which is way beyond
what can be expressed with simple flags.
While at it, I took the opportunity to change the NIC drivers to pass
up the error returned by mii_attach() (previously by mii_phy_probe())
and unify the error message used in this case where and as appropriate
as mii_attach() actually can fail for a number of reasons, not just
because of no PHY(s) being present at the expected address(es).
Reviewed by: jhb, yongari
351 lines
12 KiB
C
351 lines
12 KiB
C
/*-
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* Copyright (C) 2008 MARVELL INTERNATIONAL LTD.
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* All rights reserved.
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*
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* Developed by Semihalf.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of MARVELL nor the names of contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef __IF_MGE_H__
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#define __IF_MGE_H__
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#define MGE_INTR_COUNT 5 /* ETH controller occupies 5 IRQ lines */
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#define MGE_TX_DESC_NUM 256
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#define MGE_RX_DESC_NUM 256
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#define MGE_RX_QUEUE_NUM 8
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#define MGE_RX_DEFAULT_QUEUE 0
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#define MGE_CHECKSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
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/* Interrupt Coalescing types */
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#define MGE_IC_RX 0
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#define MGE_IC_TX 1
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struct mge_desc {
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uint32_t cmd_status;
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uint16_t buff_size;
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uint16_t byte_count;
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bus_addr_t buffer;
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bus_addr_t next_desc;
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};
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struct mge_desc_wrapper {
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bus_dmamap_t desc_dmap;
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struct mge_desc* mge_desc;
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bus_addr_t mge_desc_paddr;
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bus_dmamap_t buffer_dmap;
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struct mbuf* buffer;
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};
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struct mge_softc {
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struct ifnet *ifp; /* per-interface network data */
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phandle_t node;
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device_t dev;
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device_t miibus;
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struct mii_data *mii;
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struct resource *res[1 + MGE_INTR_COUNT]; /* resources */
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void *ih_cookie[MGE_INTR_COUNT]; /* interrupt handlers cookies */
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struct mtx transmit_lock; /* transmitter lock */
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struct mtx receive_lock; /* receiver lock */
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uint32_t mge_if_flags;
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uint32_t mge_media_status;
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struct callout wd_callout;
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int wd_timer;
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bus_dma_tag_t mge_desc_dtag;
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bus_dma_tag_t mge_tx_dtag;
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bus_dma_tag_t mge_rx_dtag;
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bus_addr_t tx_desc_start;
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bus_addr_t rx_desc_start;
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uint32_t tx_desc_curr;
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uint32_t rx_desc_curr;
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uint32_t tx_desc_used_idx;
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uint32_t tx_desc_used_count;
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uint32_t rx_ic_time;
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uint32_t tx_ic_time;
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struct mge_desc_wrapper mge_tx_desc[MGE_TX_DESC_NUM];
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struct mge_desc_wrapper mge_rx_desc[MGE_RX_DESC_NUM];
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uint32_t mge_tfut_ipg_max; /* TX FIFO Urgent Threshold */
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uint32_t mge_rx_ipg_max;
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uint32_t mge_tx_arb_cfg;
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uint32_t mge_tx_tok_cfg;
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uint32_t mge_tx_tok_cnt;
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uint16_t mge_mtu;
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int mge_ver;
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};
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/* bus access macros */
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#define MGE_READ(sc,reg) bus_read_4((sc)->res[0], (reg))
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#define MGE_WRITE(sc,reg,val) bus_write_4((sc)->res[0], (reg), (val))
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/* Locking macros */
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#define MGE_TRANSMIT_LOCK(sc) do { \
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mtx_assert(&(sc)->receive_lock, MA_NOTOWNED); \
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mtx_lock(&(sc)->transmit_lock); \
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} while (0)
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#define MGE_TRANSMIT_UNLOCK(sc) mtx_unlock(&(sc)->transmit_lock)
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#define MGE_TRANSMIT_LOCK_ASSERT(sc) mtx_assert(&(sc)->transmit_lock, MA_OWNED)
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#define MGE_RECEIVE_LOCK(sc) do { \
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mtx_assert(&(sc)->transmit_lock, MA_NOTOWNED); \
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mtx_lock(&(sc)->receive_lock); \
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} while (0)
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#define MGE_RECEIVE_UNLOCK(sc) mtx_unlock(&(sc)->receive_lock)
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#define MGE_RECEIVE_LOCK_ASSERT(sc) mtx_assert(&(sc)->receive_lock, MA_OWNED)
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#define MGE_GLOBAL_LOCK(sc) do { \
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if ((mtx_owned(&(sc)->transmit_lock) ? 1 : 0) != \
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(mtx_owned(&(sc)->receive_lock) ? 1 : 0)) { \
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panic("mge deadlock possibility detection!"); \
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} \
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mtx_lock(&(sc)->transmit_lock); \
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mtx_lock(&(sc)->receive_lock); \
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} while (0)
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#define MGE_GLOBAL_UNLOCK(sc) do { \
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MGE_RECEIVE_UNLOCK(sc); \
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MGE_TRANSMIT_UNLOCK(sc); \
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} while (0)
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#define MGE_GLOBAL_LOCK_ASSERT(sc) do { \
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MGE_TRANSMIT_LOCK_ASSERT(sc); \
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MGE_RECEIVE_LOCK_ASSERT(sc); \
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} while (0)
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/* SMI-related macros */
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#define MGE_REG_PHYDEV 0x000
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#define MGE_REG_SMI 0x004
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#define MGE_SMI_READ (1 << 26)
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#define MGE_SMI_WRITE (0 << 26)
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#define MGE_SMI_READVALID (1 << 27)
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#define MGE_SMI_BUSY (1 << 28)
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/* TODO verify the timings and retries count w/specs */
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#define MGE_SMI_READ_RETRIES 1000
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#define MGE_SMI_READ_DELAY 100
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#define MGE_SMI_WRITE_RETRIES 1000
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#define MGE_SMI_WRITE_DELAY 100
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/* MGE registers */
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#define MGE_INT_CAUSE 0x080
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#define MGE_INT_MASK 0x084
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#define MGE_PORT_CONFIG 0x400
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#define PORT_CONFIG_UPM (1 << 0) /* promiscuous */
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#define PORT_CONFIG_DFLT_RXQ(val) (((val) & 7) << 1) /* default RX queue */
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#define PORT_CONFIG_ARO_RXQ(val) (((val) & 7) << 4) /* ARP RX queue */
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#define PORT_CONFIG_REJECT_BCAST (1 << 7) /* reject non-ip and non-arp bcast */
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#define PORT_CONFIG_REJECT_IP_BCAST (1 << 8) /* reject ip bcast */
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#define PORT_CONFIG_REJECT_ARP__BCAST (1 << 9) /* reject arp bcast */
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#define PORT_CONFIG_AMNoTxES (1 << 12) /* Automatic mode not updating Error Summary in Tx descriptor */
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#define PORT_CONFIG_TCP_CAP (1 << 14) /* capture tcp to a different queue */
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#define PORT_CONFIG_UDP_CAP (1 << 15) /* capture udp to a different queue */
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#define PORT_CONFIG_TCPQ (7 << 16) /* queue to capture tcp */
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#define PORT_CONFIG_UDPQ (7 << 19) /* queue to capture udp */
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#define PORT_CONFIG_BPDUQ (7 << 22) /* queue to capture bpdu */
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#define PORT_CONFIG_RXCS (1 << 25) /* calculation Rx TCP checksum include pseudo header */
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#define MGE_PORT_EXT_CONFIG 0x404
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#define MGE_MAC_ADDR_L 0x414
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#define MGE_MAC_ADDR_H 0x418
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#define MGE_SDMA_CONFIG 0x41c
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#define MGE_SDMA_INT_ON_FRAME_BOUND (1 << 0)
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#define MGE_SDMA_RX_BURST_SIZE(val) (((val) & 7) << 1)
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#define MGE_SDMA_TX_BURST_SIZE(val) (((val) & 7) << 22)
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#define MGE_SDMA_BURST_1_WORD 0x0
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#define MGE_SDMA_BURST_2_WORD 0x1
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#define MGE_SDMA_BURST_4_WORD 0x2
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#define MGE_SDMA_BURST_8_WORD 0x3
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#define MGE_SDMA_BURST_16_WORD 0x4
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#define MGE_SDMA_RX_BYTE_SWAP (1 << 4)
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#define MGE_SDMA_TX_BYTE_SWAP (1 << 5)
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#define MGE_SDMA_DESC_SWAP_MODE (1 << 6)
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#define MGE_PORT_SERIAL_CTRL 0x43c
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#define PORT_SERIAL_ENABLE (1 << 0) /* serial port enable */
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#define PORT_SERIAL_FORCE_LINKUP (1 << 1) /* force link status to up */
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#define PORT_SERIAL_AUTONEG (1 << 2) /* enable autoneg for duplex mode */
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#define PORT_SERIAL_AUTONEG_FC (1 << 3) /* enable autoneg for FC */
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#define PORT_SERIAL_PAUSE_ADV (1 << 4) /* advertise symmetric FC in autoneg */
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#define PORT_SERIAL_FORCE_FC(val) (((val) & 3) << 5) /* pause enable & disable frames conf */
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#define PORT_SERIAL_NO_PAUSE_DIS 0x00
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#define PORT_SERIAL_PAUSE_DIS 0x01
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#define PORT_SERIAL_FORCE_BP(val) (((val) & 3) << 7) /* transmitting JAM configuration */
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#define PORT_SERIAL_NO_JAM 0x00
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#define PORT_SERIAL_JAM 0x01
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#define PORT_SERIAL_RES_BIT9 (1 << 9)
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#define PORT_SERIAL_FORCE_LINK_FAIL (1 << 10)
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#define PORT_SERIAL_SPEED_AUTONEG (1 << 13)
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#define PORT_SERIAL_FORCE_DTE_ADV (1 << 14)
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#define PORT_SERIAL_MRU(val) (((val) & 7) << 17)
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#define PORT_SERIAL_MRU_1518 0x0
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#define PORT_SERIAL_MRU_1522 0x1
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#define PORT_SERIAL_MRU_1552 0x2
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#define PORT_SERIAL_MRU_9022 0x3
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#define PORT_SERIAL_MRU_9192 0x4
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#define PORT_SERIAL_MRU_9700 0x5
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#define PORT_SERIAL_FULL_DUPLEX (1 << 21)
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#define PORT_SERIAL_FULL_DUPLEX_FC (1 << 22)
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#define PORT_SERIAL_GMII_SPEED_1000 (1 << 23)
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#define PORT_SERIAL_MII_SPEED_100 (1 << 24)
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#define MGE_PORT_STATUS 0x444
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#define MGE_STATUS_LINKUP (1 << 1)
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#define MGE_STATUS_FULL_DUPLEX (1 << 2)
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#define MGE_STATUS_FLOW_CONTROL (1 << 3)
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#define MGE_STATUS_1000MB (1 << 4)
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#define MGE_STATUS_100MB (1 << 5)
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#define MGE_STATUS_TX_IN_PROG (1 << 7)
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#define MGE_STATUS_TX_FIFO_EMPTY (1 << 10)
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#define MGE_TX_QUEUE_CMD 0x448
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#define MGE_ENABLE_TXQ (1 << 0)
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#define MGE_DISABLE_TXQ (1 << 8)
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/* 88F6281 only */
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#define MGE_PORT_SERIAL_CTRL1 0x44c
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#define MGE_PCS_LOOPBACK (1 << 1)
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#define MGE_RGMII_EN (1 << 3)
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#define MGE_PORT_RESET (1 << 4)
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#define MGE_CLK125_BYPASS (1 << 5)
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#define MGE_INBAND_AUTONEG (1 << 6)
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#define MGE_INBAND_AUTONEG_BYPASS (1 << 6)
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#define MGE_INBAND_AUTONEG_RESTART (1 << 7)
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#define MGE_1000BASEX (1 << 11)
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#define MGE_BP_COLLISION_COUNT (1 << 15)
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#define MGE_COLLISION_LIMIT(val) (((val) & 0x3f) << 16)
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#define MGE_DROP_ODD_PREAMBLE (1 << 22)
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#define MGE_PORT_INT_CAUSE 0x460
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#define MGE_PORT_INT_MASK 0x468
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#define MGE_PORT_INT_RX (1 << 0)
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#define MGE_PORT_INT_EXTEND (1 << 1)
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#define MGE_PORT_INT_RXQ0 (1 << 2)
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#define MGE_PORT_INT_RXERR (1 << 10)
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#define MGE_PORT_INT_RXERRQ0 (1 << 11)
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#define MGE_PORT_INT_SUM (1 << 31)
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#define MGE_PORT_INT_CAUSE_EXT 0x464
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#define MGE_PORT_INT_MASK_EXT 0x46C
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#define MGE_PORT_INT_EXT_TXBUF0 (1 << 0)
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#define MGE_PORT_INT_EXT_TXERR0 (1 << 8)
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#define MGE_PORT_INT_EXT_PHYSC (1 << 16)
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#define MGE_PORT_INT_EXT_RXOR (1 << 18)
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#define MGE_PORT_INT_EXT_TXUR (1 << 19)
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#define MGE_PORT_INT_EXT_LC (1 << 20)
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#define MGE_PORT_INT_EXT_IAR (1 << 23)
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#define MGE_PORT_INT_EXT_SUM (1 << 31)
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#define MGE_RX_FIFO_URGENT_TRSH 0x470
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#define MGE_TX_FIFO_URGENT_TRSH 0x474
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#define MGE_FIXED_PRIO_CONF 0x4dc
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#define MGE_FIXED_PRIO_EN(q) (1 << (q))
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#define MGE_RX_CUR_DESC_PTR(q) (0x60c + ((q)<<4))
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#define MGE_RX_QUEUE_CMD 0x680
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#define MGE_ENABLE_RXQ(q) (1 << ((q) & 0x7))
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#define MGE_ENABLE_RXQ_ALL (0xff)
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#define MGE_DISABLE_RXQ(q) (1 << (((q) & 0x7) + 8))
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#define MGE_DISABLE_RXQ_ALL (0xff00)
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#define MGE_TX_CUR_DESC_PTR 0x6c0
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#define MGE_TX_TOKEN_COUNT(q) (0x700 + ((q)<<4))
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#define MGE_TX_TOKEN_CONF(q) (0x704 + ((q)<<4))
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#define MGE_TX_ARBITER_CONF(q) (0x704 + ((q)<<4))
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#define MGE_MCAST_REG_NUMBER 64
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#define MGE_DA_FILTER_SPEC_MCAST(i) (0x1400 + ((i) << 2))
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#define MGE_DA_FILTER_OTH_MCAST(i) (0x1500 + ((i) << 2))
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#define MGE_UCAST_REG_NUMBER 4
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#define MGE_DA_FILTER_UCAST(i) (0x1600 + ((i) << 2))
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/* TX descriptor bits */
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#define MGE_TX_LLC_SNAP (1 << 9)
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#define MGE_TX_NOT_FRAGMENT (1 << 10)
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#define MGE_TX_VLAN_TAGGED (1 << 15)
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#define MGE_TX_UDP (1 << 16)
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#define MGE_TX_GEN_L4_CSUM (1 << 17)
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#define MGE_TX_GEN_IP_CSUM (1 << 18)
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#define MGE_TX_PADDING (1 << 19)
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#define MGE_TX_LAST (1 << 20)
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#define MGE_TX_FIRST (1 << 21)
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#define MGE_TX_ETH_CRC (1 << 22)
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#define MGE_TX_EN_INT (1 << 23)
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#define MGE_TX_IP_HDR_SIZE(size) ((size << 11) & 0xFFFF)
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/* RX descriptor bits */
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#define MGE_ERR_SUMMARY (1 << 0)
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#define MGE_ERR_MASK (3 << 1)
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#define MGE_RX_L4_PROTO_MASK (3 << 21)
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#define MGE_RX_L4_PROTO_TCP (0 << 21)
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#define MGE_RX_L4_PROTO_UDP (1 << 21)
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#define MGE_RX_L3_IS_IP (1 << 24)
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#define MGE_RX_IP_OK (1 << 25)
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#define MGE_RX_DESC_LAST (1 << 26)
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#define MGE_RX_DESC_FIRST (1 << 27)
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#define MGE_RX_ENABLE_INT (1 << 29)
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#define MGE_RX_L4_CSUM_OK (1 << 30)
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#define MGE_DMA_OWNED (1 << 31)
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#define MGE_RX_IP_FRAGMENT (1 << 2)
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#define MGE_RX_L4_IS_TCP(status) ((status & MGE_RX_L4_PROTO_MASK) \
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== MGE_RX_L4_PROTO_TCP)
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#define MGE_RX_L4_IS_UDP(status) ((status & MGE_RX_L4_PROTO_MASK) \
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== MGE_RX_L4_PROTO_UDP)
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/* TX error codes */
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#define MGE_TX_ERROR_LC (0 << 1) /* Late collision */
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#define MGE_TX_ERROR_UR (1 << 1) /* Underrun error */
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#define MGE_TX_ERROR_RL (2 << 1) /* Excessive collision */
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/* RX error codes */
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#define MGE_RX_ERROR_CE (0 << 1) /* CRC error */
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#define MGE_RX_ERROR_OR (1 << 1) /* Overrun error */
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#define MGE_RX_ERROR_MF (2 << 1) /* Max frame lenght error */
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#define MGE_RX_ERROR_RE (3 << 1) /* Resource error */
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#endif /* __IF_MGE_H__ */
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