160dd8eb7b
can deal with from 1GB to 2GB. I have no way to test with >1GB because I don't have high enough density memory to get any one box over 1GB. However, I have tested it on xp1000 & ds10 with < 1GB of memory & have verified that it does no harm.
668 lines
15 KiB
C
668 lines
15 KiB
C
/*-
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* Copyright (c) 1999 Andrew Gallatin
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#include "opt_cpu.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/bus.h>
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#include <machine/bus.h>
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#include <sys/rman.h>
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#include <sys/malloc.h>
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#include <pci/pcivar.h>
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#include <alpha/isa/isavar.h>
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#include <alpha/pci/tsunamireg.h>
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#include <alpha/pci/tsunamivar.h>
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#include <alpha/pci/pcibus.h>
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#include <machine/bwx.h>
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#include <machine/intr.h>
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#include <machine/intrcnt.h>
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#include <machine/cpuconf.h>
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#include <machine/rpb.h>
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#include <machine/resource.h>
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#include <machine/sgmap.h>
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#include <vm/vm.h>
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#include <vm/vm_page.h>
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#define KV(pa) ALPHA_PHYS_TO_K0SEG(pa)
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static devclass_t tsunami_devclass;
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static device_t tsunami0; /* XXX only one for now */
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struct tsunami_softc {
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int junk; /* no softc */
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};
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static int num_pchips = 0;
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static volatile tsunami_pchip *pchip[2] = {pchip0, pchip1};
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#define TSUNAMI_SOFTC(dev) (struct tsunami_softc*) device_get_softc(dev)
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static alpha_chipset_inb_t tsunami_inb;
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static alpha_chipset_inw_t tsunami_inw;
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static alpha_chipset_inl_t tsunami_inl;
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static alpha_chipset_outb_t tsunami_outb;
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static alpha_chipset_outw_t tsunami_outw;
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static alpha_chipset_outl_t tsunami_outl;
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static alpha_chipset_readb_t tsunami_readb;
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static alpha_chipset_readw_t tsunami_readw;
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static alpha_chipset_readl_t tsunami_readl;
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static alpha_chipset_writeb_t tsunami_writeb;
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static alpha_chipset_writew_t tsunami_writew;
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static alpha_chipset_writel_t tsunami_writel;
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static alpha_chipset_maxdevs_t tsunami_maxdevs;
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static alpha_chipset_cfgreadb_t tsunami_cfgreadb;
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static alpha_chipset_cfgreadw_t tsunami_cfgreadw;
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static alpha_chipset_cfgreadl_t tsunami_cfgreadl;
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static alpha_chipset_cfgwriteb_t tsunami_cfgwriteb;
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static alpha_chipset_cfgwritew_t tsunami_cfgwritew;
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static alpha_chipset_cfgwritel_t tsunami_cfgwritel;
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static alpha_chipset_addrcvt_t tsunami_cvt_dense, tsunami_cvt_bwx;
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static alpha_chipset_read_hae_t tsunami_read_hae;
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static alpha_chipset_write_hae_t tsunami_write_hae;
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static alpha_chipset_t tsunami_chipset = {
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tsunami_inb,
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tsunami_inw,
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tsunami_inl,
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tsunami_outb,
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tsunami_outw,
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tsunami_outl,
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tsunami_readb,
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tsunami_readw,
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tsunami_readl,
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tsunami_writeb,
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tsunami_writew,
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tsunami_writel,
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tsunami_maxdevs,
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tsunami_cfgreadb,
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tsunami_cfgreadw,
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tsunami_cfgreadl,
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tsunami_cfgwriteb,
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tsunami_cfgwritew,
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tsunami_cfgwritel,
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tsunami_cvt_dense,
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tsunami_cvt_bwx,
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tsunami_read_hae,
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tsunami_write_hae,
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};
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/*
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* This setup will only allow for one additional hose
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*/
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#define ADDR_TO_HOSE(x) ((x) >> 31)
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#define STRIP_HOSE(x) ((x) & 0x7fffffff)
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static void tsunami_intr_enable __P((int));
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static void tsunami_intr_disable __P((int));
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static u_int8_t
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tsunami_inb(u_int32_t port)
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{
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int hose = ADDR_TO_HOSE(port);
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port = STRIP_HOSE(port);
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alpha_mb();
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return ldbu(KV(TSUNAMI_IO(hose) + port));
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}
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static u_int16_t
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tsunami_inw(u_int32_t port)
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{
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int hose = ADDR_TO_HOSE(port);
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port = STRIP_HOSE(port);
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alpha_mb();
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return ldwu(KV(TSUNAMI_IO(hose) + port));
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}
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static u_int32_t
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tsunami_inl(u_int32_t port)
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{
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int hose = ADDR_TO_HOSE(port);
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port = STRIP_HOSE(port);
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alpha_mb();
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return ldl(KV(TSUNAMI_IO(hose) + port));
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}
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static void
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tsunami_outb(u_int32_t port, u_int8_t data)
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{
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int hose = ADDR_TO_HOSE(port);
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port = STRIP_HOSE(port);
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stb(KV(TSUNAMI_IO(hose) + port), data);
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alpha_mb();
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}
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static void
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tsunami_outw(u_int32_t port, u_int16_t data)
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{
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int hose = ADDR_TO_HOSE(port);
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port = STRIP_HOSE(port);
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stw(KV(TSUNAMI_IO(hose) + port), data);
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alpha_mb();
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}
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static void
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tsunami_outl(u_int32_t port, u_int32_t data)
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{
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int hose = ADDR_TO_HOSE(port);
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port = STRIP_HOSE(port);
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stl(KV(TSUNAMI_IO(hose) + port), data);
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alpha_mb();
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}
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static u_int8_t
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tsunami_readb(u_int32_t pa)
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{
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int hose = ADDR_TO_HOSE(pa);
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pa = STRIP_HOSE(pa);
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alpha_mb();
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return ldbu(KV(TSUNAMI_MEM(hose) + pa));
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}
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static u_int16_t
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tsunami_readw(u_int32_t pa)
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{
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int hose = ADDR_TO_HOSE(pa);
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pa = STRIP_HOSE(pa);
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alpha_mb();
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return ldwu(KV(TSUNAMI_MEM(hose) + pa));
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}
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static u_int32_t
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tsunami_readl(u_int32_t pa)
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{
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int hose = ADDR_TO_HOSE(pa);
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pa = STRIP_HOSE(pa);
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alpha_mb();
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return ldl(KV(TSUNAMI_MEM(hose) + pa));
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}
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static void
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tsunami_writeb(u_int32_t pa, u_int8_t data)
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{
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int hose = ADDR_TO_HOSE(pa);
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pa = STRIP_HOSE(pa);
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stb(KV(TSUNAMI_MEM(hose) + pa), data);
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alpha_mb();
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}
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static void
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tsunami_writew(u_int32_t pa, u_int16_t data)
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{
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int hose = ADDR_TO_HOSE(pa);
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pa = STRIP_HOSE(pa);
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stw(KV(TSUNAMI_MEM(hose) + pa), data);
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alpha_mb();
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}
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static void
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tsunami_writel(u_int32_t pa, u_int32_t data)
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{
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int hose = ADDR_TO_HOSE(pa);
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pa = STRIP_HOSE(pa);
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stl(KV(TSUNAMI_MEM(hose) + pa), data);
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alpha_mb();
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}
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static int
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tsunami_maxdevs(u_int b)
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{
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return 12; /* XXX */
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}
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static void
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tsunami_clear_abort(void)
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{
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alpha_mb();
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alpha_pal_draina();
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}
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static int
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tsunami_check_abort(void)
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{
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/* u_int32_t errbits;*/
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int ba = 0;
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alpha_pal_draina();
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alpha_mb();
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#if 0
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errbits = REGVAL(TSUNAMI_CSR_TSUNAMI_ERR);
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if (errbits & (TSUNAMI_ERR_RCVD_MAS_ABT|TSUNAMI_ERR_RCVD_TAR_ABT))
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ba = 1;
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if (errbits) {
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REGVAL(TSUNAMI_CSR_TSUNAMI_ERR) = errbits;
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alpha_mb();
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alpha_pal_draina();
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}
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#endif
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return ba;
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}
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#define TSUNAMI_CFGADDR(b, s, f, r, h) \
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KV(TSUNAMI_CONF(h) | ((b) << 16) | ((s) << 11) | ((f) << 8) | (r))
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#define CFGREAD(h, b, s, f, r, op, width, type) \
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int bus; \
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vm_offset_t va; \
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type data; \
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if (h == (u_int8_t)-1) \
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h = tsunami_hose_from_bus(b); \
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bus = tsunami_bus_within_hose(h, b) ? b : 0; \
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va = TSUNAMI_CFGADDR(bus, s, f, r, h); \
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tsunami_clear_abort(); \
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if (badaddr((caddr_t)va, width)) { \
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tsunami_check_abort(); \
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return ~0; \
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} \
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data = ##op##(va); \
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if (tsunami_check_abort()) \
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return ~0; \
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return data;
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#define CFWRITE(h, b, s, f, r, data, op, width) \
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int bus; \
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vm_offset_t va; \
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if (h == (u_int8_t)-1) \
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h = tsunami_hose_from_bus(b); \
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bus = tsunami_bus_within_hose(h, b) ? b : 0; \
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va = TSUNAMI_CFGADDR(bus, s, f, r, h); \
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tsunami_clear_abort(); \
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if (badaddr((caddr_t)va, width)) \
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return; \
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##op##(va, data); \
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tsunami_check_abort();
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static u_int8_t
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tsunami_cfgreadb(u_int h, u_int b, u_int s, u_int f, u_int r)
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{
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CFGREAD(h, b, s, f, r, ldbu, 1, u_int8_t)
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}
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static u_int16_t
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tsunami_cfgreadw(u_int h, u_int b, u_int s, u_int f, u_int r)
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{
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CFGREAD(h, b, s, f, r, ldwu, 2, u_int16_t)
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}
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static u_int32_t
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tsunami_cfgreadl(u_int h, u_int b, u_int s, u_int f, u_int r)
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{
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CFGREAD(h, b, s, f, r, ldl, 4, u_int32_t)
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}
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static void
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tsunami_cfgwriteb(u_int h, u_int b, u_int s, u_int f, u_int r, u_int8_t data)
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{
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CFWRITE(h, b, s, f, r, data, stb, 1)
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}
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static void
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tsunami_cfgwritew(u_int h, u_int b, u_int s, u_int f, u_int r, u_int16_t data)
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{
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CFWRITE(h, b, s, f, r, data, stw, 2)
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}
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static void
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tsunami_cfgwritel(u_int h, u_int b, u_int s, u_int f, u_int r, u_int32_t data)
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{
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CFWRITE(h, b, s, f, r, data, stl, 4)
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}
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vm_offset_t
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tsunami_cvt_bwx(vm_offset_t addr)
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{
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int hose;
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vm_offset_t laddr;
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laddr = addr & 0xffffffffUL;
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hose = ADDR_TO_HOSE(laddr);
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laddr = STRIP_HOSE(addr);
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laddr |= TSUNAMI_MEM(hose);
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return (KV(laddr));
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}
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vm_offset_t
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tsunami_cvt_dense(vm_offset_t addr)
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{
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return tsunami_cvt_bwx(addr);
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}
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/*
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* There doesn't appear to be an hae on this platform
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*/
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static u_int64_t
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tsunami_read_hae(void)
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{
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return 0;
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}
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static void
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tsunami_write_hae(u_int64_t hae)
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{
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}
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static int tsunami_probe(device_t dev);
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static int tsunami_attach(device_t dev);
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static int tsunami_setup_intr(device_t dev, device_t child,
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struct resource *irq, int flags,
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driver_intr_t *intr, void *arg, void **cookiep);
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static int tsunami_teardown_intr(device_t dev, device_t child,
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struct resource *irq, void *cookie);
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static device_method_t tsunami_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, tsunami_probe),
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DEVMETHOD(device_attach, tsunami_attach),
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/* Bus interface */
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DEVMETHOD(bus_print_child, bus_generic_print_child),
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DEVMETHOD(bus_alloc_resource, pci_alloc_resource),
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DEVMETHOD(bus_release_resource, pci_release_resource),
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DEVMETHOD(bus_activate_resource, pci_activate_resource),
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DEVMETHOD(bus_deactivate_resource, pci_deactivate_resource),
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DEVMETHOD(bus_setup_intr, tsunami_setup_intr),
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DEVMETHOD(bus_teardown_intr, tsunami_teardown_intr),
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{ 0, 0 }
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};
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static driver_t tsunami_driver = {
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"tsunami",
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tsunami_methods,
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sizeof(struct tsunami_softc),
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};
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static void
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pchip_init(volatile tsunami_pchip *pchip, int index)
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{
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int i;
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/*
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* initialize the direct map DMA windows.
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*
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* leave window 0 untouched; we'll set that up for S/G DMA for
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* isa devices later in the boot process
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*
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* window 1 goes at 2GB and has a length of 1 GB. It maps
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* physical address 0 - 1GB. The SRM console typically sets
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* this window up here.
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*/
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pchip->wsba[1].reg = (2UL*1024*1024*1024) | WINDOW_ENABLE;
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pchip->wsm[1].reg = (1UL*1024*1024*1024 - 1) & 0xfff00000UL;
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pchip->tba[1].reg = 0;
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/*
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* window 2 goes at 3GB and has a length of 1 GB. It maps
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* physical address 1GB-2GB.
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*/
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pchip->wsba[2].reg = (3UL*1024*1024*1024) | WINDOW_ENABLE;
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pchip->wsm[2].reg = (1UL*1024*1024*1024 - 1) & 0xfff00000UL;
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pchip->tba[2].reg = 1UL*1024*1024*1024;
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/*
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* window 3 is disabled. The SRM console typically leaves it
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* disabled
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*/
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pchip->wsba[3].reg = 0;
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alpha_mb();
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if(bootverbose) {
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printf("pchip%d:\n", index);
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for (i = 0; i < 4; i++) {
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printf("\twsba[%d].reg = 0x%lx\n",
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i, pchip->wsba[i].reg);
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printf("\t wsm[%d].reg = 0x%lx\n",
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i, pchip->wsm[i].reg);
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printf("\t tba[%d].reg = 0x%lx\n",
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i, pchip->tba[i].reg);
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}
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}
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}
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#define TSUNAMI_SGMAP_BASE (8*1024*1024)
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#define TSUNAMI_SGMAP_SIZE (8*1024*1024)
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static void
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tsunami_sgmap_invalidate(void)
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{
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alpha_mb();
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switch (num_pchips) {
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case 2:
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pchip[1]->tlbia.reg = (u_int64_t)0;
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case 1:
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pchip[0]->tlbia.reg = (u_int64_t)0;
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}
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alpha_mb();
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}
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static void
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tsunami_sgmap_map(void *arg, vm_offset_t ba, vm_offset_t pa)
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{
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u_int64_t *sgtable = arg;
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int index = alpha_btop(ba - TSUNAMI_SGMAP_BASE);
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if (pa) {
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if (pa > (1L<<32))
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panic("tsunami_sgmap_map: can't map address 0x%lx", pa);
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sgtable[index] = ((pa >> 13) << 1) | 1;
|
|
} else {
|
|
sgtable[index] = 0;
|
|
}
|
|
alpha_mb();
|
|
tsunami_sgmap_invalidate();
|
|
}
|
|
|
|
|
|
static void
|
|
tsunami_init_sgmap(void)
|
|
{
|
|
void *sgtable;
|
|
int i;
|
|
|
|
sgtable = contigmalloc(8192, M_DEVBUF, M_NOWAIT,
|
|
0, (1L<<34),
|
|
32*1024, (1L<<34));
|
|
if (!sgtable)
|
|
panic("tsunami_init_sgmap: can't allocate page table");
|
|
|
|
for(i=0; i < num_pchips; i++){
|
|
pchip[i]->tba[0].reg =
|
|
pmap_kextract((vm_offset_t) sgtable);
|
|
pchip[i]->wsba[0].reg |= WINDOW_ENABLE | WINDOW_SCATTER_GATHER;
|
|
}
|
|
|
|
chipset.sgmap = sgmap_map_create(TSUNAMI_SGMAP_BASE,
|
|
TSUNAMI_SGMAP_BASE + TSUNAMI_SGMAP_SIZE,
|
|
tsunami_sgmap_map, sgtable);
|
|
}
|
|
|
|
void
|
|
tsunami_init()
|
|
{
|
|
static int initted = 0;
|
|
|
|
if (initted) return;
|
|
initted = 1;
|
|
|
|
chipset = tsunami_chipset;
|
|
platform.pci_intr_enable = tsunami_intr_enable;
|
|
platform.pci_intr_disable = tsunami_intr_disable;
|
|
alpha_XXX_dmamap_or = 2UL * 1024UL * 1024UL * 1024UL;
|
|
|
|
if (platform.pci_intr_init)
|
|
platform.pci_intr_init();
|
|
}
|
|
|
|
static int
|
|
tsunami_probe(device_t dev)
|
|
{
|
|
int *hose;
|
|
int i;
|
|
if (tsunami0)
|
|
return ENXIO;
|
|
tsunami0 = dev;
|
|
device_set_desc(dev, "21271 Core Logic chipset");
|
|
if(cchip->csc.reg & CSC_P1P)
|
|
num_pchips = 2;
|
|
else
|
|
num_pchips = 1;
|
|
|
|
pci_init_resources();
|
|
isa_init_intr();
|
|
|
|
for(i = 0; i < num_pchips; i++) {
|
|
hose = malloc(sizeof(int), M_DEVBUF, M_NOWAIT);
|
|
*hose = i;
|
|
device_add_child(dev, "pcib", i, hose);
|
|
pchip_init(pchip[i], i);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
tsunami_attach(device_t dev)
|
|
{
|
|
tsunami_init();
|
|
|
|
if (!platform.iointr) /* XXX */
|
|
set_iointr(alpha_dispatch_intr);
|
|
|
|
snprintf(chipset_type, sizeof(chipset_type), "tsunami");
|
|
chipset_bwx = 1;
|
|
|
|
chipset_ports = TSUNAMI_IO(0);
|
|
chipset_memory = TSUNAMI_MEM(0);
|
|
chipset_dense = TSUNAMI_MEM(0);
|
|
bus_generic_attach(dev);
|
|
tsunami_init_sgmap();
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
tsunami_setup_intr(device_t dev, device_t child,
|
|
struct resource *irq, int flags,
|
|
driver_intr_t *intr, void *arg, void **cookiep)
|
|
{
|
|
int error;
|
|
|
|
error = rman_activate_resource(irq);
|
|
if (error)
|
|
return error;
|
|
|
|
error = alpha_setup_intr(0x900 + (irq->r_start << 4),
|
|
intr, arg, cookiep,
|
|
&intrcnt[INTRCNT_EB164_IRQ + irq->r_start]);
|
|
if (error)
|
|
return error;
|
|
|
|
/* Enable PCI interrupt */
|
|
platform.pci_intr_enable(irq->r_start);
|
|
|
|
device_printf(child, "interrupting at TSUNAMI irq %d\n",
|
|
(int) irq->r_start);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
tsunami_teardown_intr(device_t dev, device_t child,
|
|
struct resource *irq, void *cookie)
|
|
{
|
|
|
|
alpha_teardown_intr(cookie);
|
|
return rman_deactivate_resource(irq);
|
|
|
|
}
|
|
|
|
|
|
/*
|
|
* Currently, all interrupts will be funneled through CPU 0
|
|
*/
|
|
|
|
static void
|
|
tsunami_intr_enable(int irq)
|
|
{
|
|
volatile u_int64_t *mask;
|
|
u_int64_t saved_mask;
|
|
|
|
mask = &cchip->dim0.reg;
|
|
saved_mask = *mask;
|
|
|
|
saved_mask |= (1UL << (unsigned long)irq);
|
|
*mask = saved_mask;
|
|
alpha_mb();
|
|
alpha_mb();
|
|
saved_mask = *mask;
|
|
alpha_mb();
|
|
alpha_mb();
|
|
}
|
|
|
|
static void
|
|
tsunami_intr_disable(int irq)
|
|
{
|
|
volatile u_int64_t *mask;
|
|
u_int64_t saved_mask;
|
|
|
|
mask = &cchip->dim0.reg;
|
|
saved_mask = *mask;
|
|
|
|
saved_mask &= ~(1UL << (unsigned long)irq);
|
|
*mask = saved_mask;
|
|
alpha_mb();
|
|
saved_mask = *mask;
|
|
alpha_mb();
|
|
alpha_mb();
|
|
|
|
}
|
|
|
|
|
|
|
|
DRIVER_MODULE(tsunami, root, tsunami_driver, tsunami_devclass, 0, 0);
|
|
|