8415f755f1
Since qemu does not implement the L2 cache, we get stuck forever waiting for a bit to be set when trying to invalidate it. To prevent that, we should bail out if the L2 cache is missing. One easy way to check this is L2CFG0 == 0 (since L2CSIZE always has at least one bit set in a valid implementation) (tested on qemu, rb800, and x5000) Reviewed by: jhibbits Sponsored by: Tag1 Consulting, Inc. Differential Revision: https://reviews.freebsd.org/D25225
144 lines
3.8 KiB
C
144 lines
3.8 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2011-2012 Semihalf.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/cdefs.h>
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#include <sys/types.h>
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#include <sys/param.h>
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#include <sys/proc.h>
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#include <sys/reboot.h>
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#include <vm/vm.h>
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#include <vm/pmap.h>
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#include <machine/machdep.h>
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#include <dev/fdt/fdt_common.h>
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#include <powerpc/mpc85xx/mpc85xx.h>
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extern void dcache_enable(void);
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extern void dcache_inval(void);
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extern void icache_enable(void);
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extern void icache_inval(void);
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extern void l2cache_enable(void);
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extern void l2cache_inval(void);
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extern void bpred_enable(void);
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void
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booke_enable_l1_cache(void)
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{
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uint32_t csr;
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/* Enable D-cache if applicable */
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csr = mfspr(SPR_L1CSR0);
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if ((csr & L1CSR0_DCE) == 0) {
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dcache_inval();
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dcache_enable();
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}
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csr = mfspr(SPR_L1CSR0);
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if ((boothowto & RB_VERBOSE) != 0 || (csr & L1CSR0_DCE) == 0)
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printf("L1 D-cache %sabled\n",
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(csr & L1CSR0_DCE) ? "en" : "dis");
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/* Enable L1 I-cache if applicable. */
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csr = mfspr(SPR_L1CSR1);
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if ((csr & L1CSR1_ICE) == 0) {
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icache_inval();
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icache_enable();
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}
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csr = mfspr(SPR_L1CSR1);
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if ((boothowto & RB_VERBOSE) != 0 || (csr & L1CSR1_ICE) == 0)
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printf("L1 I-cache %sabled\n",
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(csr & L1CSR1_ICE) ? "en" : "dis");
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}
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void
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booke_enable_l2_cache(void)
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{
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uint32_t csr;
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/* Enable L2 cache on E500mc */
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if ((((mfpvr() >> 16) & 0xFFFF) == FSL_E500mc) ||
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(((mfpvr() >> 16) & 0xFFFF) == FSL_E5500)) {
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csr = mfspr(SPR_L2CSR0);
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/*
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* Don't actually attempt to manipulate the L2 cache if
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* L2CFG0 is zero.
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*
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* Any chip with a working L2 cache will have a nonzero
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* L2CFG0, as it will have a nonzero L2CSIZE field.
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*
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* This fixes waiting forever for cache enable in qemu,
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* which does not implement the L2 cache.
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*/
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if (mfspr(SPR_L2CFG0) != 0 && (csr & L2CSR0_L2E) == 0) {
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l2cache_inval();
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l2cache_enable();
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}
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csr = mfspr(SPR_L2CSR0);
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if ((boothowto & RB_VERBOSE) != 0 || (csr & L2CSR0_L2E) == 0)
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printf("L2 cache %sabled\n",
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(csr & L2CSR0_L2E) ? "en" : "dis");
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}
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}
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void
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booke_enable_bpred(void)
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{
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uint32_t csr;
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bpred_enable();
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csr = mfspr(SPR_BUCSR);
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if ((boothowto & RB_VERBOSE) != 0 || (csr & BUCSR_BPEN) == 0)
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printf("Branch Predictor %sabled\n",
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(csr & BUCSR_BPEN) ? "en" : "dis");
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}
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void
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booke_disable_l2_cache(void)
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{
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}
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/* Return 0 on handled success, otherwise signal number. */
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int
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cpu_machine_check(struct thread *td, struct trapframe *frame, int *ucode)
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{
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register_t mcsr;
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mcsr = mfspr(SPR_MCSR);
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*ucode = BUS_OBJERR;
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return (SIGBUS);
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}
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