281 lines
6.4 KiB
ArmAsm
281 lines
6.4 KiB
ArmAsm
/*-
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* Copyright (c) 2002 Jake Burkholder.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <machine/asm.h>
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__FBSDID("$FreeBSD$");
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#include <machine/asi.h>
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#include <machine/ktr.h>
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#include <machine/asmacros.h>
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#include <machine/pstate.h>
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#include "assym.s"
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.register %g2, #ignore
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.register %g3, #ignore
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#define IPI_DONE(r1, r2, r3, r4) \
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lduw [PCPU(CPUMASK)], r4 ; \
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ATOMIC_CLEAR_INT(r1, r2, r3, r4)
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/*
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* Invalidate a physical page in the data cache. For UltraSPARC I and II.
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*/
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#if 0
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ENTRY(tl_ipi_spitfire_dcache_page_inval)
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#if KTR_COMPILE & KTR_SMP
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CATR(KTR_SMP, "ipi_dcache_page_inval: pa=%#lx"
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, %g1, %g2, %g3, 7, 8, 9)
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ldx [%g5 + ICA_PA], %g2
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stx %g2, [%g1 + KTR_PARM1]
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9:
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#endif
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ldx [%g5 + ICA_PA], %g6
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srlx %g6, PAGE_SHIFT - DC_TAG_SHIFT, %g6
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SET(cache, %g3, %g2)
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lduw [%g2 + DC_SIZE], %g3
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lduw [%g2 + DC_LINESIZE], %g4
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sub %g3, %g4, %g2
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1: ldxa [%g2] ASI_DCACHE_TAG, %g1
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srlx %g1, DC_VALID_SHIFT, %g3
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andcc %g3, DC_VALID_MASK, %g0
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bz,pt %xcc, 2f
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set DC_TAG_MASK, %g3
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sllx %g3, DC_TAG_SHIFT, %g3
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and %g1, %g3, %g1
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cmp %g1, %g6
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bne,a,pt %xcc, 2f
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nop
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stxa %g1, [%g2] ASI_DCACHE_TAG
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membar #Sync
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2: brgz,pt %g2, 1b
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sub %g2, %g4, %g2
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IPI_DONE(%g5, %g1, %g2, %g3)
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retry
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END(tl_ipi_spitfire_dcache_page_inval)
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/*
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* Invalidate a physical page in the instruction cache. For UltraSPARC I and
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* II.
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*/
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ENTRY(tl_ipi_spitfire_icache_page_inval)
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#if KTR_COMPILE & KTR_SMP
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CATR(KTR_SMP, "ipi_icache_page_inval: pa=%#lx"
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, %g1, %g2, %g3, 7, 8, 9)
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ldx [%g5 + ICA_PA], %g2
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stx %g2, [%g1 + KTR_PARM1]
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9:
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#endif
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ldx [%g5 + ICA_PA], %g6
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srlx %g6, PAGE_SHIFT - IC_TAG_SHIFT, %g6
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SET(cache, %g3, %g2)
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lduw [%g2 + IC_SIZE], %g3
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lduw [%g2 + IC_LINESIZE], %g4
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sub %g3, %g4, %g2
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1: ldda [%g2] ASI_ICACHE_TAG, %g0 /*, %g1 */
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srlx %g1, IC_VALID_SHIFT, %g3
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andcc %g3, IC_VALID_MASK, %g0
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bz,pt %xcc, 2f
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set IC_TAG_MASK, %g3
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sllx %g3, IC_TAG_SHIFT, %g3
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and %g1, %g3, %g1
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cmp %g1, %g6
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bne,a,pt %xcc, 2f
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nop
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stxa %g1, [%g2] ASI_ICACHE_TAG
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membar #Sync
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2: brgz,pt %g2, 1b
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sub %g2, %g4, %g2
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IPI_DONE(%g5, %g1, %g2, %g3)
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retry
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END(tl_ipi_spitfire_icache_page_inval)
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/*
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* Invalidate a physical page in the data cache. For UltraSPARC III.
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*/
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ENTRY(tl_ipi_cheetah_dcache_page_inval)
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#if KTR_COMPILE & KTR_SMP
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CATR(KTR_SMP, "ipi_dcache_page_inval: pa=%#lx"
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, %g1, %g2, %g3, 7, 8, 9)
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ldx [%g5 + ICA_PA], %g2
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stx %g2, [%g1 + KTR_PARM1]
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9:
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#endif
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ldx [%g5 + ICA_PA], %g1
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set PAGE_SIZE, %g2
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add %g1, %g2, %g3
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SET(cache, %g4, %g2)
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lduw [%g2 + DC_LINESIZE], %g2
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1: stxa %g0, [%g1] ASI_DCACHE_INVALIDATE
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membar #Sync
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add %g1, %g2, %g1
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cmp %g1, %g3
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blt,a,pt %xcc, 1b
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nop
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IPI_DONE(%g5, %g1, %g2, %g3)
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retry
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END(tl_ipi_cheetah_dcache_page_inval)
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#endif
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/*
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* Trigger a softint at the desired level.
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*/
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ENTRY(tl_ipi_level)
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#if KTR_COMPILE & KTR_SMP
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CATR(KTR_SMP, "tl_ipi_level: cpuid=%d mid=%d d1=%#lx d2=%#lx"
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, %g1, %g2, %g3, 7, 8, 9)
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lduw [PCPU(CPUID)], %g2
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stx %g2, [%g1 + KTR_PARM1]
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lduw [PCPU(MID)], %g2
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stx %g2, [%g1 + KTR_PARM2]
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stx %g4, [%g1 + KTR_PARM3]
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stx %g5, [%g1 + KTR_PARM4]
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9:
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#endif
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mov 1, %g2
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sllx %g2, %g1, %g2
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wr %g2, 0, %set_softint
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retry
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END(tl_ipi_level)
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/*
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* Demap a page from the dtlb and/or itlb.
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*/
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#if 0
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ENTRY(tl_ipi_tlb_page_demap)
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#if KTR_COMPILE & KTR_SMP
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CATR(KTR_SMP, "ipi_tlb_page_demap: pm=%p va=%#lx"
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, %g1, %g2, %g3, 7, 8, 9)
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ldx [%g5 + ITA_PMAP], %g2
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stx %g2, [%g1 + KTR_PARM1]
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ldx [%g5 + ITA_VA], %g2
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stx %g2, [%g1 + KTR_PARM2]
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9:
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#endif
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ldx [%g5 + ITA_PMAP], %g1
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SET(kernel_pmap_store, %g3, %g2)
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mov TLB_DEMAP_NUCLEUS | TLB_DEMAP_PAGE, %g3
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cmp %g1, %g2
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movne %xcc, TLB_DEMAP_PRIMARY | TLB_DEMAP_PAGE, %g3
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ldx [%g5 + ITA_VA], %g2
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or %g2, %g3, %g2
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stxa %g0, [%g2] ASI_DMMU_DEMAP
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stxa %g0, [%g2] ASI_IMMU_DEMAP
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membar #Sync
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IPI_DONE(%g5, %g1, %g2, %g3)
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retry
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END(tl_ipi_tlb_page_demap)
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/*
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* Demap a range of pages from the dtlb and itlb.
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*/
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ENTRY(tl_ipi_tlb_range_demap)
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#if KTR_COMPILE & KTR_SMP
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CATR(KTR_SMP, "ipi_tlb_range_demap: pm=%p start=%#lx end=%#lx"
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, %g1, %g2, %g3, 7, 8, 9)
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ldx [%g5 + ITA_PMAP], %g2
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stx %g2, [%g1 + KTR_PARM1]
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ldx [%g5 + ITA_START], %g2
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stx %g2, [%g1 + KTR_PARM2]
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ldx [%g5 + ITA_END], %g2
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stx %g2, [%g1 + KTR_PARM3]
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9:
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#endif
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ldx [%g5 + ITA_PMAP], %g1
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SET(kernel_pmap_store, %g3, %g2)
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mov TLB_DEMAP_NUCLEUS | TLB_DEMAP_PAGE, %g3
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cmp %g1, %g2
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movne %xcc, TLB_DEMAP_PRIMARY | TLB_DEMAP_PAGE, %g3
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ldx [%g5 + ITA_START], %g1
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ldx [%g5 + ITA_END], %g2
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set PAGE_SIZE, %g6
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1: or %g1, %g3, %g4
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stxa %g0, [%g4] ASI_DMMU_DEMAP
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stxa %g0, [%g4] ASI_IMMU_DEMAP
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membar #Sync
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add %g1, %g6, %g1
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cmp %g1, %g2
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blt,a,pt %xcc, 1b
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nop
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IPI_DONE(%g5, %g1, %g2, %g3)
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retry
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END(tl_ipi_tlb_range_demap)
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/*
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* Demap the primary context from the dtlb and itlb.
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*/
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ENTRY(tl_ipi_tlb_context_demap)
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#if KTR_COMPILE & KTR_SMP
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CATR(KTR_SMP, "ipi_tlb_page_demap: pm=%p va=%#lx"
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, %g1, %g2, %g3, 7, 8, 9)
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ldx [%g5 + ITA_PMAP], %g2
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stx %g2, [%g1 + KTR_PARM1]
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ldx [%g5 + ITA_VA], %g2
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stx %g2, [%g1 + KTR_PARM2]
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9:
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#endif
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mov TLB_DEMAP_PRIMARY | TLB_DEMAP_CONTEXT, %g1
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stxa %g0, [%g1] ASI_DMMU_DEMAP
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stxa %g0, [%g1] ASI_IMMU_DEMAP
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membar #Sync
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IPI_DONE(%g5, %g1, %g2, %g3)
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retry
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END(tl_ipi_tlb_context_demap)
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#endif
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