16969d1448
nvmecontrol tries to upload firmware in chunks as large as it thinks
the device permits. It fails to take into account the FWUG value used
by some drives to advertise the size and alignment limits for firmware
chunks.
- Use the firwmare update granularity value from the
- If the granularity is not reported or not restricted, fall back to
the previously existing logic that calculates the max transfer
size based on MDTS.
- Add firmware update granularity to the identify-controller output.
Reviewed by: imp (previous version), chuck
Obtained from: Dell EMC Isilon
MFC after: 1 week
Sponsored by: Dell EMC Isilon
Differential Revision: https://reviews.freebsd.org/D26390
262 lines
11 KiB
C
262 lines
11 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (C) 2012-2013 Intel Corporation
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* All rights reserved.
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* Copyright (C) 2018-2019 Alexander Motin <mav@FreeBSD.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <ctype.h>
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#include <err.h>
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#include <fcntl.h>
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#include <stddef.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <unistd.h>
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#include "nvmecontrol.h"
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#include "nvmecontrol_ext.h"
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void
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nvme_print_controller(struct nvme_controller_data *cdata)
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{
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uint8_t str[128];
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char cbuf[UINT128_DIG + 1];
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uint16_t oncs, oacs;
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uint8_t compare, write_unc, dsm, t;
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uint8_t security, fmt, fw, nsmgmt;
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uint8_t fw_slot1_ro, fw_num_slots;
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uint8_t ns_smart;
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uint8_t sqes_max, sqes_min;
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uint8_t cqes_max, cqes_min;
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uint8_t fwug;
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oncs = cdata->oncs;
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compare = (oncs >> NVME_CTRLR_DATA_ONCS_COMPARE_SHIFT) &
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NVME_CTRLR_DATA_ONCS_COMPARE_MASK;
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write_unc = (oncs >> NVME_CTRLR_DATA_ONCS_WRITE_UNC_SHIFT) &
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NVME_CTRLR_DATA_ONCS_WRITE_UNC_MASK;
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dsm = (oncs >> NVME_CTRLR_DATA_ONCS_DSM_SHIFT) &
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NVME_CTRLR_DATA_ONCS_DSM_MASK;
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oacs = cdata->oacs;
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security = (oacs >> NVME_CTRLR_DATA_OACS_SECURITY_SHIFT) &
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NVME_CTRLR_DATA_OACS_SECURITY_MASK;
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fmt = (oacs >> NVME_CTRLR_DATA_OACS_FORMAT_SHIFT) &
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NVME_CTRLR_DATA_OACS_FORMAT_MASK;
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fw = (oacs >> NVME_CTRLR_DATA_OACS_FIRMWARE_SHIFT) &
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NVME_CTRLR_DATA_OACS_FIRMWARE_MASK;
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nsmgmt = (oacs >> NVME_CTRLR_DATA_OACS_NSMGMT_SHIFT) &
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NVME_CTRLR_DATA_OACS_NSMGMT_MASK;
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fw_num_slots = (cdata->frmw >> NVME_CTRLR_DATA_FRMW_NUM_SLOTS_SHIFT) &
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NVME_CTRLR_DATA_FRMW_NUM_SLOTS_MASK;
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fw_slot1_ro = (cdata->frmw >> NVME_CTRLR_DATA_FRMW_SLOT1_RO_SHIFT) &
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NVME_CTRLR_DATA_FRMW_SLOT1_RO_MASK;
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fwug = cdata->fwug;
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ns_smart = (cdata->lpa >> NVME_CTRLR_DATA_LPA_NS_SMART_SHIFT) &
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NVME_CTRLR_DATA_LPA_NS_SMART_MASK;
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sqes_min = (cdata->sqes >> NVME_CTRLR_DATA_SQES_MIN_SHIFT) &
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NVME_CTRLR_DATA_SQES_MIN_MASK;
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sqes_max = (cdata->sqes >> NVME_CTRLR_DATA_SQES_MAX_SHIFT) &
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NVME_CTRLR_DATA_SQES_MAX_MASK;
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cqes_min = (cdata->cqes >> NVME_CTRLR_DATA_CQES_MIN_SHIFT) &
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NVME_CTRLR_DATA_CQES_MIN_MASK;
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cqes_max = (cdata->cqes >> NVME_CTRLR_DATA_CQES_MAX_SHIFT) &
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NVME_CTRLR_DATA_CQES_MAX_MASK;
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printf("Controller Capabilities/Features\n");
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printf("================================\n");
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printf("Vendor ID: %04x\n", cdata->vid);
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printf("Subsystem Vendor ID: %04x\n", cdata->ssvid);
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nvme_strvis(str, cdata->sn, sizeof(str), NVME_SERIAL_NUMBER_LENGTH);
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printf("Serial Number: %s\n", str);
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nvme_strvis(str, cdata->mn, sizeof(str), NVME_MODEL_NUMBER_LENGTH);
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printf("Model Number: %s\n", str);
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nvme_strvis(str, cdata->fr, sizeof(str), NVME_FIRMWARE_REVISION_LENGTH);
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printf("Firmware Version: %s\n", str);
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printf("Recommended Arb Burst: %d\n", cdata->rab);
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printf("IEEE OUI Identifier: %02x %02x %02x\n",
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cdata->ieee[0], cdata->ieee[1], cdata->ieee[2]);
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printf("Multi-Path I/O Capabilities: %s%s%s%s%s\n",
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(cdata->mic == 0) ? "Not Supported" : "",
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((cdata->mic >> NVME_CTRLR_DATA_MIC_ANAR_SHIFT) &
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NVME_CTRLR_DATA_MIC_SRIOVVF_MASK) ? "Asymmetric, " : "",
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((cdata->mic >> NVME_CTRLR_DATA_MIC_SRIOVVF_SHIFT) &
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NVME_CTRLR_DATA_MIC_SRIOVVF_MASK) ? "SR-IOV VF, " : "",
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((cdata->mic >> NVME_CTRLR_DATA_MIC_MCTRLRS_SHIFT) &
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NVME_CTRLR_DATA_MIC_MCTRLRS_MASK) ? "Multiple controllers, " : "",
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((cdata->mic >> NVME_CTRLR_DATA_MIC_MPORTS_SHIFT) &
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NVME_CTRLR_DATA_MIC_MPORTS_MASK) ? "Multiple ports" : "");
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/* TODO: Use CAP.MPSMIN to determine true memory page size. */
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printf("Max Data Transfer Size: ");
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if (cdata->mdts == 0)
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printf("Unlimited\n");
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else
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printf("%ld bytes\n", PAGE_SIZE * (1L << cdata->mdts));
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printf("Controller ID: 0x%04x\n", cdata->ctrlr_id);
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printf("Version: %d.%d.%d\n",
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(cdata->ver >> 16) & 0xffff, (cdata->ver >> 8) & 0xff,
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cdata->ver & 0xff);
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printf("\n");
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printf("Admin Command Set Attributes\n");
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printf("============================\n");
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printf("Security Send/Receive: %s\n",
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security ? "Supported" : "Not Supported");
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printf("Format NVM: %s\n",
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fmt ? "Supported" : "Not Supported");
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printf("Firmware Activate/Download: %s\n",
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fw ? "Supported" : "Not Supported");
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printf("Namespace Managment: %s\n",
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nsmgmt ? "Supported" : "Not Supported");
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printf("Device Self-test: %sSupported\n",
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((oacs >> NVME_CTRLR_DATA_OACS_SELFTEST_SHIFT) &
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NVME_CTRLR_DATA_OACS_SELFTEST_MASK) ? "" : "Not ");
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printf("Directives: %sSupported\n",
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((oacs >> NVME_CTRLR_DATA_OACS_DIRECTIVES_SHIFT) &
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NVME_CTRLR_DATA_OACS_DIRECTIVES_MASK) ? "" : "Not ");
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printf("NVMe-MI Send/Receive: %sSupported\n",
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((oacs >> NVME_CTRLR_DATA_OACS_NVMEMI_SHIFT) &
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NVME_CTRLR_DATA_OACS_NVMEMI_MASK) ? "" : "Not ");
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printf("Virtualization Management: %sSupported\n",
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((oacs >> NVME_CTRLR_DATA_OACS_VM_SHIFT) &
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NVME_CTRLR_DATA_OACS_VM_MASK) ? "" : "Not ");
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printf("Doorbell Buffer Config: %sSupported\n",
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((oacs >> NVME_CTRLR_DATA_OACS_DBBUFFER_SHIFT) &
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NVME_CTRLR_DATA_OACS_DBBUFFER_MASK) ? "" : "Not ");
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printf("Get LBA Status: %sSupported\n",
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((oacs >> NVME_CTRLR_DATA_OACS_GETLBA_SHIFT) &
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NVME_CTRLR_DATA_OACS_GETLBA_MASK) ? "" : "Not ");
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printf("Sanitize: ");
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if (cdata->sanicap != 0) {
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printf("%s%s%s\n",
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((cdata->sanicap >> NVME_CTRLR_DATA_SANICAP_CES_SHIFT) &
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NVME_CTRLR_DATA_SANICAP_CES_MASK) ? "crypto, " : "",
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((cdata->sanicap >> NVME_CTRLR_DATA_SANICAP_BES_SHIFT) &
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NVME_CTRLR_DATA_SANICAP_BES_MASK) ? "block, " : "",
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((cdata->sanicap >> NVME_CTRLR_DATA_SANICAP_OWS_SHIFT) &
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NVME_CTRLR_DATA_SANICAP_OWS_MASK) ? "overwrite" : "");
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} else {
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printf("Not Supported\n");
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}
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printf("Abort Command Limit: %d\n", cdata->acl+1);
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printf("Async Event Request Limit: %d\n", cdata->aerl+1);
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printf("Number of Firmware Slots: ");
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if (fw != 0)
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printf("%d\n", fw_num_slots);
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else
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printf("N/A\n");
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printf("Firmware Slot 1 Read-Only: ");
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if (fw != 0)
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printf("%s\n", fw_slot1_ro ? "Yes" : "No");
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else
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printf("N/A\n");
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printf("Per-Namespace SMART Log: %s\n",
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ns_smart ? "Yes" : "No");
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printf("Error Log Page Entries: %d\n", cdata->elpe+1);
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printf("Number of Power States: %d\n", cdata->npss+1);
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if (cdata->ver >= 0x010200) {
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printf("Total NVM Capacity: %s bytes\n",
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uint128_to_str(to128(cdata->untncap.tnvmcap),
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cbuf, sizeof(cbuf)));
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printf("Unallocated NVM Capacity: %s bytes\n",
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uint128_to_str(to128(cdata->untncap.unvmcap),
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cbuf, sizeof(cbuf)));
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}
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printf("Firmware Update Granularity: %02x ", fwug);
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if (fwug == 0)
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printf("(Not Reported)\n");
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else if (fwug == 0xFF)
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printf("(No Granularity)\n");
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else
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printf("(%d bytes)\n", ((uint32_t)fwug << 12));
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printf("Host Buffer Preferred Size: %llu bytes\n",
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(long long unsigned)cdata->hmpre * 4096);
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printf("Host Buffer Minimum Size: %llu bytes\n",
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(long long unsigned)cdata->hmmin * 4096);
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printf("\n");
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printf("NVM Command Set Attributes\n");
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printf("==========================\n");
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printf("Submission Queue Entry Size\n");
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printf(" Max: %d\n", 1 << sqes_max);
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printf(" Min: %d\n", 1 << sqes_min);
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printf("Completion Queue Entry Size\n");
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printf(" Max: %d\n", 1 << cqes_max);
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printf(" Min: %d\n", 1 << cqes_min);
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printf("Number of Namespaces: %d\n", cdata->nn);
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printf("Compare Command: %s\n",
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compare ? "Supported" : "Not Supported");
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printf("Write Uncorrectable Command: %s\n",
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write_unc ? "Supported" : "Not Supported");
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printf("Dataset Management Command: %s\n",
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dsm ? "Supported" : "Not Supported");
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printf("Write Zeroes Command: %sSupported\n",
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((oncs >> NVME_CTRLR_DATA_ONCS_WRZERO_SHIFT) &
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NVME_CTRLR_DATA_ONCS_WRZERO_MASK) ? "" : "Not ");
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printf("Save Features: %sSupported\n",
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((oncs >> NVME_CTRLR_DATA_ONCS_SAVEFEAT_SHIFT) &
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NVME_CTRLR_DATA_ONCS_SAVEFEAT_MASK) ? "" : "Not ");
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printf("Reservations: %sSupported\n",
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((oncs >> NVME_CTRLR_DATA_ONCS_RESERV_SHIFT) &
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NVME_CTRLR_DATA_ONCS_RESERV_MASK) ? "" : "Not ");
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printf("Timestamp feature: %sSupported\n",
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((oncs >> NVME_CTRLR_DATA_ONCS_TIMESTAMP_SHIFT) &
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NVME_CTRLR_DATA_ONCS_TIMESTAMP_MASK) ? "" : "Not ");
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printf("Verify feature: %sSupported\n",
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((oncs >> NVME_CTRLR_DATA_ONCS_VERIFY_SHIFT) &
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NVME_CTRLR_DATA_ONCS_VERIFY_MASK) ? "" : "Not ");
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printf("Fused Operation Support: %s%s\n",
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(cdata->fuses == 0) ? "Not Supported" : "",
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((cdata->fuses >> NVME_CTRLR_DATA_FUSES_CNW_SHIFT) &
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NVME_CTRLR_DATA_FUSES_CNW_MASK) ? "Compare and Write" : "");
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printf("Format NVM Attributes: %s%s Erase, %s Format\n",
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((cdata->fna >> NVME_CTRLR_DATA_FNA_CRYPTO_ERASE_SHIFT) &
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NVME_CTRLR_DATA_FNA_CRYPTO_ERASE_MASK) ? "Crypto Erase, " : "",
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((cdata->fna >> NVME_CTRLR_DATA_FNA_ERASE_ALL_SHIFT) &
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NVME_CTRLR_DATA_FNA_ERASE_ALL_MASK) ? "All-NVM" : "Per-NS",
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((cdata->fna >> NVME_CTRLR_DATA_FNA_FORMAT_ALL_SHIFT) &
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NVME_CTRLR_DATA_FNA_FORMAT_ALL_MASK) ? "All-NVM" : "Per-NS");
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t = (cdata->vwc >> NVME_CTRLR_DATA_VWC_ALL_SHIFT) &
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NVME_CTRLR_DATA_VWC_ALL_MASK;
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printf("Volatile Write Cache: %s%s\n",
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((cdata->vwc >> NVME_CTRLR_DATA_VWC_PRESENT_SHIFT) &
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NVME_CTRLR_DATA_VWC_PRESENT_MASK) ? "Present" : "Not Present",
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(t == NVME_CTRLR_DATA_VWC_ALL_NO) ? ", no flush all" :
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(t == NVME_CTRLR_DATA_VWC_ALL_YES) ? ", flush all" : "");
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if (cdata->ver >= 0x010201)
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printf("\nNVM Subsystem Name: %.256s\n", cdata->subnqn);
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}
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