6a1e1c2c48
The bhyve virtual local APIC uses an instance-global flag to indicate when an error LVT is being delivered to prevent infinite recursion. Use a function argument instead to reduce the amount of instance-global state. This was inspired by reviewing the bhyve save/restore work, which saves a copy of the instance-global state for each vlapic. Smart OS bug: https://smartos.org/bugview/OS-7777 Submitted by: Patrick Mooney Reviewed by: markj, rgrimes Obtained from: SmartOS / Joyent Differential Revision: https://reviews.freebsd.org/D20365
192 lines
7.2 KiB
C
192 lines
7.2 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2013 Neel Natu <neel@freebsd.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _VLAPIC_PRIV_H_
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#define _VLAPIC_PRIV_H_
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#include <x86/apicreg.h>
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/*
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* APIC Register: Offset Description
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*/
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#define APIC_OFFSET_ID 0x20 /* Local APIC ID */
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#define APIC_OFFSET_VER 0x30 /* Local APIC Version */
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#define APIC_OFFSET_TPR 0x80 /* Task Priority Register */
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#define APIC_OFFSET_APR 0x90 /* Arbitration Priority */
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#define APIC_OFFSET_PPR 0xA0 /* Processor Priority Register */
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#define APIC_OFFSET_EOI 0xB0 /* EOI Register */
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#define APIC_OFFSET_RRR 0xC0 /* Remote read */
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#define APIC_OFFSET_LDR 0xD0 /* Logical Destination */
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#define APIC_OFFSET_DFR 0xE0 /* Destination Format Register */
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#define APIC_OFFSET_SVR 0xF0 /* Spurious Vector Register */
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#define APIC_OFFSET_ISR0 0x100 /* In Service Register */
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#define APIC_OFFSET_ISR1 0x110
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#define APIC_OFFSET_ISR2 0x120
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#define APIC_OFFSET_ISR3 0x130
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#define APIC_OFFSET_ISR4 0x140
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#define APIC_OFFSET_ISR5 0x150
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#define APIC_OFFSET_ISR6 0x160
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#define APIC_OFFSET_ISR7 0x170
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#define APIC_OFFSET_TMR0 0x180 /* Trigger Mode Register */
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#define APIC_OFFSET_TMR1 0x190
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#define APIC_OFFSET_TMR2 0x1A0
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#define APIC_OFFSET_TMR3 0x1B0
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#define APIC_OFFSET_TMR4 0x1C0
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#define APIC_OFFSET_TMR5 0x1D0
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#define APIC_OFFSET_TMR6 0x1E0
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#define APIC_OFFSET_TMR7 0x1F0
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#define APIC_OFFSET_IRR0 0x200 /* Interrupt Request Register */
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#define APIC_OFFSET_IRR1 0x210
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#define APIC_OFFSET_IRR2 0x220
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#define APIC_OFFSET_IRR3 0x230
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#define APIC_OFFSET_IRR4 0x240
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#define APIC_OFFSET_IRR5 0x250
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#define APIC_OFFSET_IRR6 0x260
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#define APIC_OFFSET_IRR7 0x270
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#define APIC_OFFSET_ESR 0x280 /* Error Status Register */
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#define APIC_OFFSET_CMCI_LVT 0x2F0 /* Local Vector Table (CMCI) */
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#define APIC_OFFSET_ICR_LOW 0x300 /* Interrupt Command Register */
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#define APIC_OFFSET_ICR_HI 0x310
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#define APIC_OFFSET_TIMER_LVT 0x320 /* Local Vector Table (Timer) */
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#define APIC_OFFSET_THERM_LVT 0x330 /* Local Vector Table (Thermal) */
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#define APIC_OFFSET_PERF_LVT 0x340 /* Local Vector Table (PMC) */
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#define APIC_OFFSET_LINT0_LVT 0x350 /* Local Vector Table (LINT0) */
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#define APIC_OFFSET_LINT1_LVT 0x360 /* Local Vector Table (LINT1) */
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#define APIC_OFFSET_ERROR_LVT 0x370 /* Local Vector Table (ERROR) */
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#define APIC_OFFSET_TIMER_ICR 0x380 /* Timer's Initial Count */
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#define APIC_OFFSET_TIMER_CCR 0x390 /* Timer's Current Count */
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#define APIC_OFFSET_TIMER_DCR 0x3E0 /* Timer's Divide Configuration */
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#define APIC_OFFSET_SELF_IPI 0x3F0 /* Self IPI register */
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#define VLAPIC_CTR0(vlapic, format) \
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VCPU_CTR0((vlapic)->vm, (vlapic)->vcpuid, format)
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#define VLAPIC_CTR1(vlapic, format, p1) \
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VCPU_CTR1((vlapic)->vm, (vlapic)->vcpuid, format, p1)
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#define VLAPIC_CTR2(vlapic, format, p1, p2) \
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VCPU_CTR2((vlapic)->vm, (vlapic)->vcpuid, format, p1, p2)
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#define VLAPIC_CTR3(vlapic, format, p1, p2, p3) \
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VCPU_CTR3((vlapic)->vm, (vlapic)->vcpuid, format, p1, p2, p3)
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#define VLAPIC_CTR_IRR(vlapic, msg) \
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do { \
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uint32_t *irrptr = &(vlapic)->apic_page->irr0; \
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irrptr[0] = irrptr[0]; /* silence compiler */ \
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VLAPIC_CTR1((vlapic), msg " irr0 0x%08x", irrptr[0 << 2]); \
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VLAPIC_CTR1((vlapic), msg " irr1 0x%08x", irrptr[1 << 2]); \
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VLAPIC_CTR1((vlapic), msg " irr2 0x%08x", irrptr[2 << 2]); \
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VLAPIC_CTR1((vlapic), msg " irr3 0x%08x", irrptr[3 << 2]); \
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VLAPIC_CTR1((vlapic), msg " irr4 0x%08x", irrptr[4 << 2]); \
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VLAPIC_CTR1((vlapic), msg " irr5 0x%08x", irrptr[5 << 2]); \
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VLAPIC_CTR1((vlapic), msg " irr6 0x%08x", irrptr[6 << 2]); \
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VLAPIC_CTR1((vlapic), msg " irr7 0x%08x", irrptr[7 << 2]); \
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} while (0)
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#define VLAPIC_CTR_ISR(vlapic, msg) \
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do { \
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uint32_t *isrptr = &(vlapic)->apic_page->isr0; \
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isrptr[0] = isrptr[0]; /* silence compiler */ \
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VLAPIC_CTR1((vlapic), msg " isr0 0x%08x", isrptr[0 << 2]); \
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VLAPIC_CTR1((vlapic), msg " isr1 0x%08x", isrptr[1 << 2]); \
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VLAPIC_CTR1((vlapic), msg " isr2 0x%08x", isrptr[2 << 2]); \
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VLAPIC_CTR1((vlapic), msg " isr3 0x%08x", isrptr[3 << 2]); \
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VLAPIC_CTR1((vlapic), msg " isr4 0x%08x", isrptr[4 << 2]); \
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VLAPIC_CTR1((vlapic), msg " isr5 0x%08x", isrptr[5 << 2]); \
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VLAPIC_CTR1((vlapic), msg " isr6 0x%08x", isrptr[6 << 2]); \
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VLAPIC_CTR1((vlapic), msg " isr7 0x%08x", isrptr[7 << 2]); \
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} while (0)
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enum boot_state {
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BS_INIT,
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BS_SIPI,
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BS_RUNNING
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};
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/*
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* 16 priority levels with at most one vector injected per level.
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*/
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#define ISRVEC_STK_SIZE (16 + 1)
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#define VLAPIC_MAXLVT_INDEX APIC_LVT_CMCI
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struct vlapic;
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struct vlapic_ops {
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int (*set_intr_ready)(struct vlapic *vlapic, int vector, bool level);
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int (*pending_intr)(struct vlapic *vlapic, int *vecptr);
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void (*intr_accepted)(struct vlapic *vlapic, int vector);
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void (*post_intr)(struct vlapic *vlapic, int hostcpu);
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void (*set_tmr)(struct vlapic *vlapic, int vector, bool level);
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void (*enable_x2apic_mode)(struct vlapic *vlapic);
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};
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struct vlapic {
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struct vm *vm;
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int vcpuid;
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struct LAPIC *apic_page;
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struct vlapic_ops ops;
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uint32_t esr_pending;
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struct callout callout; /* vlapic timer */
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struct bintime timer_fire_bt; /* callout expiry time */
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struct bintime timer_freq_bt; /* timer frequency */
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struct bintime timer_period_bt; /* timer period */
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struct mtx timer_mtx;
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/*
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* The 'isrvec_stk' is a stack of vectors injected by the local apic.
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* A vector is popped from the stack when the processor does an EOI.
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* The vector on the top of the stack is used to compute the
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* Processor Priority in conjunction with the TPR.
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*/
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uint8_t isrvec_stk[ISRVEC_STK_SIZE];
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int isrvec_stk_top;
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uint64_t msr_apicbase;
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enum boot_state boot_state;
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/*
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* Copies of some registers in the virtual APIC page. We do this for
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* a couple of different reasons:
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* - to be able to detect what changed (e.g. svr_last)
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* - to maintain a coherent snapshot of the register (e.g. lvt_last)
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*/
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uint32_t svr_last;
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uint32_t lvt_last[VLAPIC_MAXLVT_INDEX + 1];
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};
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void vlapic_init(struct vlapic *vlapic);
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void vlapic_cleanup(struct vlapic *vlapic);
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#endif /* _VLAPIC_PRIV_H_ */
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