473 lines
10 KiB
C
473 lines
10 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2015 Nahanni Systems, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/types.h>
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#include <sys/mman.h>
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#include <machine/vmm.h>
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#include <machine/vmm_snapshot.h>
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#include <vmmapi.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <errno.h>
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#include <unistd.h>
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#include "bhyvegc.h"
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#include "bhyverun.h"
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#include "config.h"
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#include "debug.h"
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#include "console.h"
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#include "inout.h"
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#include "pci_emul.h"
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#include "rfb.h"
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#include "vga.h"
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/*
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* bhyve Framebuffer device emulation.
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* BAR0 points to the current mode information.
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* BAR1 is the 32-bit framebuffer address.
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*
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* -s <b>,fbuf,wait,vga=on|io|off,rfb=<ip>:port,w=width,h=height
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*/
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static int fbuf_debug = 1;
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#define DEBUG_INFO 1
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#define DEBUG_VERBOSE 4
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#define DPRINTF(level, params) if (level <= fbuf_debug) PRINTLN params
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#define KB (1024UL)
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#define MB (1024 * 1024UL)
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#define DMEMSZ 128
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#define FB_SIZE (16*MB)
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#define COLS_MAX 1920
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#define ROWS_MAX 1200
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#define COLS_DEFAULT 1024
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#define ROWS_DEFAULT 768
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#define COLS_MIN 640
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#define ROWS_MIN 480
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struct pci_fbuf_softc {
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struct pci_devinst *fsc_pi;
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struct {
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uint32_t fbsize;
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uint16_t width;
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uint16_t height;
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uint16_t depth;
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uint16_t refreshrate;
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uint8_t reserved[116];
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} __packed memregs;
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/* rfb server */
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char *rfb_host;
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char *rfb_password;
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int rfb_port;
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int rfb_wait;
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int vga_enabled;
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int vga_full;
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uint32_t fbaddr;
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char *fb_base;
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uint16_t gc_width;
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uint16_t gc_height;
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void *vgasc;
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struct bhyvegc_image *gc_image;
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};
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static struct pci_fbuf_softc *fbuf_sc;
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#define PCI_FBUF_MSI_MSGS 4
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static void
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pci_fbuf_write(struct pci_devinst *pi, int baridx, uint64_t offset, int size,
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uint64_t value)
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{
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struct pci_fbuf_softc *sc;
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uint8_t *p;
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assert(baridx == 0);
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sc = pi->pi_arg;
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DPRINTF(DEBUG_VERBOSE,
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("fbuf wr: offset 0x%lx, size: %d, value: 0x%lx",
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offset, size, value));
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if (offset + size > DMEMSZ) {
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printf("fbuf: write too large, offset %ld size %d\n",
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offset, size);
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return;
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}
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p = (uint8_t *)&sc->memregs + offset;
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switch (size) {
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case 1:
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*p = value;
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break;
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case 2:
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*(uint16_t *)p = value;
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break;
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case 4:
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*(uint32_t *)p = value;
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break;
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case 8:
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*(uint64_t *)p = value;
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break;
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default:
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printf("fbuf: write unknown size %d\n", size);
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break;
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}
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if (!sc->gc_image->vgamode && sc->memregs.width == 0 &&
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sc->memregs.height == 0) {
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DPRINTF(DEBUG_INFO, ("switching to VGA mode"));
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sc->gc_image->vgamode = 1;
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sc->gc_width = 0;
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sc->gc_height = 0;
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} else if (sc->gc_image->vgamode && sc->memregs.width != 0 &&
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sc->memregs.height != 0) {
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DPRINTF(DEBUG_INFO, ("switching to VESA mode"));
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sc->gc_image->vgamode = 0;
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}
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}
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static uint64_t
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pci_fbuf_read(struct pci_devinst *pi, int baridx, uint64_t offset, int size)
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{
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struct pci_fbuf_softc *sc;
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uint8_t *p;
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uint64_t value;
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assert(baridx == 0);
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sc = pi->pi_arg;
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if (offset + size > DMEMSZ) {
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printf("fbuf: read too large, offset %ld size %d\n",
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offset, size);
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return (0);
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}
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p = (uint8_t *)&sc->memregs + offset;
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value = 0;
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switch (size) {
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case 1:
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value = *p;
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break;
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case 2:
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value = *(uint16_t *)p;
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break;
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case 4:
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value = *(uint32_t *)p;
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break;
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case 8:
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value = *(uint64_t *)p;
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break;
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default:
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printf("fbuf: read unknown size %d\n", size);
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break;
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}
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DPRINTF(DEBUG_VERBOSE,
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("fbuf rd: offset 0x%lx, size: %d, value: 0x%lx",
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offset, size, value));
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return (value);
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}
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static void
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pci_fbuf_baraddr(struct pci_devinst *pi, int baridx, int enabled,
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uint64_t address)
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{
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struct pci_fbuf_softc *sc;
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int prot;
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if (baridx != 1)
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return;
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sc = pi->pi_arg;
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if (!enabled) {
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if (vm_munmap_memseg(pi->pi_vmctx, sc->fbaddr, FB_SIZE) != 0)
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EPRINTLN("pci_fbuf: munmap_memseg failed");
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sc->fbaddr = 0;
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} else {
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prot = PROT_READ | PROT_WRITE;
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if (vm_mmap_memseg(pi->pi_vmctx, address, VM_FRAMEBUFFER, 0,
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FB_SIZE, prot) != 0)
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EPRINTLN("pci_fbuf: mmap_memseg failed");
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sc->fbaddr = address;
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}
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}
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static int
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pci_fbuf_parse_config(struct pci_fbuf_softc *sc, nvlist_t *nvl)
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{
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const char *value;
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char *cp;
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sc->rfb_wait = get_config_bool_node_default(nvl, "wait", false);
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/* Prefer "rfb" to "tcp". */
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value = get_config_value_node(nvl, "rfb");
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if (value == NULL)
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value = get_config_value_node(nvl, "tcp");
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if (value != NULL) {
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/*
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* IPv4 -- host-ip:port
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* IPv6 -- [host-ip%zone]:port
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* XXX for now port is mandatory for IPv4.
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*/
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if (value[0] == '[') {
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cp = strchr(value + 1, ']');
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if (cp == NULL || cp == value + 1) {
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EPRINTLN("fbuf: Invalid IPv6 address: \"%s\"",
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value);
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return (-1);
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}
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sc->rfb_host = strndup(value + 1, cp - (value + 1));
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cp++;
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if (*cp == ':') {
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cp++;
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if (*cp == '\0') {
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EPRINTLN(
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"fbuf: Missing port number: \"%s\"",
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value);
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return (-1);
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}
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sc->rfb_port = atoi(cp);
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} else if (*cp != '\0') {
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EPRINTLN("fbuf: Invalid IPv6 address: \"%s\"",
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value);
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return (-1);
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}
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} else {
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cp = strchr(value, ':');
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if (cp == NULL) {
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sc->rfb_port = atoi(value);
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} else {
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sc->rfb_host = strndup(value, cp - value);
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cp++;
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if (*cp == '\0') {
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EPRINTLN(
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"fbuf: Missing port number: \"%s\"",
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value);
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return (-1);
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}
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sc->rfb_port = atoi(cp);
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}
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}
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}
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value = get_config_value_node(nvl, "vga");
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if (value != NULL) {
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if (strcmp(value, "off") == 0) {
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sc->vga_enabled = 0;
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} else if (strcmp(value, "io") == 0) {
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sc->vga_enabled = 1;
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sc->vga_full = 0;
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} else if (strcmp(value, "on") == 0) {
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sc->vga_enabled = 1;
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sc->vga_full = 1;
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} else {
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EPRINTLN("fbuf: Invalid vga setting: \"%s\"", value);
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return (-1);
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}
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}
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value = get_config_value_node(nvl, "w");
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if (value != NULL) {
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sc->memregs.width = atoi(value);
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if (sc->memregs.width > COLS_MAX) {
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EPRINTLN("fbuf: width %d too large", sc->memregs.width);
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return (-1);
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}
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if (sc->memregs.width == 0)
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sc->memregs.width = 1920;
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}
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value = get_config_value_node(nvl, "h");
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if (value != NULL) {
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sc->memregs.height = atoi(value);
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if (sc->memregs.height > ROWS_MAX) {
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EPRINTLN("fbuf: height %d too large",
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sc->memregs.height);
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return (-1);
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}
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if (sc->memregs.height == 0)
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sc->memregs.height = 1080;
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}
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value = get_config_value_node(nvl, "password");
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if (value != NULL)
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sc->rfb_password = strdup(value);
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return (0);
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}
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static void
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pci_fbuf_render(struct bhyvegc *gc, void *arg)
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{
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struct pci_fbuf_softc *sc;
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sc = arg;
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if (sc->vga_full && sc->gc_image->vgamode) {
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/* TODO: mode switching to vga and vesa should use the special
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* EFI-bhyve protocol port.
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*/
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vga_render(gc, sc->vgasc);
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return;
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}
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if (sc->gc_width != sc->memregs.width ||
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sc->gc_height != sc->memregs.height) {
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bhyvegc_resize(gc, sc->memregs.width, sc->memregs.height);
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sc->gc_width = sc->memregs.width;
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sc->gc_height = sc->memregs.height;
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}
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}
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static int
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pci_fbuf_init(struct pci_devinst *pi, nvlist_t *nvl)
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{
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int error;
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struct pci_fbuf_softc *sc;
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if (fbuf_sc != NULL) {
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EPRINTLN("Only one frame buffer device is allowed.");
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return (-1);
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}
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sc = calloc(1, sizeof(struct pci_fbuf_softc));
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pi->pi_arg = sc;
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/* initialize config space */
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pci_set_cfgdata16(pi, PCIR_DEVICE, 0x40FB);
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pci_set_cfgdata16(pi, PCIR_VENDOR, 0xFB5D);
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pci_set_cfgdata8(pi, PCIR_CLASS, PCIC_DISPLAY);
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pci_set_cfgdata8(pi, PCIR_SUBCLASS, PCIS_DISPLAY_VGA);
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sc->fb_base = vm_create_devmem(pi->pi_vmctx, VM_FRAMEBUFFER,
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"framebuffer", FB_SIZE);
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if (sc->fb_base == MAP_FAILED) {
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error = -1;
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goto done;
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}
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error = pci_emul_alloc_bar(pi, 0, PCIBAR_MEM32, DMEMSZ);
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assert(error == 0);
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error = pci_emul_alloc_bar(pi, 1, PCIBAR_MEM32, FB_SIZE);
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assert(error == 0);
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error = pci_emul_add_msicap(pi, PCI_FBUF_MSI_MSGS);
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assert(error == 0);
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sc->memregs.fbsize = FB_SIZE;
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sc->memregs.width = COLS_DEFAULT;
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sc->memregs.height = ROWS_DEFAULT;
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sc->memregs.depth = 32;
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sc->vga_enabled = 1;
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sc->vga_full = 0;
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sc->fsc_pi = pi;
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error = pci_fbuf_parse_config(sc, nvl);
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if (error != 0)
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goto done;
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/* XXX until VGA rendering is enabled */
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if (sc->vga_full != 0) {
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EPRINTLN("pci_fbuf: VGA rendering not enabled");
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goto done;
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}
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DPRINTF(DEBUG_INFO, ("fbuf frame buffer base: %p [sz %lu]",
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sc->fb_base, FB_SIZE));
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console_init(sc->memregs.width, sc->memregs.height, sc->fb_base);
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console_fb_register(pci_fbuf_render, sc);
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if (sc->vga_enabled)
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sc->vgasc = vga_init(!sc->vga_full);
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sc->gc_image = console_get_image();
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fbuf_sc = sc;
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memset((void *)sc->fb_base, 0, FB_SIZE);
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error = rfb_init(sc->rfb_host, sc->rfb_port, sc->rfb_wait, sc->rfb_password);
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done:
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if (error)
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free(sc);
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return (error);
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}
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#ifdef BHYVE_SNAPSHOT
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static int
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pci_fbuf_snapshot(struct vm_snapshot_meta *meta)
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{
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int ret;
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SNAPSHOT_BUF_OR_LEAVE(fbuf_sc->fb_base, FB_SIZE, meta, ret, err);
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err:
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return (ret);
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}
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#endif
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static const struct pci_devemu pci_fbuf = {
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.pe_emu = "fbuf",
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.pe_init = pci_fbuf_init,
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.pe_barwrite = pci_fbuf_write,
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.pe_barread = pci_fbuf_read,
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.pe_baraddr = pci_fbuf_baraddr,
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#ifdef BHYVE_SNAPSHOT
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.pe_snapshot = pci_fbuf_snapshot,
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#endif
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};
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PCI_EMUL_SET(pci_fbuf);
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