This replaces the 'struct vm, int vcpuid' tuple passed to most API calls and is similar to the changes recently made in vmm(4) in the kernel. struct vcpu is an opaque type managed by libvmmapi. For now it stores a pointer to the VM context and an integer id. As an immediate effect this removes the divergence between the kernel and userland for the instruction emulation code introduced by the recent vmm(4) changes. Since this is a major change to the vmmapi API, bump VMMAPI_VERSION to 0x200 (2.0) and the shared library major version. While here (and since the major version is bumped), remove unused vcpu argument from vm_setup_pptdev_msi*(). Add new functions vm_suspend_all_cpus() and vm_resume_all_cpus() for use by the debug server. The underyling ioctl (which uses a vcpuid of -1) remains unchanged, but the userlevel API now uses separate functions for global CPU suspend/resume. Reviewed by: corvink, markj Differential Revision: https://reviews.freebsd.org/D38124
247 lines
5.5 KiB
C
247 lines
5.5 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2011 NetApp, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/types.h>
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#include <machine/cpufunc.h>
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#include <machine/vmm.h>
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#include <machine/specialreg.h>
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#include <vmmapi.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include "debug.h"
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#include "xmsr.h"
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static int cpu_vendor_intel, cpu_vendor_amd, cpu_vendor_hygon;
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int
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emulate_wrmsr(struct vcpu *vcpu __unused, uint32_t num, uint64_t val __unused)
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{
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if (cpu_vendor_intel) {
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switch (num) {
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case 0xd04: /* Sandy Bridge uncore PMCs */
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case 0xc24:
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return (0);
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case MSR_BIOS_UPDT_TRIG:
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return (0);
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case MSR_BIOS_SIGN:
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return (0);
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default:
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break;
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}
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} else if (cpu_vendor_amd || cpu_vendor_hygon) {
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switch (num) {
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case MSR_HWCR:
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/*
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* Ignore writes to hardware configuration MSR.
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*/
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return (0);
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case MSR_NB_CFG1:
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case MSR_LS_CFG:
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case MSR_IC_CFG:
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return (0); /* Ignore writes */
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case MSR_PERFEVSEL0:
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case MSR_PERFEVSEL1:
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case MSR_PERFEVSEL2:
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case MSR_PERFEVSEL3:
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/* Ignore writes to the PerfEvtSel MSRs */
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return (0);
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case MSR_K7_PERFCTR0:
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case MSR_K7_PERFCTR1:
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case MSR_K7_PERFCTR2:
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case MSR_K7_PERFCTR3:
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/* Ignore writes to the PerfCtr MSRs */
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return (0);
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case MSR_P_STATE_CONTROL:
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/* Ignore write to change the P-state */
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return (0);
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default:
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break;
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}
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}
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return (-1);
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}
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int
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emulate_rdmsr(struct vcpu *vcpu __unused, uint32_t num, uint64_t *val)
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{
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int error = 0;
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if (cpu_vendor_intel) {
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switch (num) {
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case MSR_BIOS_SIGN:
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case MSR_IA32_PLATFORM_ID:
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case MSR_PKG_ENERGY_STATUS:
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case MSR_PP0_ENERGY_STATUS:
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case MSR_PP1_ENERGY_STATUS:
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case MSR_DRAM_ENERGY_STATUS:
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case MSR_MISC_FEATURE_ENABLES:
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*val = 0;
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break;
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case MSR_RAPL_POWER_UNIT:
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/*
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* Use the default value documented in section
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* "RAPL Interfaces" in Intel SDM vol3.
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*/
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*val = 0x000a1003;
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break;
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case MSR_IA32_FEATURE_CONTROL:
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/*
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* Windows guests check this MSR.
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* Set the lock bit to avoid writes
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* to this MSR.
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*/
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*val = IA32_FEATURE_CONTROL_LOCK;
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break;
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default:
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error = -1;
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break;
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}
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} else if (cpu_vendor_amd || cpu_vendor_hygon) {
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switch (num) {
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case MSR_BIOS_SIGN:
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*val = 0;
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break;
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case MSR_HWCR:
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/*
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* Bios and Kernel Developer's Guides for AMD Families
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* 12H, 14H, 15H and 16H.
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*/
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*val = 0x01000010; /* Reset value */
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*val |= 1 << 9; /* MONITOR/MWAIT disable */
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break;
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case MSR_NB_CFG1:
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case MSR_LS_CFG:
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case MSR_IC_CFG:
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/*
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* The reset value is processor family dependent so
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* just return 0.
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*/
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*val = 0;
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break;
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case MSR_PERFEVSEL0:
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case MSR_PERFEVSEL1:
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case MSR_PERFEVSEL2:
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case MSR_PERFEVSEL3:
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/*
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* PerfEvtSel MSRs are not properly virtualized so just
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* return zero.
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*/
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*val = 0;
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break;
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case MSR_K7_PERFCTR0:
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case MSR_K7_PERFCTR1:
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case MSR_K7_PERFCTR2:
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case MSR_K7_PERFCTR3:
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/*
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* PerfCtr MSRs are not properly virtualized so just
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* return zero.
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*/
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*val = 0;
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break;
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case MSR_SMM_ADDR:
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case MSR_SMM_MASK:
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/*
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* Return the reset value defined in the AMD Bios and
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* Kernel Developer's Guide.
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*/
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*val = 0;
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break;
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case MSR_P_STATE_LIMIT:
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case MSR_P_STATE_CONTROL:
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case MSR_P_STATE_STATUS:
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case MSR_P_STATE_CONFIG(0): /* P0 configuration */
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*val = 0;
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break;
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/*
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* OpenBSD guests test bit 0 of this MSR to detect if the
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* workaround for erratum 721 is already applied.
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* https://support.amd.com/TechDocs/41322_10h_Rev_Gd.pdf
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*/
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case 0xC0011029:
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*val = 1;
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break;
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default:
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error = -1;
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break;
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}
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} else {
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error = -1;
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}
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return (error);
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}
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int
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init_msr(void)
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{
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int error;
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u_int regs[4];
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char cpu_vendor[13];
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do_cpuid(0, regs);
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((u_int *)&cpu_vendor)[0] = regs[1];
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((u_int *)&cpu_vendor)[1] = regs[3];
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((u_int *)&cpu_vendor)[2] = regs[2];
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cpu_vendor[12] = '\0';
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error = 0;
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if (strcmp(cpu_vendor, "AuthenticAMD") == 0) {
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cpu_vendor_amd = 1;
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} else if (strcmp(cpu_vendor, "HygonGenuine") == 0) {
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cpu_vendor_hygon = 1;
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} else if (strcmp(cpu_vendor, "GenuineIntel") == 0) {
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cpu_vendor_intel = 1;
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} else {
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EPRINTLN("Unknown cpu vendor \"%s\"", cpu_vendor);
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error = -1;
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}
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return (error);
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}
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