6bd95d70db
on for a while: - fine grained TLB shootdown for SMP on i386 - ranged TLB shootdowns.. eg: specify a range of pages to shoot down with a single IPI, since the IPI is very expensive. Adjust some callers that used to trigger this inside tight loops to do a ranged shootdown at the end instead. - PG_G support for SMP on i386 (options ENABLE_PG_G) - defer PG_G activation till after we decide what we are going to do with PSE and the 4MB pages at the start of the kernel. This should solve some rumored strangeness about stale PG_G entries getting stuck underneath the 4MB pages. - add some instrumentation for the fine TLB shootdown - convert some asm instruction wrappers from functions to inlines. gcc seems to do a fair bit better with this. - [temporarily!] pessimize the tlb shootdown IPI handlers. I will fix this again shortly. This has been working fairly well for me for a while, but I have tweaked it again prior to commit since my last major testing round. The only outstanding problem that I know of is PG_G related, which is why there is an option for it (not on by default for SMP). I have seen a world speedups by a few percent (as much as 4 or 5% in one case) but I have *not* accurately measured this - I am a bit sceptical of these numbers.
181 lines
4.0 KiB
C
181 lines
4.0 KiB
C
/*
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* Copyright (c) 1996, by Steve Passe
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. The name of the developer may NOT be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _MACHINE_SMPTESTS_H_
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#define _MACHINE_SMPTESTS_H_
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/*
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* Various 'tests in progress' and configuration parameters.
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*/
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/*
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* Control the "giant lock" pushdown by logical steps.
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*/
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#define PUSHDOWN_LEVEL_1
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#define PUSHDOWN_LEVEL_2
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/*
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* Put FAST_INTR() ISRs at an APIC priority above the regular INTs.
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* Allow the mp_lock() routines to handle FAST interrupts while spinning.
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*/
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#ifdef PUSHDOWN_LEVEL_1
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#define FAST_HI
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#endif
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/*
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* These defines enable critical region locking of areas that were
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* protected via cli/sti in the UP kernel.
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*
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* COMLOCK protects the sio/cy drivers.
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* known to be incomplete:
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* joystick lkm
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* ?
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*/
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#ifdef PUSHDOWN_LEVEL_1
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#define USE_COMLOCK
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#endif
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/*
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* Portions of the old TEST_LOPRIO code, back from the grave!
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*/
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#define GRAB_LOPRIO
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/*
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* Send CPUSTOP IPI for stop/restart of other CPUs on DDB break.
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#define VERBOSE_CPUSTOP_ON_DDBBREAK
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*/
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#define CPUSTOP_ON_DDBBREAK
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/*
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* Bracket code/comments relevant to the current 'giant lock' model.
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* Everything is now the 'giant lock' model, but we will use this as
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* we start to "push down" the lock.
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*/
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#define GIANT_LOCK
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#ifdef APIC_IO
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/*
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* Don't assume that slow interrupt handler X is called from vector
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* X + ICU_OFFSET.
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*/
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#define APIC_INTR_REORDER
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#endif /* APIC_IO */
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/*
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* Misc. counters.
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*
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#define COUNT_XINVLTLB_HITS
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*/
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/**
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* Hack to "fake-out" kernel into thinking it is running on a 'default config'.
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*
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* value == default type
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#define TEST_DEFAULT_CONFIG 6
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*/
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/*
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* Simple test code for IPI interaction, save for future...
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*
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#define TEST_TEST1
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#define IPI_TARGET_TEST1 1
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*/
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/*
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* Address of POST hardware port.
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* Defining this enables POSTCODE macros.
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*
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#define POST_ADDR 0x80
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*/
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/*
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* POST hardware macros.
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*/
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#ifdef POST_ADDR
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#define ASMPOSTCODE_INC \
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pushl %eax ; \
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movl _current_postcode, %eax ; \
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incl %eax ; \
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andl $0xff, %eax ; \
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movl %eax, _current_postcode ; \
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outb %al, $POST_ADDR ; \
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popl %eax
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/*
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* Overwrite the current_postcode value.
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*/
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#define ASMPOSTCODE(X) \
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pushl %eax ; \
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movl $X, %eax ; \
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movl %eax, _current_postcode ; \
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outb %al, $POST_ADDR ; \
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popl %eax
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/*
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* Overwrite the current_postcode low nibble.
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*/
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#define ASMPOSTCODE_LO(X) \
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pushl %eax ; \
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movl _current_postcode, %eax ; \
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andl $0xf0, %eax ; \
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orl $X, %eax ; \
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movl %eax, _current_postcode ; \
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outb %al, $POST_ADDR ; \
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popl %eax
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/*
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* Overwrite the current_postcode high nibble.
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*/
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#define ASMPOSTCODE_HI(X) \
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pushl %eax ; \
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movl _current_postcode, %eax ; \
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andl $0x0f, %eax ; \
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orl $(X<<4), %eax ; \
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movl %eax, _current_postcode ; \
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outb %al, $POST_ADDR ; \
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popl %eax
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#else
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#define ASMPOSTCODE_INC
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#define ASMPOSTCODE(X)
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#define ASMPOSTCODE_LO(X)
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#define ASMPOSTCODE_HI(X)
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#endif /* POST_ADDR */
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#endif /* _MACHINE_SMPTESTS_H_ */
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