fa790ea99f
David Somayajulu (davidcs): Overall RDMA Driver infrastructure and iWARP Anand Khoje (akhoje@marvell.com): RoCEv1 verbs implementation MFC after:5 days
113 lines
3.3 KiB
C
113 lines
3.3 KiB
C
/*
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* Copyright (c) 2018-2019 Cavium, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef __QLNXR_CM_H__
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#define __QLNXR_CM_H__
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/* ECORE LL2 has a limit to the number of buffers it can handle.
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* FYI, OFED used 512 and 128 for recv and send.
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*/
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#define QLNXR_GSI_MAX_RECV_WR (4096)
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#define QLNXR_GSI_MAX_SEND_WR (4096)
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#define QLNXR_GSI_MAX_RECV_SGE (1) /* LL2 FW limitation */
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/* future OFED/kernel will have these */
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#define ETH_P_ROCE (0x8915)
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#define QLNXR_ROCE_V2_UDP_SPORT (0000)
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#if __FreeBSD_version >= 1102000
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#define rdma_wr(_wr) rdma_wr(_wr)
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#define ud_wr(_wr) ud_wr(_wr)
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#define atomic_wr(_wr) atomic_wr(_wr)
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#else
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#define rdma_wr(_wr) (&(_wr->wr.rdma))
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#define ud_wr(_wr) (&(_wr->wr.ud))
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#define atomic_wr(_wr) (&(_wr->wr.atomic))
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#endif /* #if __FreeBSD_version >= 1102000 */
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static inline u32 qlnxr_get_ipv4_from_gid(u8 *gid)
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{
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return *(u32 *)(void *)&gid[12];
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}
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struct ecore_roce_ll2_header {
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void *vaddr;
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dma_addr_t baddr;
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size_t len;
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};
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struct ecore_roce_ll2_buffer {
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dma_addr_t baddr;
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size_t len;
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};
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struct ecore_roce_ll2_packet {
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struct ecore_roce_ll2_header header;
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int n_seg;
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struct ecore_roce_ll2_buffer payload[RDMA_MAX_SGE_PER_SQ_WQE];
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int roce_mode;
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enum ecore_roce_ll2_tx_dest tx_dest;
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};
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/* RDMA CM */
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extern int qlnxr_gsi_poll_cq(struct ib_cq *ibcq,
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int num_entries,
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struct ib_wc *wc);
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extern int qlnxr_gsi_post_recv(struct ib_qp *ibqp,
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struct ib_recv_wr *wr,
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struct ib_recv_wr **bad_wr);
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extern int qlnxr_gsi_post_send(struct ib_qp *ibqp,
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struct ib_send_wr *wr,
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struct ib_send_wr **bad_wr);
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extern struct ib_qp* qlnxr_create_gsi_qp(struct qlnxr_dev *dev,
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struct ib_qp_init_attr *attrs,
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struct qlnxr_qp *qp);
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extern void qlnxr_store_gsi_qp_cq(struct qlnxr_dev *dev,
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struct qlnxr_qp *qp,
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struct ib_qp_init_attr *attrs);
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extern void qlnxr_inc_sw_gsi_cons(struct qlnxr_qp_hwq_info *info);
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extern int qlnxr_destroy_gsi_qp(struct qlnxr_dev *dev);
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#endif /* #ifndef __QLNXR_CM_H__ */
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