387 lines
12 KiB
C
387 lines
12 KiB
C
/******************************************************************************
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* os.h
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*
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* random collection of macros and definition
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*/
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#ifndef _XEN_OS_H_
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#define _XEN_OS_H_
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#include <machine/param.h>
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#ifdef PAE
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#define CONFIG_X86_PAE
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#endif
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#if defined(XEN) && !defined(__XEN_INTERFACE_VERSION__)
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/*
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* Can update to a more recent version when we implement
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* the hypercall page
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*/
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#define __XEN_INTERFACE_VERSION__ 0x00030204
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#endif
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#include <xen/interface/xen.h>
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/* Force a proper event-channel callback from Xen. */
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void force_evtchn_callback(void);
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#define likely(x) __builtin_expect((x),1)
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#define unlikely(x) __builtin_expect((x),0)
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#ifndef vtophys
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#include <vm/vm.h>
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#include <vm/vm_param.h>
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#include <vm/pmap.h>
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#endif
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#ifdef SMP
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#include <sys/time.h> /* XXX for pcpu.h */
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#include <sys/pcpu.h> /* XXX for PCPU_GET */
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extern int gdtset;
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static inline int
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smp_processor_id(void)
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{
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if (likely(gdtset))
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return PCPU_GET(cpuid);
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return 0;
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}
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#else
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#define smp_processor_id() 0
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#endif
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#ifndef NULL
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#define NULL (void *)0
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#endif
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#ifndef PANIC_IF
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#define PANIC_IF(exp) if (unlikely(exp)) {printk("panic - %s: %s:%d\n",#exp, __FILE__, __LINE__); panic("%s: %s:%d", #exp, __FILE__, __LINE__);}
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#endif
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extern shared_info_t *HYPERVISOR_shared_info;
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/* Somewhere in the middle of the GCC 2.96 development cycle, we implemented
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a mechanism by which the user can annotate likely branch directions and
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expect the blocks to be reordered appropriately. Define __builtin_expect
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to nothing for earlier compilers. */
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/* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
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static inline void rep_nop(void)
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{
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__asm__ __volatile__ ( "rep;nop" : : : "memory" );
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}
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#define cpu_relax() rep_nop()
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#if __GNUC__ == 2 && __GNUC_MINOR__ < 96
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#define __builtin_expect(x, expected_value) (x)
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#endif
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#define DEFINE_PER_CPU(type, name) \
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__typeof__(type) per_cpu__##name
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#define per_cpu(var, cpu) (*((void)cpu, &per_cpu__##var))
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/* crude memory allocator for memory allocation early in
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* boot
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*/
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void *bootmem_alloc(unsigned int size);
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void bootmem_free(void *ptr, unsigned int size);
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/* Everything below this point is not included by assembler (.S) files. */
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#ifndef __ASSEMBLY__
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#include <sys/types.h>
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void printk(const char *fmt, ...);
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/* some function prototypes */
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void trap_init(void);
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extern int preemptable;
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#define preempt_disable() (preemptable = 0)
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#define preempt_enable() (preemptable = 1)
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#define preempt_enable_no_resched() (preemptable = 1)
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/*
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* STI/CLI equivalents. These basically set and clear the virtual
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* event_enable flag in teh shared_info structure. Note that when
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* the enable bit is set, there may be pending events to be handled.
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* We may therefore call into do_hypervisor_callback() directly.
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*/
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#define __cli() \
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do { \
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vcpu_info_t *_vcpu; \
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preempt_disable(); \
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_vcpu = &HYPERVISOR_shared_info->vcpu_info[smp_processor_id()]; \
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_vcpu->evtchn_upcall_mask = 1; \
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preempt_enable_no_resched(); \
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barrier(); \
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} while (0)
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#define __sti() \
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do { \
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vcpu_info_t *_vcpu; \
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barrier(); \
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preempt_disable(); \
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_vcpu = &HYPERVISOR_shared_info->vcpu_info[smp_processor_id()]; \
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_vcpu->evtchn_upcall_mask = 0; \
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barrier(); /* unmask then check (avoid races) */ \
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if ( unlikely(_vcpu->evtchn_upcall_pending) ) \
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force_evtchn_callback(); \
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preempt_enable(); \
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} while (0)
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#define __save_flags(x) \
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do { \
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vcpu_info_t *vcpu; \
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vcpu = HYPERVISOR_shared_info->vcpu_info[smp_processor_id()]; \
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(x) = _vcpu->evtchn_upcall_mask; \
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} while (0)
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#define __restore_flags(x) \
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do { \
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vcpu_info_t *_vcpu; \
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barrier(); \
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preempt_disable(); \
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_vcpu = &HYPERVISOR_shared_info->vcpu_info[smp_processor_id()]; \
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if ((_vcpu->evtchn_upcall_mask = (x)) == 0) { \
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barrier(); /* unmask then check (avoid races) */ \
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if ( unlikely(_vcpu->evtchn_upcall_pending) ) \
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force_evtchn_callback(); \
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preempt_enable(); \
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} else \
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preempt_enable_no_resched(); \
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} while (0)
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/*
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* Add critical_{enter, exit}?
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*
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*/
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#define __save_and_cli(x) \
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do { \
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vcpu_info_t *_vcpu; \
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_vcpu = &HYPERVISOR_shared_info->vcpu_info[smp_processor_id()]; \
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(x) = _vcpu->evtchn_upcall_mask; \
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_vcpu->evtchn_upcall_mask = 1; \
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barrier(); \
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} while (0)
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#define cli() __cli()
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#define sti() __sti()
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#define save_flags(x) __save_flags(x)
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#define restore_flags(x) __restore_flags(x)
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#define save_and_cli(x) __save_and_cli(x)
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#define local_irq_save(x) __save_and_cli(x)
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#define local_irq_restore(x) __restore_flags(x)
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#define local_irq_disable() __cli()
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#define local_irq_enable() __sti()
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#define mtx_lock_irqsave(lock, x) {local_irq_save((x)); mtx_lock_spin((lock));}
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#define mtx_unlock_irqrestore(lock, x) {mtx_unlock_spin((lock)); local_irq_restore((x)); }
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#define spin_lock_irqsave mtx_lock_irqsave
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#define spin_unlock_irqrestore mtx_unlock_irqrestore
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#ifndef mb
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#define mb() __asm__ __volatile__("lock; addl $0, 0(%%esp)": : :"memory")
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#endif
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#ifndef rmb
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#define rmb() mb()
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#endif
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#ifndef wmb
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#define wmb() barrier()
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#endif
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#ifdef SMP
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#define smp_mb() mb()
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#define smp_rmb() rmb()
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#define smp_wmb() wmb()
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#define smp_read_barrier_depends() read_barrier_depends()
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#define set_mb(var, value) do { xchg(&var, value); } while (0)
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#else
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#define smp_mb() barrier()
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#define smp_rmb() barrier()
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#define smp_wmb() barrier()
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#define smp_read_barrier_depends() do { } while(0)
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#define set_mb(var, value) do { var = value; barrier(); } while (0)
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#endif
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/* This is a barrier for the compiler only, NOT the processor! */
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#define barrier() __asm__ __volatile__("": : :"memory")
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#define LOCK_PREFIX ""
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#define LOCK ""
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#define ADDR (*(volatile long *) addr)
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/*
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* Make sure gcc doesn't try to be clever and move things around
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* on us. We need to use _exactly_ the address the user gave us,
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* not some alias that contains the same information.
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*/
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typedef struct { volatile int counter; } atomic_t;
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#define xen_xchg(ptr,v) \
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((__typeof__(*(ptr)))__xchg((unsigned long)(v),(ptr),sizeof(*(ptr))))
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struct __xchg_dummy { unsigned long a[100]; };
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#define __xg(x) ((volatile struct __xchg_dummy *)(x))
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static __inline unsigned long __xchg(unsigned long x, volatile void * ptr,
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int size)
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{
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switch (size) {
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case 1:
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__asm__ __volatile__("xchgb %b0,%1"
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:"=q" (x)
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:"m" (*__xg(ptr)), "0" (x)
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:"memory");
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break;
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case 2:
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__asm__ __volatile__("xchgw %w0,%1"
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:"=r" (x)
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:"m" (*__xg(ptr)), "0" (x)
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:"memory");
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break;
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case 4:
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__asm__ __volatile__("xchgl %0,%1"
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:"=r" (x)
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:"m" (*__xg(ptr)), "0" (x)
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:"memory");
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break;
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}
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return x;
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}
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/**
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* test_and_clear_bit - Clear a bit and return its old value
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* @nr: Bit to set
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* @addr: Address to count from
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*
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* This operation is atomic and cannot be reordered.
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* It also implies a memory barrier.
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*/
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static __inline int test_and_clear_bit(int nr, volatile void * addr)
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{
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int oldbit;
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__asm__ __volatile__( LOCK_PREFIX
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"btrl %2,%1\n\tsbbl %0,%0"
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:"=r" (oldbit),"=m" (ADDR)
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:"Ir" (nr) : "memory");
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return oldbit;
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}
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static __inline int constant_test_bit(int nr, const volatile void * addr)
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{
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return ((1UL << (nr & 31)) & (((const volatile unsigned int *) addr)[nr >> 5])) != 0;
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}
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static __inline int variable_test_bit(int nr, volatile void * addr)
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{
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int oldbit;
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__asm__ __volatile__(
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"btl %2,%1\n\tsbbl %0,%0"
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:"=r" (oldbit)
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:"m" (ADDR),"Ir" (nr));
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return oldbit;
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}
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#define test_bit(nr,addr) \
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(__builtin_constant_p(nr) ? \
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constant_test_bit((nr),(addr)) : \
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variable_test_bit((nr),(addr)))
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/**
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* set_bit - Atomically set a bit in memory
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* @nr: the bit to set
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* @addr: the address to start counting from
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*
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* This function is atomic and may not be reordered. See __set_bit()
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* if you do not require the atomic guarantees.
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* Note that @nr may be almost arbitrarily large; this function is not
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* restricted to acting on a single-word quantity.
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*/
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static __inline__ void set_bit(int nr, volatile void * addr)
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{
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__asm__ __volatile__( LOCK_PREFIX
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"btsl %1,%0"
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:"=m" (ADDR)
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:"Ir" (nr));
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}
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/**
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* clear_bit - Clears a bit in memory
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* @nr: Bit to clear
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* @addr: Address to start counting from
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*
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* clear_bit() is atomic and may not be reordered. However, it does
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* not contain a memory barrier, so if it is used for locking purposes,
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* you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit()
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* in order to ensure changes are visible on other processors.
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*/
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static __inline__ void clear_bit(int nr, volatile void * addr)
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{
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__asm__ __volatile__( LOCK_PREFIX
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"btrl %1,%0"
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:"=m" (ADDR)
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:"Ir" (nr));
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}
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/**
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* atomic_inc - increment atomic variable
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* @v: pointer of type atomic_t
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*
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* Atomically increments @v by 1. Note that the guaranteed
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* useful range of an atomic_t is only 24 bits.
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*/
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static __inline__ void atomic_inc(atomic_t *v)
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{
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__asm__ __volatile__(
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LOCK "incl %0"
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:"=m" (v->counter)
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:"m" (v->counter));
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}
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#define rdtscll(val) \
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__asm__ __volatile__("rdtsc" : "=A" (val))
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/*
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* Kernel pointers have redundant information, so we can use a
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* scheme where we can return either an error code or a dentry
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* pointer with the same return value.
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*
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* This should be a per-architecture thing, to allow different
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* error and pointer decisions.
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*/
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#define IS_ERR_VALUE(x) unlikely((x) > (unsigned long)-1000L)
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static inline void *ERR_PTR(long error)
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{
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return (void *) error;
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}
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static inline long PTR_ERR(const void *ptr)
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{
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return (long) ptr;
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}
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static inline long IS_ERR(const void *ptr)
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{
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return IS_ERR_VALUE((unsigned long)ptr);
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}
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#endif /* !__ASSEMBLY__ */
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#endif /* _OS_H_ */
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