e64428edf7
P1022 SATA controller may set the wrong CCR bit for a command completion. This would previously cause an interrupt storm. Solve this by marking all commands complete, and letting the end_transaction deal with the successes. Causes no problems on P5020. While here, fix a minor bug in collision detection. The Freescale SATA controller only has 16 slots, not 32. |
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atpic.c | ||
ds1553_bus_fdt.c | ||
ds1553_core.c | ||
ds1553_reg.h | ||
fsl_diu.c | ||
fsl_espi.c | ||
fsl_sata.c | ||
fsl_sata.h | ||
i2c.c | ||
isa.c | ||
lbc.c | ||
lbc.h | ||
mpc85xx_cache.c | ||
mpc85xx_gpio.c | ||
mpc85xx.c | ||
mpc85xx.h | ||
pci_mpc85xx_pcib.c | ||
pci_mpc85xx.c | ||
platform_mpc85xx.c | ||
qoriq_gpio.c |