637f34cb64
Newer Book-E cores (e500mc, e5500, e6500) do not support the WE bit in the MSR, and instead delegate CPU idling to the SoC. Perhaps in the future the QORIQ_DPAA option for the mpc85xx platform will become a subclass, which will eliminate most of the #ifdef's.
518 lines
12 KiB
C
518 lines
12 KiB
C
/*-
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* Copyright (c) 2008-2012 Semihalf.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "opt_platform.h"
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/bus.h>
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#include <sys/pcpu.h>
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#include <sys/proc.h>
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#include <sys/smp.h>
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#include <machine/bus.h>
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#include <machine/cpu.h>
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#include <machine/hid.h>
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#include <machine/machdep.h>
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#include <machine/platform.h>
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#include <machine/platformvar.h>
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#include <machine/smp.h>
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#include <machine/spr.h>
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#include <machine/vmparam.h>
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#include <dev/fdt/fdt_common.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <dev/ofw/openfirm.h>
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#include <vm/vm.h>
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#include <vm/pmap.h>
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#include <powerpc/mpc85xx/mpc85xx.h>
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#include "platform_if.h"
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#ifdef SMP
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extern void *ap_pcpu;
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extern vm_paddr_t kernload; /* Kernel physical load address */
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extern uint8_t __boot_page[]; /* Boot page body */
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extern uint32_t bp_ntlb1s;
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extern uint32_t bp_tlb1[];
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extern uint32_t bp_tlb1_end[];
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#endif
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extern uint32_t *bootinfo;
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vm_offset_t ccsrbar_va;
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static int cpu, maxcpu;
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static int mpc85xx_probe(platform_t);
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static void mpc85xx_mem_regions(platform_t, struct mem_region *phys,
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int *physsz, struct mem_region *avail, int *availsz);
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static u_long mpc85xx_timebase_freq(platform_t, struct cpuref *cpuref);
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static int mpc85xx_smp_first_cpu(platform_t, struct cpuref *cpuref);
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static int mpc85xx_smp_next_cpu(platform_t, struct cpuref *cpuref);
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static int mpc85xx_smp_get_bsp(platform_t, struct cpuref *cpuref);
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static int mpc85xx_smp_start_cpu(platform_t, struct pcpu *cpu);
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static void mpc85xx_idle(platform_t, int cpu);
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static int mpc85xx_idle_wakeup(platform_t plat, int cpu);
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static void mpc85xx_reset(platform_t);
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static platform_method_t mpc85xx_methods[] = {
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PLATFORMMETHOD(platform_probe, mpc85xx_probe),
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PLATFORMMETHOD(platform_attach, mpc85xx_attach),
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PLATFORMMETHOD(platform_mem_regions, mpc85xx_mem_regions),
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PLATFORMMETHOD(platform_timebase_freq, mpc85xx_timebase_freq),
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PLATFORMMETHOD(platform_smp_first_cpu, mpc85xx_smp_first_cpu),
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PLATFORMMETHOD(platform_smp_next_cpu, mpc85xx_smp_next_cpu),
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PLATFORMMETHOD(platform_smp_get_bsp, mpc85xx_smp_get_bsp),
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PLATFORMMETHOD(platform_smp_start_cpu, mpc85xx_smp_start_cpu),
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PLATFORMMETHOD(platform_reset, mpc85xx_reset),
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PLATFORMMETHOD(platform_idle, mpc85xx_idle),
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PLATFORMMETHOD(platform_idle_wakeup, mpc85xx_idle_wakeup),
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PLATFORMMETHOD_END
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};
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DEFINE_CLASS_0(mpc85xx, mpc85xx_platform, mpc85xx_methods, 0);
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PLATFORM_DEF(mpc85xx_platform);
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static int
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mpc85xx_probe(platform_t plat)
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{
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u_int pvr = mfpvr() >> 16;
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if ((pvr & 0xfff0) == FSL_E500v1)
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return (BUS_PROBE_DEFAULT);
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return (ENXIO);
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}
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int
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mpc85xx_attach(platform_t plat)
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{
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phandle_t cpus, child, ccsr;
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const char *soc_name_guesses[] = {"/soc", "soc", NULL};
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const char **name;
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pcell_t ranges[6], acells, pacells, scells;
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uint32_t sr;
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uint64_t ccsrbar, ccsrsize;
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int i, law_max, tgt;
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if ((cpus = OF_finddevice("/cpus")) != -1) {
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for (maxcpu = 0, child = OF_child(cpus); child != 0;
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child = OF_peer(child), maxcpu++)
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;
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} else
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maxcpu = 1;
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/*
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* Locate CCSR region. Irritatingly, there is no way to find it
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* unless you already know where it is. Try to infer its location
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* from the device tree.
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*/
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ccsr = -1;
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for (name = soc_name_guesses; *name != NULL && ccsr == -1; name++)
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ccsr = OF_finddevice(*name);
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if (ccsr == -1) {
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char type[64];
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/* That didn't work. Search for devices of type "soc" */
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child = OF_child(OF_peer(0));
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for (OF_child(child); child != 0; child = OF_peer(child)) {
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if (OF_getprop(child, "device_type", type, sizeof(type))
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<= 0)
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continue;
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if (strcmp(type, "soc") == 0) {
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ccsr = child;
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break;
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}
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}
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}
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if (ccsr == -1)
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panic("Could not locate CCSR window!");
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OF_getprop(ccsr, "#size-cells", &scells, sizeof(scells));
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OF_getprop(ccsr, "#address-cells", &acells, sizeof(acells));
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OF_searchprop(OF_parent(ccsr), "#address-cells", &pacells,
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sizeof(pacells));
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OF_getprop(ccsr, "ranges", ranges, sizeof(ranges));
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ccsrbar = ccsrsize = 0;
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for (i = acells; i < acells + pacells; i++) {
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ccsrbar <<= 32;
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ccsrbar |= ranges[i];
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}
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for (i = acells + pacells; i < acells + pacells + scells; i++) {
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ccsrsize <<= 32;
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ccsrsize |= ranges[i];
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}
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ccsrbar_va = pmap_early_io_map(ccsrbar, ccsrsize);
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mpc85xx_fix_errata(ccsrbar_va);
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mpc85xx_enable_l3_cache();
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/*
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* Clear local access windows. Skip DRAM entries, so we don't shoot
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* ourselves in the foot.
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*/
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law_max = law_getmax();
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for (i = 0; i < law_max; i++) {
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sr = ccsr_read4(OCP85XX_LAWSR(i));
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if ((sr & OCP85XX_ENA_MASK) == 0)
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continue;
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tgt = (sr & 0x01f00000) >> 20;
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if (tgt == OCP85XX_TGTIF_RAM1 || tgt == OCP85XX_TGTIF_RAM2 ||
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tgt == OCP85XX_TGTIF_RAM_INTL)
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continue;
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ccsr_write4(OCP85XX_LAWSR(i), sr & OCP85XX_DIS_MASK);
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}
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return (0);
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}
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void
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mpc85xx_mem_regions(platform_t plat, struct mem_region *phys, int *physsz,
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struct mem_region *avail, int *availsz)
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{
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ofw_mem_regions(phys, physsz, avail, availsz);
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}
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static u_long
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mpc85xx_timebase_freq(platform_t plat, struct cpuref *cpuref)
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{
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u_long ticks;
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phandle_t cpus, child;
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pcell_t freq;
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if (bootinfo != NULL) {
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if (bootinfo[0] == 1) {
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/* Backward compatibility. See 8-STABLE. */
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ticks = bootinfo[3] >> 3;
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} else {
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/* Compatibility with Juniper's loader. */
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ticks = bootinfo[5] >> 3;
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}
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} else
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ticks = 0;
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if ((cpus = OF_finddevice("/cpus")) == -1)
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goto out;
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if ((child = OF_child(cpus)) == 0)
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goto out;
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switch (OF_getproplen(child, "timebase-frequency")) {
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case 4:
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{
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uint32_t tbase;
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OF_getprop(child, "timebase-frequency", &tbase, sizeof(tbase));
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ticks = tbase;
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return (ticks);
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}
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case 8:
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{
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uint64_t tbase;
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OF_getprop(child, "timebase-frequency", &tbase, sizeof(tbase));
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ticks = tbase;
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return (ticks);
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}
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default:
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break;
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}
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freq = 0;
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if (OF_getprop(child, "bus-frequency", (void *)&freq,
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sizeof(freq)) <= 0)
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goto out;
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/*
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* Time Base and Decrementer are updated every 8 CCB bus clocks.
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* HID0[SEL_TBCLK] = 0
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*/
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if (freq != 0)
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#ifdef QORIQ_DPAA
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ticks = freq / 32;
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#else
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ticks = freq / 8;
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#endif
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out:
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if (ticks <= 0)
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panic("Unable to determine timebase frequency!");
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return (ticks);
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}
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static int
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mpc85xx_smp_first_cpu(platform_t plat, struct cpuref *cpuref)
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{
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cpu = 0;
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cpuref->cr_cpuid = cpu;
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cpuref->cr_hwref = cpuref->cr_cpuid;
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if (bootverbose)
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printf("powerpc_smp_first_cpu: cpuid %d\n", cpuref->cr_cpuid);
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cpu++;
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return (0);
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}
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static int
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mpc85xx_smp_next_cpu(platform_t plat, struct cpuref *cpuref)
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{
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if (cpu >= maxcpu)
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return (ENOENT);
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cpuref->cr_cpuid = cpu++;
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cpuref->cr_hwref = cpuref->cr_cpuid;
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if (bootverbose)
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printf("powerpc_smp_next_cpu: cpuid %d\n", cpuref->cr_cpuid);
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return (0);
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}
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static int
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mpc85xx_smp_get_bsp(platform_t plat, struct cpuref *cpuref)
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{
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cpuref->cr_cpuid = mfspr(SPR_PIR);
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cpuref->cr_hwref = cpuref->cr_cpuid;
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return (0);
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}
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static int
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mpc85xx_smp_start_cpu(platform_t plat, struct pcpu *pc)
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{
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#ifdef SMP
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uint32_t *tlb1;
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vm_paddr_t bptr;
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uint32_t reg;
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int i, timeout;
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uintptr_t brr;
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int cpuid;
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#ifdef QORIQ_DPAA
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uint32_t tgt;
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reg = ccsr_read4(OCP85XX_COREDISR);
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cpuid = pc->pc_cpuid;
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if ((reg & cpuid) != 0) {
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printf("%s: CPU %d is disabled!\n", __func__, pc->pc_cpuid);
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return (-1);
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}
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brr = OCP85XX_BRR;
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#else /* QORIQ_DPAA */
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brr = OCP85XX_EEBPCR;
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cpuid = pc->pc_cpuid + 24;
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#endif
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reg = ccsr_read4(brr);
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if ((reg & (1 << cpuid)) != 0) {
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printf("SMP: CPU %d already out of hold-off state!\n",
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pc->pc_cpuid);
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return (ENXIO);
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}
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ap_pcpu = pc;
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__asm __volatile("msync; isync");
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i = 0;
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tlb1 = bp_tlb1;
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while (i < bp_ntlb1s && tlb1 < bp_tlb1_end) {
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mtspr(SPR_MAS0, MAS0_TLBSEL(1) | MAS0_ESEL(i));
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__asm __volatile("isync; tlbre");
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tlb1[0] = mfspr(SPR_MAS1);
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tlb1[1] = mfspr(SPR_MAS2);
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tlb1[2] = mfspr(SPR_MAS3);
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i++;
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tlb1 += 3;
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}
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if (i < bp_ntlb1s)
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bp_ntlb1s = i;
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/* Flush caches to have our changes hit DRAM. */
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cpu_flush_dcache(__boot_page, 4096);
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bptr = ((vm_paddr_t)(uintptr_t)__boot_page - KERNBASE) + kernload;
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KASSERT((bptr & 0xfff) == 0,
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("%s: boot page is not aligned (%#jx)", __func__, (uintmax_t)bptr));
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#ifdef QORIQ_DPAA
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/*
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* Read DDR controller configuration to select proper BPTR target ID.
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*
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* On P5020 bit 29 of DDR1_CS0_CONFIG enables DDR controllers
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* interleaving. If this bit is set, we have to use
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* OCP85XX_TGTIF_RAM_INTL as BPTR target ID. On other QorIQ DPAA SoCs,
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* this bit is reserved and always 0.
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*/
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reg = ccsr_read4(OCP85XX_DDR1_CS0_CONFIG);
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if (reg & (1 << 29))
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tgt = OCP85XX_TGTIF_RAM_INTL;
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else
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tgt = OCP85XX_TGTIF_RAM1;
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/*
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* Set BSTR to the physical address of the boot page
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*/
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ccsr_write4(OCP85XX_BSTRH, bptr >> 32);
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ccsr_write4(OCP85XX_BSTRL, bptr);
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ccsr_write4(OCP85XX_BSTAR, OCP85XX_ENA_MASK |
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(tgt << OCP85XX_TRGT_SHIFT) | (ffsl(PAGE_SIZE) - 2));
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/* Read back OCP85XX_BSTAR to synchronize write */
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ccsr_read4(OCP85XX_BSTAR);
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/*
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* Enable and configure time base on new CPU.
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*/
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/* Set TB clock source to platform clock / 32 */
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reg = ccsr_read4(CCSR_CTBCKSELR);
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ccsr_write4(CCSR_CTBCKSELR, reg & ~(1 << pc->pc_cpuid));
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/* Enable TB */
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reg = ccsr_read4(CCSR_CTBENR);
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ccsr_write4(CCSR_CTBENR, reg | (1 << pc->pc_cpuid));
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#else
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/*
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* Set BPTR to the physical address of the boot page
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*/
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bptr = (bptr >> 12) | 0x80000000u;
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ccsr_write4(OCP85XX_BPTR, bptr);
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__asm __volatile("isync; msync");
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#endif /* QORIQ_DPAA */
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/*
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* Release AP from hold-off state
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*/
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reg = ccsr_read4(brr);
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ccsr_write4(brr, reg | (1 << cpuid));
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__asm __volatile("isync; msync");
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timeout = 500;
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while (!pc->pc_awake && timeout--)
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DELAY(1000); /* wait 1ms */
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/*
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* Disable boot page translation so that the 4K page at the default
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* address (= 0xfffff000) isn't permanently remapped and thus not
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* usable otherwise.
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*/
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#ifdef QORIQ_DPAA
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ccsr_write4(OCP85XX_BSTAR, 0);
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#else
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ccsr_write4(OCP85XX_BPTR, 0);
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#endif
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__asm __volatile("isync; msync");
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if (!pc->pc_awake)
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printf("SMP: CPU %d didn't wake up.\n", pc->pc_cpuid);
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return ((pc->pc_awake) ? 0 : EBUSY);
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#else
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/* No SMP support */
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return (ENXIO);
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#endif
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}
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static void
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mpc85xx_reset(platform_t plat)
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{
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/*
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* Try the dedicated reset register first.
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* If the SoC doesn't have one, we'll fall
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* back to using the debug control register.
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*/
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ccsr_write4(OCP85XX_RSTCR, 2);
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/* Clear DBCR0, disables debug interrupts and events. */
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mtspr(SPR_DBCR0, 0);
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__asm __volatile("isync");
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/* Enable Debug Interrupts in MSR. */
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mtmsr(mfmsr() | PSL_DE);
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/* Enable debug interrupts and issue reset. */
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mtspr(SPR_DBCR0, mfspr(SPR_DBCR0) | DBCR0_IDM | DBCR0_RST_SYSTEM);
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printf("Reset failed...\n");
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while (1)
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;
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}
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static void
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mpc85xx_idle(platform_t plat, int cpu)
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{
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#ifdef QORIQ_DPAA
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uint32_t reg;
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reg = ccsr_read4(OCP85XX_RCPM_CDOZCR);
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ccsr_write4(OCP85XX_RCPM_CDOZCR, reg | (1 << cpu));
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|
ccsr_read4(OCP85XX_RCPM_CDOZCR);
|
|
#else
|
|
register_t msr;
|
|
|
|
msr = mfmsr();
|
|
/* Freescale E500 core RM section 6.4.1. */
|
|
__asm __volatile("msync; mtmsr %0; isync" ::
|
|
"r" (msr | PSL_WE));
|
|
#endif
|
|
}
|
|
|
|
static int
|
|
mpc85xx_idle_wakeup(platform_t plat, int cpu)
|
|
{
|
|
#ifdef QORIQ_DPAA
|
|
uint32_t reg;
|
|
|
|
reg = ccsr_read4(OCP85XX_RCPM_CDOZCR);
|
|
ccsr_write4(OCP85XX_RCPM_CDOZCR, reg & ~(1 << cpu));
|
|
ccsr_read4(OCP85XX_RCPM_CDOZCR);
|
|
|
|
return (1);
|
|
#endif
|
|
return (0);
|
|
}
|