ad15dc0f1b
swi_exit code in exception.S instead of having its own inline expansion of the DO_AST and PULLFRAME macros. That means that now all references to the PUSH/PULLFRAME and DO_AST macros are localized to exception.S, so move the macros themselves into there and remove them from asmacros.h
498 lines
13 KiB
ArmAsm
498 lines
13 KiB
ArmAsm
/* $NetBSD: cpuswitch.S,v 1.41 2003/11/15 08:44:18 scw Exp $ */
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/*-
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* Copyright 2003 Wasabi Systems, Inc.
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* All rights reserved.
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*
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* Written by Steve C. Woodford for Wasabi Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for the NetBSD Project by
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* Wasabi Systems, Inc.
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* 4. The name of Wasabi Systems, Inc. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*-
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* Copyright (c) 1994-1998 Mark Brinicombe.
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* Copyright (c) 1994 Brini.
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* All rights reserved.
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*
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* This code is derived from software written for Brini by Mark Brinicombe
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Brini.
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* 4. The name of the company nor the name of the author may be used to
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* endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* RiscBSD kernel project
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*
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* cpuswitch.S
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*
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* cpu switching functions
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*
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* Created : 15/10/94
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*
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*/
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#include "assym.s"
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#include "opt_sched.h"
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#include <machine/asm.h>
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#include <machine/asmacros.h>
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#include <machine/armreg.h>
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#include <machine/vfp.h>
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__FBSDID("$FreeBSD$");
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#define DOMAIN_CLIENT 0x01
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#if defined(_ARM_ARCH_6) && defined(SMP)
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#define GET_PCPU(tmp, tmp2) \
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mrc p15, 0, tmp, c0, c0, 5; \
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and tmp, tmp, #0xf; \
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ldr tmp2, .Lcurpcpu+4; \
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mul tmp, tmp, tmp2; \
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ldr tmp2, .Lcurpcpu; \
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add tmp, tmp, tmp2;
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#else
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#define GET_PCPU(tmp, tmp2) \
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ldr tmp, .Lcurpcpu
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#endif
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#ifdef VFP
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.fpu vfp /* allow VFP instructions */
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#endif
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.Lcurpcpu:
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.word _C_LABEL(__pcpu)
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.word PCPU_SIZE
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.Lcpufuncs:
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.word _C_LABEL(cpufuncs)
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.Lblocked_lock:
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.word _C_LABEL(blocked_lock)
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ENTRY(cpu_throw)
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mov r5, r1
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/*
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* r0 = oldtd
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* r5 = newtd
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*/
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#ifdef VFP /* This thread is dying, disable */
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bl _C_LABEL(vfp_discard) /* VFP without preserving state. */
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#endif
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GET_PCPU(r7, r9)
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ldr r7, [r5, #(TD_PCB)] /* r7 = new thread's PCB */
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/* Switch to lwp0 context */
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ldr r9, .Lcpufuncs
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#if !defined(CPU_ARM11) && !defined(CPU_CORTEXA) && !defined(CPU_MV_PJ4B) && !defined(CPU_KRAIT)
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mov lr, pc
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ldr pc, [r9, #CF_IDCACHE_WBINV_ALL]
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#endif
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ldr r0, [r7, #(PCB_PL1VEC)]
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ldr r1, [r7, #(PCB_DACR)]
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/*
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* r0 = Pointer to L1 slot for vector_page (or NULL)
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* r1 = lwp0's DACR
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* r5 = lwp0
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* r6 = exit func
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* r7 = lwp0's PCB
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* r9 = cpufuncs
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*/
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/*
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* Ensure the vector table is accessible by fixing up lwp0's L1
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*/
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cmp r0, #0 /* No need to fixup vector table? */
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ldrne r3, [r0] /* But if yes, fetch current value */
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ldrne r2, [r7, #(PCB_L1VEC)] /* Fetch new vector_page value */
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mcr p15, 0, r1, c3, c0, 0 /* Update DACR for lwp0's context */
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cmpne r3, r2 /* Stuffing the same value? */
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strne r2, [r0] /* Store if not. */
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#ifdef PMAP_INCLUDE_PTE_SYNC
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/*
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* Need to sync the cache to make sure that last store is
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* visible to the MMU.
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*/
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movne r1, #4
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movne lr, pc
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ldrne pc, [r9, #CF_DCACHE_WB_RANGE]
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#endif /* PMAP_INCLUDE_PTE_SYNC */
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/*
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* Note: We don't do the same optimisation as cpu_switch() with
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* respect to avoiding flushing the TLB if we're switching to
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* the same L1 since this process' VM space may be about to go
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* away, so we don't want *any* turds left in the TLB.
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*/
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/* Switch the memory to the new process */
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ldr r0, [r7, #(PCB_PAGEDIR)]
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mov lr, pc
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ldr pc, [r9, #CF_CONTEXT_SWITCH]
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/* Restore all the save registers */
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#ifndef _ARM_ARCH_5E
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add r1, r7, #PCB_R8
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ldmia r1, {r8-r13}
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#else
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ldr r8, [r7, #(PCB_R8)]
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ldr r9, [r7, #(PCB_R9)]
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ldr r10, [r7, #(PCB_R10)]
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ldr r11, [r7, #(PCB_R11)]
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ldr r12, [r7, #(PCB_R12)]
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ldr r13, [r7, #(PCB_SP)]
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#endif
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GET_PCPU(r6, r4)
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/* Hook in a new pcb */
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str r7, [r6, #PC_CURPCB]
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/* We have a new curthread now so make a note it */
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add r6, r6, #PC_CURTHREAD
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str r5, [r6]
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#ifndef ARM_TP_ADDRESS
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mcr p15, 0, r5, c13, c0, 4
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#endif
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/* Set the new tp */
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ldr r6, [r5, #(TD_MD + MD_TP)]
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#ifdef ARM_TP_ADDRESS
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ldr r4, =ARM_TP_ADDRESS
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str r6, [r4]
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ldr r6, [r5, #(TD_MD + MD_RAS_START)]
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str r6, [r4, #4] /* ARM_RAS_START */
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ldr r6, [r5, #(TD_MD + MD_RAS_END)]
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str r6, [r4, #8] /* ARM_RAS_END */
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#else
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mcr p15, 0, r6, c13, c0, 3
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#endif
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add sp, sp, #4;
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ldmfd sp!, {r4-r7, pc}
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END(cpu_throw)
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ENTRY(cpu_switch)
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stmfd sp!, {r4-r7, lr}
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sub sp, sp, #4;
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#ifdef __ARM_EABI__
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.save {r4-r7, lr}
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.pad #4
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#endif
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mov r6, r2 /* Save the mutex */
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.Lswitch_resume:
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/* rem: r0 = old lwp */
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/* rem: interrupts are disabled */
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/* Process is now on a processor. */
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/* We have a new curthread now so make a note it */
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GET_PCPU(r7, r2)
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str r1, [r7, #PC_CURTHREAD]
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#ifndef ARM_TP_ADDRESS
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mcr p15, 0, r1, c13, c0, 4
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#endif
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/* Hook in a new pcb */
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ldr r2, [r1, #TD_PCB]
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str r2, [r7, #PC_CURPCB]
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/* rem: r1 = new process */
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/* rem: interrupts are enabled */
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/* Stage two : Save old context */
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/* Get the user structure for the old thread. */
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ldr r2, [r0, #(TD_PCB)]
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mov r4, r0 /* Save the old thread. */
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/* Save all the registers in the old thread's pcb */
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#ifndef _ARM_ARCH_5E
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add r7, r2, #(PCB_R8)
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stmia r7, {r8-r13}
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#else
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strd r8, [r2, #(PCB_R8)]
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strd r10, [r2, #(PCB_R10)]
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strd r12, [r2, #(PCB_R12)]
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#endif
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str pc, [r2, #(PCB_PC)]
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/*
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* NOTE: We can now use r8-r13 until it is time to restore
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* them for the new process.
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*/
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#ifdef ARM_TP_ADDRESS
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/* Store the old tp */
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ldr r3, =ARM_TP_ADDRESS
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ldr r9, [r3]
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str r9, [r0, #(TD_MD + MD_TP)]
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ldr r9, [r3, #4]
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str r9, [r0, #(TD_MD + MD_RAS_START)]
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ldr r9, [r3, #8]
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str r9, [r0, #(TD_MD + MD_RAS_END)]
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/* Set the new tp */
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ldr r9, [r1, #(TD_MD + MD_TP)]
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str r9, [r3]
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ldr r9, [r1, #(TD_MD + MD_RAS_START)]
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str r9, [r3, #4]
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ldr r9, [r1, #(TD_MD + MD_RAS_END)]
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str r9, [r3, #8]
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#else
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/* Store the old tp */
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mrc p15, 0, r9, c13, c0, 3
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str r9, [r0, #(TD_MD + MD_TP)]
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/* Set the new tp */
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ldr r9, [r1, #(TD_MD + MD_TP)]
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mcr p15, 0, r9, c13, c0, 3
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#endif
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/* Get the user structure for the new process in r9 */
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ldr r9, [r1, #(TD_PCB)]
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/* rem: r2 = old PCB */
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/* rem: r9 = new PCB */
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/* rem: interrupts are enabled */
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#ifdef VFP
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fmrx r0, fpexc /* If the VFP is enabled */
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tst r0, #(VFPEXC_EN) /* the current thread has */
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movne r1, #1 /* used it, so go save */
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addne r0, r2, #(PCB_VFPSTATE) /* the state into the PCB */
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blne _C_LABEL(vfp_store) /* and disable the VFP. */
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#endif
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/* r0-r3 now free! */
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/* Third phase : restore saved context */
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/* rem: r2 = old PCB */
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/* rem: r9 = new PCB */
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/* rem: interrupts are enabled */
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ldr r5, [r9, #(PCB_DACR)] /* r5 = new DACR */
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mov r2, #DOMAIN_CLIENT
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cmp r5, r2, lsl #(PMAP_DOMAIN_KERNEL * 2) /* Sw to kernel thread? */
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beq .Lcs_context_switched /* Yup. Don't flush cache */
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mrc p15, 0, r0, c3, c0, 0 /* r0 = old DACR */
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/*
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* Get the new L1 table pointer into r11. If we're switching to
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* an LWP with the same address space as the outgoing one, we can
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* skip the cache purge and the TTB load.
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*
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* To avoid data dep stalls that would happen anyway, we try
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* and get some useful work done in the mean time.
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*/
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mrc p15, 0, r10, c2, c0, 0 /* r10 = old L1 */
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ldr r11, [r9, #(PCB_PAGEDIR)] /* r11 = new L1 */
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teq r10, r11 /* Same L1? */
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cmpeq r0, r5 /* Same DACR? */
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beq .Lcs_context_switched /* yes! */
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#if !defined(CPU_ARM11) && !defined(CPU_CORTEXA) && !defined(CPU_MV_PJ4B) && !defined(CPU_KRAIT)
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/*
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* Definately need to flush the cache.
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*/
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ldr r1, .Lcpufuncs
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mov lr, pc
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ldr pc, [r1, #CF_IDCACHE_WBINV_ALL]
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#endif
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.Lcs_cache_purge_skipped:
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/* rem: r6 = lock */
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/* rem: r9 = new PCB */
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/* rem: r10 = old L1 */
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/* rem: r11 = new L1 */
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mov r2, #0x00000000
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ldr r7, [r9, #(PCB_PL1VEC)]
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/*
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* Ensure the vector table is accessible by fixing up the L1
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*/
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cmp r7, #0 /* No need to fixup vector table? */
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ldrne r2, [r7] /* But if yes, fetch current value */
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ldrne r0, [r9, #(PCB_L1VEC)] /* Fetch new vector_page value */
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mcr p15, 0, r5, c3, c0, 0 /* Update DACR for new context */
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cmpne r2, r0 /* Stuffing the same value? */
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#ifndef PMAP_INCLUDE_PTE_SYNC
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strne r0, [r7] /* Nope, update it */
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#else
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beq .Lcs_same_vector
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str r0, [r7] /* Otherwise, update it */
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/*
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* Need to sync the cache to make sure that last store is
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* visible to the MMU.
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*/
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ldr r2, .Lcpufuncs
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mov r0, r7
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mov r1, #4
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mov lr, pc
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ldr pc, [r2, #CF_DCACHE_WB_RANGE]
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.Lcs_same_vector:
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#endif /* PMAP_INCLUDE_PTE_SYNC */
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cmp r10, r11 /* Switching to the same L1? */
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ldr r10, .Lcpufuncs
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beq .Lcs_same_l1 /* Yup. */
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/*
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* Do a full context switch, including full TLB flush.
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*/
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mov r0, r11
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mov lr, pc
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ldr pc, [r10, #CF_CONTEXT_SWITCH]
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b .Lcs_context_switched
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/*
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* We're switching to a different process in the same L1.
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* In this situation, we only need to flush the TLB for the
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* vector_page mapping, and even then only if r7 is non-NULL.
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*/
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.Lcs_same_l1:
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cmp r7, #0
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movne r0, #0 /* We *know* vector_page's VA is 0x0 */
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movne lr, pc
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ldrne pc, [r10, #CF_TLB_FLUSHID_SE]
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.Lcs_context_switched:
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/* Release the old thread */
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str r6, [r4, #TD_LOCK]
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#if defined(SCHED_ULE) && defined(SMP)
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ldr r6, .Lblocked_lock
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GET_CURTHREAD_PTR(r3)
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1:
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ldr r4, [r3, #TD_LOCK]
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cmp r4, r6
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beq 1b
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#endif
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/* XXXSCW: Safe to re-enable FIQs here */
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/* rem: r9 = new PCB */
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/* Restore all the save registers */
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#ifndef _ARM_ARCH_5E
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add r7, r9, #PCB_R8
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ldmia r7, {r8-r13}
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sub r7, r7, #PCB_R8 /* restore PCB pointer */
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#else
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mov r7, r9
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ldr r8, [r7, #(PCB_R8)]
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ldr r9, [r7, #(PCB_R9)]
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ldr r10, [r7, #(PCB_R10)]
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ldr r11, [r7, #(PCB_R11)]
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ldr r12, [r7, #(PCB_R12)]
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ldr r13, [r7, #(PCB_SP)]
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#endif
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/* rem: r5 = new lwp's proc */
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/* rem: r6 = lock */
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/* rem: r7 = new PCB */
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.Lswitch_return:
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/*
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* Pull the registers that got pushed when either savectx() or
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* cpu_switch() was called and return.
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*/
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add sp, sp, #4;
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ldmfd sp!, {r4-r7, pc}
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#ifdef DIAGNOSTIC
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.Lswitch_bogons:
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adr r0, .Lswitch_panic_str
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bl _C_LABEL(panic)
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1: nop
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b 1b
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.Lswitch_panic_str:
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.asciz "cpu_switch: sched_qs empty with non-zero sched_whichqs!\n"
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#endif
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END(cpu_switch)
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ENTRY(savectx)
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stmfd sp!, {r4-r7, lr}
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sub sp, sp, #4
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/*
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* r0 = pcb
|
|
*/
|
|
/* Store all the registers in the process's pcb */
|
|
add r2, r0, #(PCB_R8)
|
|
stmia r2, {r8-r13}
|
|
#ifdef VFP
|
|
fmrx r2, fpexc /* If the VFP is enabled */
|
|
tst r2, #(VFPEXC_EN) /* the current thread has */
|
|
movne r1, #1 /* used it, so go save */
|
|
addne r0, r0, #(PCB_VFPSTATE) /* the state into the PCB */
|
|
blne _C_LABEL(vfp_store) /* and disable the VFP. */
|
|
#endif
|
|
add sp, sp, #4;
|
|
ldmfd sp!, {r4-r7, pc}
|
|
END(savectx)
|
|
|
|
ENTRY(fork_trampoline)
|
|
STOP_UNWINDING /* EABI: Don't unwind beyond the thread enty point. */
|
|
mov fp, #0 /* OABI: Stack traceback via fp stops here. */
|
|
mov r2, sp
|
|
mov r1, r5
|
|
mov r0, r4
|
|
ldr lr, =swi_exit /* Go finish forking, then return */
|
|
b _C_LABEL(fork_exit) /* to userland via swi_exit code. */
|
|
END(fork_trampoline)
|
|
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