718c2b5b11
reading registers from other CPUs. As it turns out, the hardware doesn't really like concurrent IPI'ing causing adverse effects. Also the thought deadlock when using this spin lock here and the targeted CPU(s) are also holding or in case of nested locks can't actually happen. This is due to the fact that on sparc64, spinlock_enter() only raises the PIL but doesn't disable interrupts completely. Thus direct cross calls as used for the register reading (and all other MD IPI needs) still will be executed by the targeted CPU(s) in that case. MFC after: 3 days
383 lines
8.1 KiB
C
383 lines
8.1 KiB
C
/*-
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* Copyright (c) 2001 Jake Burkholder.
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* Copyright (c) 2007 - 2011 Marius Strobl <marius@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _MACHINE_SMP_H_
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#define _MACHINE_SMP_H_
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#ifdef SMP
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#define CPU_TICKSYNC 1
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#define CPU_STICKSYNC 2
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#define CPU_INIT 3
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#define CPU_BOOTSTRAP 4
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#ifndef LOCORE
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#include <sys/cpuset.h>
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#include <sys/proc.h>
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#include <sys/sched.h>
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#include <sys/smp.h>
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#include <machine/intr_machdep.h>
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#include <machine/pcb.h>
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#include <machine/tte.h>
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#define IDR_BUSY 0x0000000000000001ULL
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#define IDR_NACK 0x0000000000000002ULL
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#define IDR_CHEETAH_ALL_BUSY 0x5555555555555555ULL
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#define IDR_CHEETAH_ALL_NACK (~IDR_CHEETAH_ALL_BUSY)
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#define IDR_CHEETAH_MAX_BN_PAIRS 32
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#define IDR_JALAPENO_MAX_BN_PAIRS 4
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#define IDC_ITID_SHIFT 14
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#define IDC_BN_SHIFT 24
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#define IPI_AST PIL_AST
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#define IPI_RENDEZVOUS PIL_RENDEZVOUS
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#define IPI_PREEMPT PIL_PREEMPT
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#define IPI_HARDCLOCK PIL_HARDCLOCK
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#define IPI_STOP PIL_STOP
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#define IPI_STOP_HARD PIL_STOP
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#define IPI_RETRIES 5000
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struct cpu_start_args {
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u_int csa_count;
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u_int csa_mid;
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u_int csa_state;
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vm_offset_t csa_pcpu;
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u_long csa_tick;
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u_long csa_stick;
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u_long csa_ver;
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struct tte csa_ttes[PCPU_PAGES];
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};
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struct ipi_cache_args {
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cpuset_t ica_mask;
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vm_paddr_t ica_pa;
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};
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struct ipi_rd_args {
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cpuset_t ira_mask;
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register_t *ira_val;
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};
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struct ipi_tlb_args {
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cpuset_t ita_mask;
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struct pmap *ita_pmap;
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u_long ita_start;
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u_long ita_end;
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};
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#define ita_va ita_start
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struct pcpu;
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extern struct pcb stoppcbs[];
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void cpu_mp_bootstrap(struct pcpu *pc);
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void cpu_mp_shutdown(void);
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typedef void cpu_ipi_selected_t(cpuset_t, u_long, u_long, u_long);
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extern cpu_ipi_selected_t *cpu_ipi_selected;
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typedef void cpu_ipi_single_t(u_int, u_long, u_long, u_long);
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extern cpu_ipi_single_t *cpu_ipi_single;
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void mp_init(u_int cpu_impl);
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extern struct ipi_cache_args ipi_cache_args;
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extern struct ipi_rd_args ipi_rd_args;
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extern struct ipi_tlb_args ipi_tlb_args;
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extern char *mp_tramp_code;
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extern u_long mp_tramp_code_len;
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extern u_long mp_tramp_tlb_slots;
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extern u_long mp_tramp_func;
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extern void mp_startup(void);
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extern char tl_ipi_cheetah_dcache_page_inval[];
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extern char tl_ipi_spitfire_dcache_page_inval[];
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extern char tl_ipi_spitfire_icache_page_inval[];
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extern char tl_ipi_level[];
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extern char tl_ipi_stick_rd[];
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extern char tl_ipi_tick_rd[];
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extern char tl_ipi_tlb_context_demap[];
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extern char tl_ipi_tlb_page_demap[];
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extern char tl_ipi_tlb_range_demap[];
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static __inline void
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ipi_all_but_self(u_int ipi)
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{
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cpuset_t cpus;
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cpus = all_cpus;
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CPU_CLR(PCPU_GET(cpuid), &cpus);
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cpu_ipi_selected(cpus, 0, (u_long)tl_ipi_level, ipi);
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}
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static __inline void
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ipi_selected(cpuset_t cpus, u_int ipi)
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{
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cpu_ipi_selected(cpus, 0, (u_long)tl_ipi_level, ipi);
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}
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static __inline void
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ipi_cpu(int cpu, u_int ipi)
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{
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cpu_ipi_single(cpu, 0, (u_long)tl_ipi_level, ipi);
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}
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#if defined(_MACHINE_PMAP_H_) && defined(_SYS_MUTEX_H_)
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static __inline void *
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ipi_dcache_page_inval(void *func, vm_paddr_t pa)
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{
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struct ipi_cache_args *ica;
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if (smp_cpus == 1)
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return (NULL);
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sched_pin();
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ica = &ipi_cache_args;
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mtx_lock_spin(&smp_ipi_mtx);
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ica->ica_mask = all_cpus;
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CPU_CLR(PCPU_GET(cpuid), &ica->ica_mask);
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ica->ica_pa = pa;
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cpu_ipi_selected(ica->ica_mask, 0, (u_long)func, (u_long)ica);
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return (&ica->ica_mask);
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}
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static __inline void *
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ipi_icache_page_inval(void *func, vm_paddr_t pa)
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{
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struct ipi_cache_args *ica;
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if (smp_cpus == 1)
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return (NULL);
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sched_pin();
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ica = &ipi_cache_args;
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mtx_lock_spin(&smp_ipi_mtx);
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ica->ica_mask = all_cpus;
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CPU_CLR(PCPU_GET(cpuid), &ica->ica_mask);
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ica->ica_pa = pa;
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cpu_ipi_selected(ica->ica_mask, 0, (u_long)func, (u_long)ica);
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return (&ica->ica_mask);
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}
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static __inline void *
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ipi_rd(u_int cpu, void *func, u_long *val)
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{
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struct ipi_rd_args *ira;
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if (smp_cpus == 1)
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return (NULL);
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sched_pin();
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ira = &ipi_rd_args;
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mtx_lock_spin(&smp_ipi_mtx);
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CPU_SETOF(cpu, &ira->ira_mask);
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ira->ira_val = val;
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cpu_ipi_single(cpu, 0, (u_long)func, (u_long)ira);
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return (&ira->ira_mask);
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}
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static __inline void *
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ipi_tlb_context_demap(struct pmap *pm)
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{
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struct ipi_tlb_args *ita;
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cpuset_t cpus;
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if (smp_cpus == 1)
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return (NULL);
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sched_pin();
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cpus = pm->pm_active;
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CPU_AND(&cpus, &all_cpus);
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CPU_CLR(PCPU_GET(cpuid), &cpus);
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if (CPU_EMPTY(&cpus)) {
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sched_unpin();
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return (NULL);
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}
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ita = &ipi_tlb_args;
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mtx_lock_spin(&smp_ipi_mtx);
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ita->ita_mask = cpus;
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ita->ita_pmap = pm;
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cpu_ipi_selected(cpus, 0, (u_long)tl_ipi_tlb_context_demap,
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(u_long)ita);
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return (&ita->ita_mask);
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}
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static __inline void *
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ipi_tlb_page_demap(struct pmap *pm, vm_offset_t va)
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{
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struct ipi_tlb_args *ita;
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cpuset_t cpus;
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if (smp_cpus == 1)
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return (NULL);
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sched_pin();
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cpus = pm->pm_active;
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CPU_AND(&cpus, &all_cpus);
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CPU_CLR(PCPU_GET(cpuid), &cpus);
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if (CPU_EMPTY(&cpus)) {
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sched_unpin();
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return (NULL);
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}
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ita = &ipi_tlb_args;
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mtx_lock_spin(&smp_ipi_mtx);
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ita->ita_mask = cpus;
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ita->ita_pmap = pm;
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ita->ita_va = va;
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cpu_ipi_selected(cpus, 0, (u_long)tl_ipi_tlb_page_demap, (u_long)ita);
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return (&ita->ita_mask);
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}
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static __inline void *
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ipi_tlb_range_demap(struct pmap *pm, vm_offset_t start, vm_offset_t end)
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{
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struct ipi_tlb_args *ita;
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cpuset_t cpus;
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if (smp_cpus == 1)
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return (NULL);
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sched_pin();
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cpus = pm->pm_active;
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CPU_AND(&cpus, &all_cpus);
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CPU_CLR(PCPU_GET(cpuid), &cpus);
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if (CPU_EMPTY(&cpus)) {
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sched_unpin();
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return (NULL);
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}
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ita = &ipi_tlb_args;
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mtx_lock_spin(&smp_ipi_mtx);
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ita->ita_mask = cpus;
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ita->ita_pmap = pm;
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ita->ita_start = start;
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ita->ita_end = end;
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cpu_ipi_selected(cpus, 0, (u_long)tl_ipi_tlb_range_demap,
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(u_long)ita);
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return (&ita->ita_mask);
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}
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static __inline void
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ipi_wait(void *cookie)
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{
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volatile cpuset_t *mask;
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if ((mask = cookie) != NULL) {
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while (!CPU_EMPTY(mask))
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;
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mtx_unlock_spin(&smp_ipi_mtx);
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sched_unpin();
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}
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}
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#endif /* _MACHINE_PMAP_H_ && _SYS_MUTEX_H_ */
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#endif /* !LOCORE */
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#else
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#ifndef LOCORE
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static __inline void *
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ipi_dcache_page_inval(void *func __unused, vm_paddr_t pa __unused)
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{
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return (NULL);
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}
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static __inline void *
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ipi_icache_page_inval(void *func __unused, vm_paddr_t pa __unused)
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{
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return (NULL);
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}
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static __inline void *
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ipi_rd(u_int cpu __unused, void *func __unused, u_long *val __unused)
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{
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return (NULL);
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}
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static __inline void *
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ipi_tlb_context_demap(struct pmap *pm __unused)
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{
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return (NULL);
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}
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static __inline void *
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ipi_tlb_page_demap(struct pmap *pm __unused, vm_offset_t va __unused)
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{
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return (NULL);
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}
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static __inline void *
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ipi_tlb_range_demap(struct pmap *pm __unused, vm_offset_t start __unused,
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__unused vm_offset_t end)
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{
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return (NULL);
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}
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static __inline void
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ipi_wait(void *cookie __unused)
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{
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}
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static __inline void
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tl_ipi_cheetah_dcache_page_inval(void)
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{
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}
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static __inline void
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tl_ipi_spitfire_dcache_page_inval(void)
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{
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}
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static __inline void
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tl_ipi_spitfire_icache_page_inval(void)
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{
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}
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#endif /* !LOCORE */
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#endif /* SMP */
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#endif /* !_MACHINE_SMP_H_ */
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