1ac4b82b11
controllers. It currently supports the P, PL, PD and PU variants, with more to be supported shortly.
354 lines
12 KiB
C
354 lines
12 KiB
C
/*-
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* Copyright (c) 1999 Michael Smith
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/*
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* We could actually use all 33 segments, but using only 32 means that
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* each scatter/gather map is 256 bytes in size, and thus we don't have to worry about
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* maps crossing page boundaries.
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*/
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#define MLX_NSEG 32 /* max scatter/gather segments we use */
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#define MLX_NSLOTS 256 /* max number of command slots */
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#define MLX_CFG_BASE0 0x10 /* first region */
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#define MLX_CFG_BASE1 0x14 /* second region (type 3 only) */
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#define MLX_MAXDRIVES 32
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#define MLX_BLKSIZE 512 /* fixed feature */
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/*
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* Structure describing a System Drive as attached to the controller.
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*/
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struct mlx_sysdrive
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{
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/* from MLX_CMD_ENQSYSDRIVE */
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u_int32_t ms_size;
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int ms_state;
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int ms_raidlevel;
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/* synthetic geometry */
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int ms_cylinders;
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int ms_heads;
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int ms_sectors;
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/* handle for attached driver */
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device_t ms_disk;
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};
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/*
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* Per-command control structure.
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*/
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struct mlx_command
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{
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TAILQ_ENTRY(mlx_command) mc_link; /* list linkage */
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struct mlx_softc *mc_sc; /* controller that owns us */
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u_int8_t mc_slot; /* command slot we occupy */
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u_int16_t mc_status; /* command completion status */
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u_int8_t mc_mailbox[16]; /* command mailbox */
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u_int32_t mc_sgphys; /* physical address of s/g array in controller space */
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int mc_nsgent; /* number of entries in s/g map */
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int mc_flags;
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#define MLX_CMD_DATAIN (1<<0)
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#define MLX_CMD_DATAOUT (1<<1)
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#define MLX_CMD_PRIORITY (1<<2) /* high-priority command */
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void *mc_data; /* data buffer */
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size_t mc_length;
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bus_dmamap_t mc_dmamap; /* DMA map for data */
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u_int32_t mc_dataphys; /* data buffer base address controller space */
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void (* mc_complete)(struct mlx_command *mc); /* completion handler */
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void *mc_private; /* submitter-private data or wait channel */
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};
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/*
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* Per-controller structure.
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*/
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struct mlx_softc
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{
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/* bus connections */
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device_t mlx_dev;
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struct resource *mlx_mem; /* mailbox interface window */
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bus_space_handle_t mlx_bhandle; /* bus space handle */
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bus_space_tag_t mlx_btag; /* bus space tag */
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bus_dma_tag_t mlx_parent_dmat;/* parent DMA tag */
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bus_dma_tag_t mlx_buffer_dmat;/* data buffer DMA tag */
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struct resource *mlx_irq; /* interrupt */
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void *mlx_intr; /* interrupt handle */
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/* scatter/gather lists and their controller-visible mappings */
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struct mlx_sgentry *mlx_sgtable; /* s/g lists */
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u_int32_t mlx_sgbusaddr; /* s/g table base address in bus space */
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bus_dma_tag_t mlx_sg_dmat; /* s/g buffer DMA tag */
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bus_dmamap_t mlx_sg_dmamap; /* map for s/g buffers */
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/* controller limits and features */
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int mlx_hwid; /* hardware identifier */
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int mlx_maxiop; /* maximum number of I/O operations */
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int mlx_nchan; /* number of active channels */
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int mlx_maxiosize; /* largest I/O for this controller */
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int mlx_maxtarg; /* maximum number of targets per channel */
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int mlx_maxtags; /* maximum number of tags per device */
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int mlx_scsicap; /* SCSI capabilities */
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int mlx_feature; /* controller features/quirks */
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#define MLX_FEAT_PAUSEWORKS (1<<0) /* channel pause works as expected */
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/* controller queues and arrays */
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TAILQ_HEAD(, mlx_command) mlx_freecmds; /* command structures available for reuse */
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TAILQ_HEAD(, mlx_command) mlx_donecmd; /* commands waiting for completion processing */
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struct mlx_command *mlx_busycmd[MLX_NSLOTS]; /* busy commands */
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int mlx_busycmds; /* count of busy commands */
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struct mlx_sysdrive mlx_sysdrive[MLX_MAXDRIVES]; /* system drives */
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struct buf_queue_head mlx_bufq; /* outstanding I/O operations */
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int mlx_waitbufs; /* number of bufs awaiting commands */
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/* controller status */
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u_int8_t mlx_fwminor; /* firmware revision */
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u_int8_t mlx_fwmajor;
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int mlx_geom;
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#define MLX_GEOM_128_32 0 /* geoemetry translation modes */
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#define MLX_GEOM_256_63 1
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int mlx_state;
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#define MLX_STATE_INTEN (1<<0) /* interrupts have been enabled */
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#define MLX_STATE_SHUTDOWN (1<<1) /* controller is shut down */
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#define MLX_STATE_OPEN (1<<2) /* control device is open */
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#define MLX_STATE_SUSPEND (1<<3) /* controller is suspended */
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struct callout_handle mlx_timeout; /* periodic status monitor */
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time_t mlx_lastpoll; /* last time_second we polled for status */
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u_int16_t mlx_lastevent; /* sequence number of the last event we recorded */
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u_int16_t mlx_currevent; /* sequence number last time we looked */
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int mlx_polling; /* if > 0, polling operations still running */
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int mlx_rebuild; /* if >= 0, drive is being rebuilt */
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u_int32_t mlx_rebuildstat;/* blocks left to rebuild if active */
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int mlx_check; /* if >= 0, drive is being checked */
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struct mlx_pause mlx_pause; /* pending pause operation details */
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/* interface-specific accessor functions */
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int mlx_iftype; /* interface protocol */
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#define MLX_IFTYPE_3 3
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#define MLX_IFTYPE_4 4
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#define MLX_IFTYPE_5 5
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int (* mlx_tryqueue)(struct mlx_softc *sc, struct mlx_command *mc);
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int (* mlx_findcomplete)(struct mlx_softc *sc, u_int8_t *slot, u_int16_t *status);
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void (* mlx_intaction)(struct mlx_softc *sc, int action);
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#define MLX_INTACTION_DISABLE 0
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#define MLX_INTACTION_ENABLE 1
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#define MLX_INTACTION_ACKNOWLEDGE 2
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};
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/*
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* Interface between bus connections and driver core.
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*/
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extern void mlx_free(struct mlx_softc *sc);
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extern int mlx_attach(struct mlx_softc *sc);
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extern void mlx_startup(struct mlx_softc *sc);
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extern void mlx_intr(void *data);
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extern int mlx_detach(device_t dev);
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extern int mlx_shutdown(device_t dev);
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extern int mlx_suspend(device_t dev);
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extern int mlx_resume(device_t dev);
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extern d_open_t mlx_open;
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extern d_close_t mlx_close;
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extern d_ioctl_t mlx_ioctl;
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extern devclass_t mlx_devclass;
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/*
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* Mylex System Disk driver
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*/
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struct mlxd_softc
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{
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device_t mlxd_dev;
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struct mlx_softc *mlxd_controller;
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struct mlx_sysdrive *mlxd_drive;
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struct disk mlxd_disk;
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struct devstat mlxd_stats;
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struct disklabel mlxd_label;
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int mlxd_unit;
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int mlxd_flags;
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#define MLXD_OPEN (1<<0) /* drive is open (can't shut down) */
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};
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/*
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* Interface between driver core and disk driver (should be using a bus?)
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*/
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extern int mlx_submit_buf(struct mlx_softc *sc, struct buf *bp);
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extern int mlx_submit_ioctl(struct mlx_softc *sc, struct mlx_sysdrive *drive, u_long cmd,
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caddr_t addr, int32_t flag, struct proc *p);
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extern void mlxd_intr(void *data);
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/*
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* Accessor defines for the V3 interface.
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*/
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#define MLX_V3_MAILBOX 0x00
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#define MLX_V3_STATUS_IDENT 0x0d
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#define MLX_V3_STATUS 0x0e
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#define MLX_V3_IDBR 0x40
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#define MLX_V3_ODBR 0x41
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#define MLX_V3_IER 0x43
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#define MLX_V3_PUT_MAILBOX(sc, idx, val) bus_space_write_1(sc->mlx_btag, sc->mlx_bhandle, MLX_V3_MAILBOX + idx, val)
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#define MLX_V3_GET_STATUS_IDENT(sc) bus_space_read_1 (sc->mlx_btag, sc->mlx_bhandle, MLX_V3_STATUS_IDENT)
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#define MLX_V3_GET_STATUS(sc) bus_space_read_2 (sc->mlx_btag, sc->mlx_bhandle, MLX_V3_STATUS)
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#define MLX_V3_GET_IDBR(sc) bus_space_read_1 (sc->mlx_btag, sc->mlx_bhandle, MLX_V3_IDBR)
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#define MLX_V3_PUT_IDBR(sc, val) bus_space_write_1(sc->mlx_btag, sc->mlx_bhandle, MLX_V3_IDBR, val)
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#define MLX_V3_GET_ODBR(sc) bus_space_read_1 (sc->mlx_btag, sc->mlx_bhandle, MLX_V3_ODBR)
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#define MLX_V3_PUT_ODBR(sc, val) bus_space_write_1(sc->mlx_btag, sc->mlx_bhandle, MLX_V3_ODBR, val)
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#define MLX_V3_PUT_IER(sc, val) bus_space_write_1(sc->mlx_btag, sc->mlx_bhandle, MLX_V3_IER, val)
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#define MLX_V3_IDB_FULL (1<<0) /* mailbox is full */
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#define MLX_V3_IDB_SACK (1<<1) /* acknowledge status read */
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#define MLX_V3_IDB_RESET (1<<3) /* request soft reset */
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#define MLX_V3_ODB_SAVAIL (1<<0) /* status is available */
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/*
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* Inlines to build various command structures
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*/
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static __inline void
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mlx_make_type1(struct mlx_command *mc,
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u_int8_t code,
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u_int16_t f1,
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u_int32_t f2,
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u_int8_t f3,
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u_int32_t f4,
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u_int8_t f5)
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{
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mc->mc_mailbox[0x0] = code;
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mc->mc_mailbox[0x2] = f1 & 0xff;
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mc->mc_mailbox[0x3] = (((f2 >> 24) & 0x3) << 6) | ((f1 >> 8) & 0x3f);
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mc->mc_mailbox[0x4] = f2 & 0xff;
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mc->mc_mailbox[0x5] = (f2 >> 8) & 0xff;
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mc->mc_mailbox[0x6] = (f2 >> 16) & 0xff;
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mc->mc_mailbox[0x7] = f3;
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mc->mc_mailbox[0x8] = f4 & 0xff;
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mc->mc_mailbox[0x9] = (f4 >> 8) & 0xff;
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mc->mc_mailbox[0xa] = (f4 >> 16) & 0xff;
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mc->mc_mailbox[0xb] = (f4 >> 24) & 0xff;
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mc->mc_mailbox[0xc] = f5;
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}
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static __inline void
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mlx_make_type2(struct mlx_command *mc,
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u_int8_t code,
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u_int8_t f1,
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u_int8_t f2,
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u_int8_t f3,
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u_int8_t f4,
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u_int8_t f5,
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u_int8_t f6,
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u_int32_t f7,
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u_int8_t f8)
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{
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mc->mc_mailbox[0x0] = code;
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mc->mc_mailbox[0x2] = f1;
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mc->mc_mailbox[0x3] = f2;
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mc->mc_mailbox[0x4] = f3;
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mc->mc_mailbox[0x5] = f4;
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mc->mc_mailbox[0x6] = f5;
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mc->mc_mailbox[0x7] = f6;
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mc->mc_mailbox[0x8] = f7 & 0xff;
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mc->mc_mailbox[0x9] = (f7 >> 8) & 0xff;
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mc->mc_mailbox[0xa] = (f7 >> 16) & 0xff;
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mc->mc_mailbox[0xb] = (f7 >> 24) & 0xff;
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mc->mc_mailbox[0xc] = f8;
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}
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static __inline void
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mlx_make_type3(struct mlx_command *mc,
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u_int8_t code,
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u_int8_t f1,
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u_int8_t f2,
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u_int16_t f3,
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u_int8_t f4,
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u_int8_t f5,
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u_int32_t f6,
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u_int8_t f7)
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{
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mc->mc_mailbox[0x0] = code;
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mc->mc_mailbox[0x2] = f1;
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mc->mc_mailbox[0x3] = f2;
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mc->mc_mailbox[0x4] = f3 & 0xff;
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mc->mc_mailbox[0x5] = (f3 >> 8) & 0xff;
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mc->mc_mailbox[0x6] = f4;
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mc->mc_mailbox[0x7] = f5;
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mc->mc_mailbox[0x8] = f6 & 0xff;
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mc->mc_mailbox[0x9] = (f6 >> 8) & 0xff;
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mc->mc_mailbox[0xa] = (f6 >> 16) & 0xff;
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mc->mc_mailbox[0xb] = (f6 >> 24) & 0xff;
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mc->mc_mailbox[0xc] = f7;
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}
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static __inline void
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mlx_make_type4(struct mlx_command *mc,
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u_int8_t code,
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u_int16_t f1,
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u_int32_t f2,
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u_int32_t f3,
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u_int8_t f4)
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{
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mc->mc_mailbox[0x0] = code;
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mc->mc_mailbox[0x2] = f1 & 0xff;
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mc->mc_mailbox[0x3] = (f1 >> 8) & 0xff;
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mc->mc_mailbox[0x4] = f2 & 0xff;
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mc->mc_mailbox[0x5] = (f2 >> 8) & 0xff;
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mc->mc_mailbox[0x6] = (f2 >> 16) & 0xff;
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mc->mc_mailbox[0x7] = (f2 >> 24) & 0xff;
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mc->mc_mailbox[0x8] = f3 & 0xff;
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mc->mc_mailbox[0x9] = (f3 >> 8) & 0xff;
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mc->mc_mailbox[0xa] = (f3 >> 16) & 0xff;
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mc->mc_mailbox[0xb] = (f3 >> 24) & 0xff;
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mc->mc_mailbox[0xc] = f4;
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}
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static __inline void
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mlx_make_type5(struct mlx_command *mc,
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u_int8_t code,
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u_int8_t f1,
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u_int8_t f2,
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u_int32_t f3,
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u_int32_t f4,
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u_int8_t f5)
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{
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mc->mc_mailbox[0x0] = code;
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mc->mc_mailbox[0x2] = f1;
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mc->mc_mailbox[0x3] = f2;
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mc->mc_mailbox[0x4] = f3 & 0xff;
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mc->mc_mailbox[0x5] = (f3 >> 8) & 0xff;
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mc->mc_mailbox[0x6] = (f3 >> 16) & 0xff;
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mc->mc_mailbox[0x7] = (f3 >> 24) & 0xff;
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mc->mc_mailbox[0x8] = f4 & 0xff;
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mc->mc_mailbox[0x9] = (f4 >> 8) & 0xff;
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mc->mc_mailbox[0xa] = (f4 >> 16) & 0xff;
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mc->mc_mailbox[0xb] = (f4 >> 24) & 0xff;
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mc->mc_mailbox[0xc] = f5;
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}
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